Home
last modified time | relevance | path

Searched refs:BIT (Results 1 – 200 of 1896) sorted by relevance

12345678910

/linux-4.1.27/drivers/staging/rtl8723au/include/
Drtl8723a_spec.h482 #define CmdEEPROM_En BIT(5)
485 #define CmdEERPOMSEL BIT(4)
486 #define Cmd9346CR_9356SEL BIT(4)
494 #define GPIOSEL_ENBT BIT(5)
536 #define RRSR_1M BIT(0)
537 #define RRSR_2M BIT(1)
538 #define RRSR_5_5M BIT(2)
539 #define RRSR_11M BIT(3)
540 #define RRSR_6M BIT(4)
541 #define RRSR_9M BIT(5)
[all …]
DHal8723PwrSeq.h42 …K, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] …
43 …{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(…
45 …{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(…
46 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(…
47 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait til…
48 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release …
49 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(…
50 …, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},/* disab…
51 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* polling …
52 …UT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},/**/ \
[all …]
Dodm_debug.h68 #define ODM_COMP_DIG BIT(0)
69 #define ODM_COMP_RA_MASK BIT(1)
70 #define ODM_COMP_DYNAMIC_TXPWR BIT(2)
71 #define ODM_COMP_FA_CNT BIT(3)
72 #define ODM_COMP_RSSI_MONITOR BIT(4)
73 #define ODM_COMP_CCK_PD BIT(5)
74 #define ODM_COMP_ANT_DIV BIT(6)
75 #define ODM_COMP_PWR_SAVE BIT(7)
76 #define ODM_COMP_PWR_TRAIN BIT(8)
77 #define ODM_COMP_RATE_ADAPTIVE BIT(9)
[all …]
DHalPwrSeqCmd.h67 #define PWR_INTF_SDIO_MSK BIT(0)
68 #define PWR_INTF_USB_MSK BIT(1)
69 #define PWR_INTF_PCI_MSK BIT(2)
70 #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
75 #define PWR_FAB_TSMC_MSK BIT(0)
76 #define PWR_FAB_UMC_MSK BIT(1)
77 #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
82 #define PWR_CUT_TESTCHIP_MSK BIT(0)
83 #define PWR_CUT_A_MSK BIT(1)
84 #define PWR_CUT_B_MSK BIT(2)
[all …]
Drtw_debug.h31 #define _module_rtl871x_xmit_c_ BIT(0)
32 #define _module_xmit_osdep_c_ BIT(1)
33 #define _module_rtl871x_recv_c_ BIT(2)
34 #define _module_recv_osdep_c_ BIT(3)
35 #define _module_rtl871x_mlme_c_ BIT(4)
36 #define _module_mlme_osdep_c_ BIT(5)
37 #define _module_rtl871x_sta_mgt_c_ BIT(6)
38 #define _module_rtl871x_cmd_c_ BIT(7)
39 #define _module_cmd_osdep_c_ BIT(8)
40 #define _module_rtl871x_io_c_ BIT(9)
[all …]
Drtw_pwrctrl.h36 #define XMIT_ALIVE BIT(0)
37 #define RECV_ALIVE BIT(1)
38 #define CMD_ALIVE BIT(2)
39 #define EVT_ALIVE BIT(3)
62 #define PS_DPS BIT(0)
64 #define PS_RF_OFF BIT(1)
65 #define PS_ALL_ON BIT(2)
66 #define PS_ST_ACTIVE BIT(3)
68 #define PS_ISR_ENABLE BIT(4)
69 #define PS_IMR_ENABLE BIT(5)
[all …]
Dieee80211.h33 #define WLAN_STA_AUTH BIT(0)
34 #define WLAN_STA_ASSOC BIT(1)
35 #define WLAN_STA_PS BIT(2)
36 #define WLAN_STA_TIM BIT(3)
37 #define WLAN_STA_PERM BIT(4)
38 #define WLAN_STA_AUTHORIZED BIT(5)
39 #define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */
40 #define WLAN_STA_SHORT_PREAMBLE BIT(7)
41 #define WLAN_STA_PREAUTH BIT(8)
42 #define WLAN_STA_WME BIT(9)
[all …]
/linux-4.1.27/include/linux/mfd/abx500/
Dab8500-sysctrl.h89 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
90 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
91 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
92 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)
93 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
94 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)
95 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
97 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
98 #define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
103 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)
[all …]
/linux-4.1.27/drivers/scsi/
Dnsp32.h92 # define IRQSTATUS_LATCHED_MSG BIT(0)
93 # define IRQSTATUS_LATCHED_IO BIT(1)
94 # define IRQSTATUS_LATCHED_CD BIT(2)
95 # define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
96 # define IRQSTATUS_RESELECT_OCCUER BIT(4)
97 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
98 # define IRQSTATUS_SCSIRESET_IRQ BIT(6)
99 # define IRQSTATUS_TIMER_IRQ BIT(7)
100 # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
101 # define IRQSTATUS_PCI_IRQ BIT(9)
[all …]
Daha1542.h9 #define STST BIT(7) /* Self Test in Progress */
10 #define DIAGF BIT(6) /* Internal Diagnostic Failure */
11 #define INIT BIT(5) /* Mailbox Initialization Required */
12 #define IDLE BIT(4) /* SCSI Host Adapter Idle */
13 #define CDF BIT(3) /* Command/Data Out Port Full */
14 #define DF BIT(2) /* Data In Port Full */
16 #define INVDCMD BIT(0) /* Invalid H A Command */
20 #define ANYINTR BIT(7) /* Any Interrupt */
21 #define SCRD BIT(3) /* SCSI Reset Detected */
22 #define HACC BIT(2) /* HA Command Complete */
[all …]
/linux-4.1.27/drivers/pinctrl/sirf/
Dpinctrl-prima2.c138 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
139 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
140 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
141 BIT(17) | BIT(18),
144 .mask = BIT(31),
152 .funcmask = BIT(4),
162 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
163 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
164 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
165 BIT(17) | BIT(18),
[all …]
Dpinctrl-atlas6.c134 .mask = BIT(30) | BIT(31),
137 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
138 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
139 BIT(16) | BIT(17) | BIT(18) | BIT(19) |
140 BIT(20) | BIT(21) | BIT(22) | BIT(31),
148 .funcmask = BIT(4),
158 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
159 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
160 BIT(16) | BIT(17) | BIT(18) | BIT(19) |
161 BIT(20) | BIT(21) | BIT(22) | BIT(31),
[all …]
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192de/
Dreg.h94 #define MAC0_ON BIT(7)
95 #define MAC1_ON BIT(0)
96 #define MAC0_READY BIT(0)
97 #define MAC1_READY BIT(0)
443 #define RATE_1M BIT(0)
444 #define RATE_2M BIT(1)
445 #define RATE_5_5M BIT(2)
446 #define RATE_11M BIT(3)
448 #define RATE_6M BIT(4)
449 #define RATE_9M BIT(5)
[all …]
Ddef.h114 #define CHIP_92D_SINGLEPHY BIT(9)
127 #define CHIP_8723 BIT(0)
128 #define CHIP_92D BIT(1)
129 #define NORMAL_CHIP BIT(3)
130 #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
131 #define RF_TYPE_1T2R BIT(4)
132 #define RF_TYPE_2T2R BIT(5)
133 #define CHIP_VENDOR_UMC BIT(7)
134 #define CHIP_92D_B_CUT BIT(12)
135 #define CHIP_92D_C_CUT BIT(13)
[all …]
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192se/
Dreg.h327 #define RXDMA_AGG_EN BIT(7)
333 #define ISO_MD2PP BIT(0)
334 #define ISO_PA2PCIE BIT(3)
335 #define ISO_PLL2MD BIT(4)
336 #define ISO_PWC_DV2RP BIT(11)
337 #define ISO_PWC_RV2RP BIT(12)
340 #define FEN_MREGEN BIT(15)
341 #define FEN_DCORE BIT(11)
342 #define FEN_CPUEN BIT(10)
344 #define PAD_HWPD_IDN BIT(22)
[all …]
/linux-4.1.27/include/linux/mfd/da9150/
Dregisters.h164 #define DA9150_WRITE_MODE_MASK BIT(6)
166 #define DA9150_REVERT_MASK BIT(7)
176 #define DA9150_VFAULT_STAT_MASK BIT(0)
178 #define DA9150_TFAULT_STAT_MASK BIT(1)
182 #define DA9150_VDD33_STAT_MASK BIT(0)
184 #define DA9150_VDD33_SLEEP_MASK BIT(1)
186 #define DA9150_LFOSC_STAT_MASK BIT(7)
190 #define DA9150_GPIOA_STAT_MASK BIT(0)
192 #define DA9150_GPIOB_STAT_MASK BIT(1)
194 #define DA9150_GPIOC_STAT_MASK BIT(2)
[all …]
/linux-4.1.27/drivers/net/ethernet/atheros/alx/
Dreg.h61 #define ALX_UE_SVRT_FCPROTERR BIT(13)
62 #define ALX_UE_SVRT_DLPROTERR BIT(4)
66 #define ALX_EFLD_F_EXIST BIT(10)
67 #define ALX_EFLD_E_EXIST BIT(9)
68 #define ALX_EFLD_STAT BIT(5)
69 #define ALX_EFLD_START BIT(0)
73 #define ALX_SLD_STAT BIT(12)
74 #define ALX_SLD_START BIT(11)
78 #define ALX_PDLL_TRNS1_D3PLLOFF_EN BIT(11)
81 #define ALX_PMCTRL_HOTRST_WTEN BIT(31)
[all …]
/linux-4.1.27/arch/x86/include/asm/
Dpmc_atom.h35 #define BIT_LPC_CLOCK_RUN BIT(4)
36 #define BIT_SHARED_IRQ_GPSC BIT(5)
37 #define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18)
38 #define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19)
39 #define BIT_SHARED_IRQ_GPSS BIT(20)
59 #define PMC_PSS_BIT_GBE BIT(0)
60 #define PMC_PSS_BIT_SATA BIT(1)
61 #define PMC_PSS_BIT_HDA BIT(2)
62 #define PMC_PSS_BIT_SEC BIT(3)
63 #define PMC_PSS_BIT_PCIE BIT(4)
[all …]
Dimr.h22 #define IMR_ESRAM_FLUSH BIT(31)
23 #define IMR_CPU_SNOOP BIT(30) /* Applicable only to write */
24 #define IMR_RMU BIT(29)
25 #define IMR_VC1_SAI_ID3 BIT(15)
26 #define IMR_VC1_SAI_ID2 BIT(14)
27 #define IMR_VC1_SAI_ID1 BIT(13)
28 #define IMR_VC1_SAI_ID0 BIT(12)
29 #define IMR_VC0_SAI_ID3 BIT(11)
30 #define IMR_VC0_SAI_ID2 BIT(10)
31 #define IMR_VC0_SAI_ID1 BIT(9)
[all …]
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723ae/
Dreg.h342 #define CMDEEPROM_EN BIT(5)
343 #define CMDEEPROM_SEL BIT(4)
344 #define CMD9346CR_9356SEL BIT(4)
349 #define GPIOSEL_ENBT BIT(5)
367 #define RRSR_1M BIT(0)
368 #define RRSR_2M BIT(1)
369 #define RRSR_5_5M BIT(2)
370 #define RRSR_11M BIT(3)
371 #define RRSR_6M BIT(4)
372 #define RRSR_9M BIT(5)
[all …]
Dpwrseq.h68 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
71 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
74 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
77 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
85 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
99 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
[all …]
Dhal_bt_coexist.h50 #define BT_COEX_STATE_BT30 BIT(0)
51 #define BT_COEX_STATE_WIFI_HT20 BIT(1)
52 #define BT_COEX_STATE_WIFI_HT40 BIT(2)
53 #define BT_COEX_STATE_WIFI_LEGACY BIT(3)
55 #define BT_COEX_STATE_WIFI_RSSI_LOW BIT(4)
56 #define BT_COEX_STATE_WIFI_RSSI_MEDIUM BIT(5)
57 #define BT_COEX_STATE_WIFI_RSSI_HIGH BIT(6)
58 #define BT_COEX_STATE_DEC_BT_POWER BIT(7)
60 #define BT_COEX_STATE_WIFI_IDLE BIT(8)
61 #define BT_COEX_STATE_WIFI_UPLINK BIT(9)
[all …]
Ddef.h70 #define CHIP_8723 BIT(0)
71 #define NORMAL_CHIP BIT(3)
72 #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
73 #define RF_TYPE_1T2R BIT(4)
74 #define RF_TYPE_2T2R BIT(5)
75 #define CHIP_VENDOR_UMC BIT(7)
76 #define B_CUT_VERSION BIT(12)
77 #define C_CUT_VERSION BIT(13)
78 #define D_CUT_VERSION ((BIT(12)|BIT(13)))
79 #define E_CUT_VERSION BIT(14)
[all …]
/linux-4.1.27/drivers/usb/chipidea/
Dbits.h29 #define HCCPARAMS_LEN BIT(17)
33 #define DCCPARAMS_DC BIT(7)
34 #define DCCPARAMS_HC BIT(8)
37 #define TESTMODE_FORCE BIT(0)
40 #define USBCMD_RS BIT(0)
41 #define USBCMD_RST BIT(1)
42 #define USBCMD_SUTW BIT(13)
43 #define USBCMD_ATDTW BIT(14)
46 #define USBi_UI BIT(0)
47 #define USBi_UEI BIT(1)
[all …]
/linux-4.1.27/include/linux/mfd/
Dtps65218.h66 #define TPS65218_INT1_VPRG BIT(5)
67 #define TPS65218_INT1_AC BIT(4)
68 #define TPS65218_INT1_PB BIT(3)
69 #define TPS65218_INT1_HOT BIT(2)
70 #define TPS65218_INT1_CC_AQC BIT(1)
71 #define TPS65218_INT1_PRGC BIT(0)
73 #define TPS65218_INT2_LS3_F BIT(5)
74 #define TPS65218_INT2_LS2_F BIT(4)
75 #define TPS65218_INT2_LS1_F BIT(3)
76 #define TPS65218_INT2_LS3_I BIT(2)
[all …]
Dtps65217.h69 #define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
70 #define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
71 #define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
72 #define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
76 #define TPS65217_INT_PBM BIT(6)
77 #define TPS65217_INT_ACM BIT(5)
78 #define TPS65217_INT_USBM BIT(4)
79 #define TPS65217_INT_PBI BIT(2)
80 #define TPS65217_INT_ACI BIT(1)
81 #define TPS65217_INT_USBI BIT(0)
[all …]
Das3722.h189 #define AS3722_LDO_ILIMIT_MASK BIT(7)
190 #define AS3722_LDO_ILIMIT_BIT BIT(7)
206 #define AS3722_LDO0_CTRL BIT(0)
207 #define AS3722_LDO1_CTRL BIT(1)
208 #define AS3722_LDO2_CTRL BIT(2)
209 #define AS3722_LDO3_CTRL BIT(3)
210 #define AS3722_LDO4_CTRL BIT(4)
211 #define AS3722_LDO5_CTRL BIT(5)
212 #define AS3722_LDO6_CTRL BIT(6)
213 #define AS3722_LDO7_CTRL BIT(7)
[all …]
Dmax77843-private.h187 #define MAX77843_SYS_IRQ_SYSUVLO_INT BIT(0)
188 #define MAX77843_SYS_IRQ_SYSOVLO_INT BIT(1)
189 #define MAX77843_SYS_IRQ_TSHDN_INT BIT(2)
190 #define MAX77843_SYS_IRQ_TM_INT BIT(3)
194 #define MAX77843_MAINCTRL1_BIASEN_MASK BIT(MAINCTRL1_BIASEN_SHIFT)
201 #define MAX77843_MCONFIG_MODE_MASK BIT(MCONFIG_MODE_SHIFT)
202 #define MAX77843_MCONFIG_MEN_MASK BIT(MCONFIG_MEN_SHIFT)
206 #define MAX77843_CHG_BYP_I BIT(0)
207 #define MAX77843_CHG_BATP_I BIT(2)
208 #define MAX77843_CHG_BAT_I BIT(3)
[all …]
Dtps6507x.h23 #define TPS6507X_CHG_USB BIT(7)
24 #define TPS6507X_CHG_AC BIT(6)
25 #define TPS6507X_CHG_USB_PW_ENABLE BIT(5)
26 #define TPS6507X_CHG_AC_PW_ENABLE BIT(4)
27 #define TPS6507X_CHG_AC_CURRENT BIT(2)
28 #define TPS6507X_CHG_USB_CURRENT BIT(0)
31 #define TPS6507X_REG_MASK_AC_USB BIT(7)
32 #define TPS6507X_REG_MASK_TSC BIT(6)
33 #define TPS6507X_REG_MASK_PB_IN BIT(5)
34 #define TPS6507X_REG_TSC_INT BIT(3)
[all …]
Datmel-hlcdc.h28 #define ATMEL_HLCDC_HSPOL BIT(0)
29 #define ATMEL_HLCDC_VSPOL BIT(1)
30 #define ATMEL_HLCDC_VSPDLYS BIT(2)
31 #define ATMEL_HLCDC_VSPDLYE BIT(3)
32 #define ATMEL_HLCDC_DISPPOL BIT(4)
33 #define ATMEL_HLCDC_DITHER BIT(6)
34 #define ATMEL_HLCDC_DISPDLY BIT(7)
36 #define ATMEL_HLCDC_PP BIT(10)
37 #define ATMEL_HLCDC_VSPSU BIT(12)
38 #define ATMEL_HLCDC_VSPHO BIT(13)
[all …]
Dmax14577-private.h105 #define MAX14577_INT1_ADC_MASK BIT(0)
106 #define MAX14577_INT1_ADCLOW_MASK BIT(1)
107 #define MAX14577_INT1_ADCERR_MASK BIT(2)
108 #define MAX77836_INT1_ADC1K_MASK BIT(3)
110 #define MAX14577_INT2_CHGTYP_MASK BIT(0)
111 #define MAX14577_INT2_CHGDETRUN_MASK BIT(1)
112 #define MAX14577_INT2_DCDTMR_MASK BIT(2)
113 #define MAX14577_INT2_DBCHG_MASK BIT(3)
114 #define MAX14577_INT2_VBVOLT_MASK BIT(4)
115 #define MAX77836_INT2_VIDRM_MASK BIT(5)
[all …]
Dmax77693-private.h137 #define FLASH_STATUS_FLASH_ON BIT(3)
138 #define FLASH_STATUS_TORCH_ON BIT(2)
141 #define FLASH_INT_FLED2_OPEN BIT(0)
142 #define FLASH_INT_FLED2_SHORT BIT(1)
143 #define FLASH_INT_FLED1_OPEN BIT(2)
144 #define FLASH_INT_FLED1_SHORT BIT(3)
145 #define FLASH_INT_OVER_CURRENT BIT(4)
170 #define CHG_INT_OK_BYP_MASK BIT(CHG_INT_OK_BYP_SHIFT)
171 #define CHG_INT_OK_BAT_MASK BIT(CHG_INT_OK_BAT_SHIFT)
172 #define CHG_INT_OK_CHG_MASK BIT(CHG_INT_OK_CHG_SHIFT)
[all …]
Ddavinci_voicecodec.h54 #define DAVINCI_VC_CTRL_RSTADC BIT(0)
55 #define DAVINCI_VC_CTRL_RSTDAC BIT(1)
56 #define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
57 #define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
58 #define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
59 #define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
60 #define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
61 #define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
62 #define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
63 #define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
[all …]
Dti_am335x_tscadc.h44 #define IRQWKUP_ENB BIT(0)
54 #define IRQENB_HW_PEN BIT(0)
55 #define IRQENB_EOS BIT(1)
56 #define IRQENB_FIFO0THRES BIT(2)
57 #define IRQENB_FIFO0OVRRUN BIT(3)
58 #define IRQENB_FIFO0UNDRFLW BIT(4)
59 #define IRQENB_FIFO1THRES BIT(5)
60 #define IRQENB_FIFO1OVRRUN BIT(6)
61 #define IRQENB_FIFO1UNDRFLW BIT(7)
62 #define IRQENB_PENUP BIT(9)
[all …]
Dwl1273-core.h138 #define WL1273_MODE_RX BIT(0)
139 #define WL1273_MODE_TX BIT(1)
140 #define WL1273_MODE_OFF BIT(2)
141 #define WL1273_MODE_SUSPENDED BIT(3)
143 #define WL1273_RADIO_CHILD BIT(0)
144 #define WL1273_CODEC_CHILD BIT(1)
158 #define WL1273_AUDIO_ENABLE_I2S BIT(0)
159 #define WL1273_AUDIO_ENABLE_ANALOG BIT(1)
223 #define WL1273_FR_EVENT BIT(0)
224 #define WL1273_BL_EVENT BIT(1)
[all …]
Drk808.h130 #define RK808_IRQ_VOUT_LO_MSK BIT(0)
131 #define RK808_IRQ_VB_LO_MSK BIT(1)
132 #define RK808_IRQ_PWRON_MSK BIT(2)
133 #define RK808_IRQ_PWRON_LP_MSK BIT(3)
134 #define RK808_IRQ_HOTDIE_MSK BIT(4)
135 #define RK808_IRQ_RTC_ALARM_MSK BIT(5)
136 #define RK808_IRQ_RTC_PERIOD_MSK BIT(6)
137 #define RK808_IRQ_PLUG_IN_INT_MSK BIT(0)
138 #define RK808_IRQ_PLUG_OUT_INT_MSK BIT(1)
162 #define SWITCH2_EN BIT(6)
[all …]
/linux-4.1.27/drivers/staging/rtl8712/
Drtl8712_cmdctrl_bitdef.h28 #define _APSDOFF_STATUS BIT(15)
29 #define _APSDOFF BIT(14)
30 #define _BBRSTn BIT(13) /*Enable OFDM/CCK*/
31 #define _BB_GLB_RSTn BIT(12) /*Enable BB*/
32 #define _SCHEDULE_EN BIT(10) /*Enable MAC scheduler*/
33 #define _MACRXEN BIT(9)
34 #define _MACTXEN BIT(8)
35 #define _DDMA_EN BIT(7) /*FW off load function enable*/
36 #define _FW2HW_EN BIT(6) /*MAC every module reset */
37 #define _RXDMA_EN BIT(5)
[all …]
Drtl8712_fifoctrl_bitdef.h30 #define _TXSTATUS_OVF BIT(15)
33 #define _STATUSFF1_OVF BIT(7)
34 #define _STATUSFF1_EMPTY BIT(6)
35 #define _STATUSFF0_OVF BIT(5)
36 #define _STATUSFF0_EMPTY BIT(4)
37 #define _RXFF1_OVF BIT(3)
38 #define _RXFF1_EMPTY BIT(2)
39 #define _RXFF0_OVF BIT(1)
40 #define _RXFF0_EMPTY BIT(0)
58 #define _C2HFF_POLL BIT(4)
[all …]
Drtl8712_syscfg_bitdef.h36 #define iso_LDR2RP BIT(iso_LDR2RP_SHT) /* 1:isolation, 0:attach*/
40 #define FEN_DIO_SDIO BIT(FEN_DIO_SDIO_SHT)
42 #define FEN_SDIO BIT(FEN_SDIO_SHT)
44 #define FEN_USBA BIT(FEN_USBA_SHT)
46 #define FEN_UPLL BIT(FEN_UPLL_SHT)
48 #define FEN_USBD BIT(FEN_USBD_SHT)
50 #define FEN_DIO_PCIE BIT(FEN_DIO_PCIE_SHT)
52 #define FEN_PCIEA BIT(FEN_PCIEA_SHT)
54 #define FEN_PPLL BIT(FEN_PPLL_SHT)
56 #define FEN_PCIED BIT(FEN_PCIED_SHT)
[all …]
Drtl8712_interrupt_bitdef.h25 #define _CPUERR BIT(29)
26 #define _ATIMEND BIT(28)
27 #define _TXBCNOK BIT(27)
28 #define _TXBCNERR BIT(26)
29 #define _BCNDMAINT4 BIT(25)
30 #define _BCNDMAINT3 BIT(24)
31 #define _BCNDMAINT2 BIT(23)
32 #define _BCNDMAINT1 BIT(22)
33 #define _BCNDOK4 BIT(21)
34 #define _BCNDOK3 BIT(20)
[all …]
Dwifi.h31 #ifdef BIT
32 #undef BIT
34 #define BIT(x) (1 << (x)) macro
61 WIFI_CTRL_TYPE = (BIT(2)),
62 WIFI_DATA_TYPE = (BIT(3)),
63 WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), /*!< QoS Data */
69 WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE),
70 WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE),
71 WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE),
72 WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE),
[all …]
Drtl871x_debug.h44 #define _module_rtl871x_xmit_c_ BIT(0)
45 #define _module_xmit_osdep_c_ BIT(1)
46 #define _module_rtl871x_recv_c_ BIT(2)
47 #define _module_recv_osdep_c_ BIT(3)
48 #define _module_rtl871x_mlme_c_ BIT(4)
49 #define _module_mlme_osdep_c_ BIT(5)
50 #define _module_rtl871x_sta_mgt_c_ BIT(6)
51 #define _module_rtl871x_cmd_c_ BIT(7)
52 #define _module_cmd_osdep_c_ BIT(8)
53 #define _module_rtl871x_io_c_ BIT(9)
[all …]
Drtl8712_security_bitdef.h24 #define _SECCAM_POLLING BIT(31)
25 #define _SECCAM_CLR BIT(30)
26 #define _SECCAM_WE BIT(16)
31 #define _SECCAM_INFO BIT(31)
32 #define _SEC_KEYFOUND BIT(30)
39 #define _NOSKMC BIT(5)
40 #define _SKBYA2 BIT(4)
41 #define _RXDEC BIT(3)
42 #define _TXENC BIT(2)
43 #define _RXUSEDK BIT(1)
[all …]
Drtl8712_powersave_bitdef.h24 #define _UWF BIT(3)
25 #define _MAGIC BIT(2)
26 #define _WOW_EN BIT(1)
27 #define _PMEN BIT(0)
33 #define _PSSWITCH_ACT BIT(7)
38 #define _LPNAV_EN BIT(31)
46 #define _TOGGLING BIT(7)
47 #define _WWLAN BIT(3)
48 #define _RPS_ST BIT(2)
49 #define _WLAN_TRX BIT(1)
[all …]
Drtl8712_edcasetting_bitdef.h47 #define _AVG_TIME_UP BIT(3)
51 #define _VOQ_ACM_STATUS BIT(6)
52 #define _VIQ_ACM_STATUS BIT(5)
53 #define _BEQ_ACM_STATUS BIT(4)
54 #define _VOQ_ACM_EN BIT(3)
55 #define _VIQ_ACM_EN BIT(2)
56 #define _BEQ_ACM_EN BIT(1)
57 #define _ACMHWEN BIT(0)
60 #define _VO_ACM_RUT BIT(18)
64 #define _VI_ACM_RUT BIT(18)
[all …]
Drtl8712_gp_bitdef.h44 #define _LED1SV BIT(7)
47 #define _LED0SV BIT(3)
54 #define _HST_RDRDY BIT(_HST_RDRDY_SHT)
57 #define _CPU_WTBUSY BIT(_CPU_WTBUSY_SHT)
65 #define GPIOMUX_EN BIT(3) /* When this bit is set to "1",
72 #define GPIOSEL_GPIO_MASK (~(BIT(0)|BIT(1)))
74 #define HAL_8192S_HW_GPIO_OFF_BIT BIT(3)
76 #define HAL_8192S_HW_GPIO_WPS_BIT BIT(4)
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8188ee/
Dreg.h374 #define CMDEEPROM_EN BIT(5)
375 #define CMDEEPROM_SEL BIT(4)
376 #define CMD9346CR_9356SEL BIT(4)
381 #define GPIOSEL_ENBT BIT(5)
391 #define HSIMR_GPIO12_0_INT_EN BIT(0)
392 #define HSIMR_SPS_OCP_INT_EN BIT(5)
393 #define HSIMR_RON_INT_EN BIT(6)
394 #define HSIMR_PDN_INT_EN BIT(7)
395 #define HSIMR_GPIO9_INT_EN BIT(25)
400 #define HSISR_GPIO12_0_INT BIT(0)
[all …]
Dpwrseq.h68 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \
71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0 \
74 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
77 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0 \
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0 \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0) \
86 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0 \
89 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
100 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
[all …]
Ddef.h75 #define CHIP_8723 BIT(0)
76 #define CHIP_92D BIT(1)
77 #define NORMAL_CHIP BIT(3)
78 #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
79 #define RF_TYPE_1T2R BIT(4)
80 #define RF_TYPE_2T2R BIT(5)
81 #define CHIP_VENDOR_UMC BIT(7)
82 #define B_CUT_VERSION BIT(12)
83 #define C_CUT_VERSION BIT(13)
84 #define D_CUT_VERSION ((BIT(12)|BIT(13)))
[all …]
/linux-4.1.27/include/linux/mfd/syscon/
Dimx6q-iomuxc-gpr.h72 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
74 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
75 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
77 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
78 #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5)
80 #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5)
81 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4)
83 #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4)
84 #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3)
86 #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1 BIT(3)
[all …]
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192ee/
Dreg.h404 #define CMDEEPROM_EN BIT(5)
405 #define CMDEEPROM_SEL BIT(4)
406 #define CMD9346CR_9356SEL BIT(4)
411 #define GPIOSEL_ENBT BIT(5)
429 #define RRSR_1M BIT(0)
430 #define RRSR_2M BIT(1)
431 #define RRSR_5_5M BIT(2)
432 #define RRSR_11M BIT(3)
433 #define RRSR_6M BIT(4)
434 #define RRSR_9M BIT(5)
[all …]
Dpwrseq.h69 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
72 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
75 PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
78 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
81 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
84 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
87 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
98 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
101 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
104 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},
[all …]
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192ce/
Dreg.h360 #define CMDEEPROM_EN BIT(5)
361 #define CMDEEPROM_SEL BIT(4)
362 #define CMD9346CR_9356SEL BIT(4)
367 #define GPIOSEL_ENBT BIT(5)
386 #define RRSR_1M BIT(0)
387 #define RRSR_2M BIT(1)
388 #define RRSR_5_5M BIT(2)
389 #define RRSR_11M BIT(3)
390 #define RRSR_6M BIT(4)
391 #define RRSR_9M BIT(5)
[all …]
/linux-4.1.27/arch/mips/include/asm/ip32/
Dmace.h26 #define MACEPCI_ERROR_MASTER_ABORT BIT(31)
27 #define MACEPCI_ERROR_TARGET_ABORT BIT(30)
28 #define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29)
29 #define MACEPCI_ERROR_RETRY_ERR BIT(28)
30 #define MACEPCI_ERROR_ILLEGAL_CMD BIT(27)
31 #define MACEPCI_ERROR_SYSTEM_ERR BIT(26)
32 #define MACEPCI_ERROR_INTERRUPT_TEST BIT(25)
33 #define MACEPCI_ERROR_PARITY_ERR BIT(24)
34 #define MACEPCI_ERROR_OVERRUN BIT(23)
35 #define MACEPCI_ERROR_RSVD BIT(22)
[all …]
Dcrime.h50 #define MACE_VID_IN1_INT BIT(0)
51 #define MACE_VID_IN2_INT BIT(1)
52 #define MACE_VID_OUT_INT BIT(2)
53 #define MACE_ETHERNET_INT BIT(3)
54 #define MACE_SUPERIO_INT BIT(4)
55 #define MACE_MISC_INT BIT(5)
56 #define MACE_AUDIO_INT BIT(6)
57 #define MACE_PCI_BRIDGE_INT BIT(7)
58 #define MACEPCI_SCSI0_INT BIT(8)
59 #define MACEPCI_SCSI1_INT BIT(9)
[all …]
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723be/
Dreg.h389 #define CMDEEPROM_EN BIT(5)
390 #define CMDEEPROM_SEL BIT(4)
391 #define CMD9346CR_9356SEL BIT(4)
396 #define GPIOSEL_ENBT BIT(5)
404 #define HSIMR_GPIO12_0_INT_EN BIT(0)
405 #define HSIMR_SPS_OCP_INT_EN BIT(5)
406 #define HSIMR_RON_INT_EN BIT(6)
407 #define HSIMR_PDN_INT_EN BIT(7)
408 #define HSIMR_GPIO9_INT_EN BIT(25)
411 #define HSISR_GPIO12_0_INT BIT(0)
[all …]
Dpwrseq.h68 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
72 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
86 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
89 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
98 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
101 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
[all …]
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/
Dreg.h400 #define CMDEEPROM_EN BIT(5)
401 #define CMDEEPROM_SEL BIT(4)
402 #define CMD9346CR_9356SEL BIT(4)
407 #define GPIOSEL_ENBT BIT(5)
415 #define HSIMR_GPIO12_0_INT_EN BIT(0)
416 #define HSIMR_SPS_OCP_INT_EN BIT(5)
417 #define HSIMR_RON_INT_EN BIT(6)
418 #define HSIMR_PDN_INT_EN BIT(7)
419 #define HSIMR_GPIO9_INT_EN BIT(25)
422 #define HSISR_GPIO12_0_INT BIT(0)
[all …]
Ddef.h165 #define CHIP_8812 BIT(2)
166 #define CHIP_8821 (BIT(0)|BIT(2))
168 #define CHIP_8821A (BIT(0)|BIT(2))
169 #define NORMAL_CHIP BIT(3)
170 #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
171 #define RF_TYPE_1T2R BIT(4)
172 #define RF_TYPE_2T2R BIT(5)
173 #define CHIP_VENDOR_UMC BIT(7)
174 #define B_CUT_VERSION BIT(12)
175 #define C_CUT_VERSION BIT(13)
[all …]
/linux-4.1.27/arch/mips/include/asm/mach-ath79/
Dar71xx_regs.h203 #define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
233 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
234 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
235 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
242 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
243 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
244 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
268 #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
269 #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
270 #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
[all …]
Dar933x_uart.h24 #define AR933X_UART_DATA_RX_CSR BIT(8)
25 #define AR933X_UART_DATA_TX_CSR BIT(9)
39 #define AR933X_UART_CS_DMA_EN BIT(6)
40 #define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
41 #define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
42 #define AR933X_UART_CS_TX_READY BIT(9)
43 #define AR933X_UART_CS_RX_BREAK BIT(10)
44 #define AR933X_UART_CS_TX_BREAK BIT(11)
45 #define AR933X_UART_CS_HOST_INT BIT(12)
46 #define AR933X_UART_CS_HOST_INT_EN BIT(13)
[all …]
/linux-4.1.27/sound/soc/davinci/
Ddavinci-mcasp.h106 #define MCASP_FREE BIT(0)
107 #define MCASP_SOFT BIT(1)
113 #define PFUNC_AMUTE BIT(25)
114 #define ACLKX BIT(26)
115 #define AHCLKX BIT(27)
116 #define AFSX BIT(28)
117 #define ACLKR BIT(29)
118 #define AHCLKR BIT(30)
119 #define AFSR BIT(31)
125 #define PDIR_AMUTE BIT(25)
[all …]
/linux-4.1.27/drivers/staging/rtl8188eu/include/
Drtl8188e_spec.h22 #ifndef BIT
23 #define BIT(x) (1 << (x)) macro
381 #define RXERR_RPT_RST BIT(27)
749 #define ISO_MD2PP BIT(0)
750 #define ISO_UA2USB BIT(1)
751 #define ISO_UD2CORE BIT(2)
752 #define ISO_PA2PCIE BIT(3)
753 #define ISO_PD2CORE BIT(4)
754 #define ISO_IP2MAC BIT(5)
755 #define ISO_DIOP BIT(6)
[all …]
Dwifi.h24 #ifdef BIT
26 #undef BIT
28 #define BIT(x) (1 << (x)) macro
61 WIFI_CTRL_TYPE = (BIT(2)),
62 WIFI_DATA_TYPE = (BIT(3)),
63 WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), /* QoS Data */
69 WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE),
70 WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE),
71 WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE),
72 WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE),
[all …]
Dhal_com.h60 #define RATE_1M BIT(0)
61 #define RATE_2M BIT(1)
62 #define RATE_5_5M BIT(2)
63 #define RATE_11M BIT(3)
65 #define RATE_6M BIT(4)
66 #define RATE_9M BIT(5)
67 #define RATE_12M BIT(6)
68 #define RATE_18M BIT(7)
69 #define RATE_24M BIT(8)
70 #define RATE_36M BIT(9)
[all …]
Dpwrseqcmd.h40 #define PWR_INTF_SDIO_MSK BIT(0)
41 #define PWR_INTF_USB_MSK BIT(1)
42 #define PWR_INTF_PCI_MSK BIT(2)
43 #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
46 #define PWR_FAB_TSMC_MSK BIT(0)
47 #define PWR_FAB_UMC_MSK BIT(1)
48 #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
51 #define PWR_CUT_TESTCHIP_MSK BIT(0)
52 #define PWR_CUT_A_MSK BIT(1)
53 #define PWR_CUT_B_MSK BIT(2)
[all …]
Drtw_debug.h38 #define _module_rtl871x_xmit_c_ BIT(0)
39 #define _module_xmit_osdep_c_ BIT(1)
40 #define _module_rtl871x_recv_c_ BIT(2)
41 #define _module_recv_osdep_c_ BIT(3)
42 #define _module_rtl871x_mlme_c_ BIT(4)
43 #define _module_mlme_osdep_c_ BIT(5)
44 #define _module_rtl871x_sta_mgt_c_ BIT(6)
45 #define _module_rtl871x_cmd_c_ BIT(7)
46 #define _module_cmd_osdep_c_ BIT(8)
47 #define _module_rtl871x_io_c_ BIT(9)
[all …]
Drtl8188e_xmit.h61 #define BMC BIT(24)
62 #define LSG BIT(26)
63 #define FSG BIT(27)
64 #define OWN BIT(31)
71 #define NAVUSEHDR BIT(20)
76 #define AGG_EN BIT(12)
77 #define AGG_BK BIT(16)
79 #define ANTSEL_A BIT(24)
80 #define ANTSEL_B BIT(25)
87 #define EN_HWSEQ BIT(31)
[all …]
Drtw_pwrctrl.h38 #define XMIT_ALIVE BIT(0)
39 #define RECV_ALIVE BIT(1)
40 #define CMD_ALIVE BIT(2)
41 #define EVT_ALIVE BIT(3)
65 #define PS_DPS BIT(0)
67 #define PS_RF_OFF BIT(1)
68 #define PS_ALL_ON BIT(2)
69 #define PS_ST_ACTIVE BIT(3)
71 #define PS_ISR_ENABLE BIT(4)
72 #define PS_IMR_ENABLE BIT(5)
[all …]
/linux-4.1.27/drivers/mmc/host/
Dtoshsd.h32 #define SD_PCICFG_CLKMODE_DIV_DISABLE BIT(0)
78 #define SD_TRANSCTL_SET BIT(8)
80 #define SD_CARDCLK_DIV_DISABLE BIT(15)
81 #define SD_CARDCLK_ENABLE_CLOCK BIT(8)
82 #define SD_CARDCLK_CLK_DIV_512 BIT(7)
83 #define SD_CARDCLK_CLK_DIV_256 BIT(6)
84 #define SD_CARDCLK_CLK_DIV_128 BIT(5)
85 #define SD_CARDCLK_CLK_DIV_64 BIT(4)
86 #define SD_CARDCLK_CLK_DIV_32 BIT(3)
87 #define SD_CARDCLK_CLK_DIV_16 BIT(2)
[all …]
Ddw_mmc.h81 #define SDMMC_CTRL_USE_IDMAC BIT(25)
82 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
83 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
84 #define SDMMC_CTRL_SEND_CCSD BIT(9)
85 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
86 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
87 #define SDMMC_CTRL_READ_WAIT BIT(6)
88 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
89 #define SDMMC_CTRL_INT_ENABLE BIT(4)
90 #define SDMMC_CTRL_DMA_RESET BIT(2)
[all …]
Dsunxi-mmc.c80 #define SDXC_SOFT_RESET BIT(0)
81 #define SDXC_FIFO_RESET BIT(1)
82 #define SDXC_DMA_RESET BIT(2)
83 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
84 #define SDXC_DMA_ENABLE_BIT BIT(5)
85 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
86 #define SDXC_POSEDGE_LATCH_DATA BIT(9)
87 #define SDXC_DDR_MODE BIT(10)
88 #define SDXC_MEMORY_ACCESS_DONE BIT(29)
89 #define SDXC_ACCESS_DONE_DIRECT BIT(30)
[all …]
Ddw_mmc-exynos.h35 #define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
38 #define DATA_STROBE_EN BIT(0)
39 #define AXI_NON_BLOCKING_WR BIT(7)
53 #define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7)
54 #define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6)
55 #define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
56 #define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
57 #define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3)
58 #define SDMMC_MPSCTRL_ECB_MODE BIT(2)
59 #define SDMMC_MPSCTRL_ENCRYPTION BIT(1)
[all …]
/linux-4.1.27/drivers/net/ethernet/moxa/
Dmoxart_ether.h120 #define RPKT_FINISH BIT(0) /* DMA data received */
121 #define NORXBUF BIT(1) /* receive buffer unavailable */
122 #define XPKT_FINISH BIT(2) /* DMA moved data to TX FIFO */
123 #define NOTXBUF BIT(3) /* transmit buffer unavailable */
124 #define XPKT_OK_INT_STS BIT(4) /* transmit to ethernet success */
125 #define XPKT_LOST_INT_STS BIT(5) /* transmit ethernet lost (collision) */
126 #define RPKT_SAV BIT(6) /* FIFO receive success */
127 #define RPKT_LOST_INT_STS BIT(7) /* FIFO full, receive failed */
128 #define AHB_ERR BIT(8) /* AHB error */
129 #define PHYSTS_CHG BIT(9) /* PHY link status change */
[all …]
/linux-4.1.27/drivers/net/ethernet/atheros/atl1c/
Datl1c_hw.h108 #define TWSI_CTRL_LD_EXIST BIT(23)
109 #define TWSI_CTRL_HW_LDSTAT BIT(12) /* 0:finish,1:in progress */
110 #define TWSI_CTRL_SW_LDSTART BIT(11)
122 #define PCIE_PHYMISC_FORCE_RCV_DET BIT(2)
135 #define TWSI_DEBUG_DEV_EXIST BIT(29)
138 #define DMA_DBG_VENDOR_MSG BIT(0)
151 #define OTP_CTRL_CLK_EN BIT(1)
154 #define PM_CTRL_HOTRST BIT(31)
155 #define PM_CTRL_MAC_ASPM_CHK BIT(30) /* L0s/L1 dis by MAC based on
157 #define PM_CTRL_SA_DLY_EN BIT(29)
[all …]
/linux-4.1.27/drivers/net/wireless/rtlwifi/
Ddebug.h75 #define COMP_ERR BIT(0)
76 #define COMP_FW BIT(1)
77 #define COMP_INIT BIT(2) /*For init/deinit */
78 #define COMP_RECV BIT(3) /*For Rx. */
79 #define COMP_SEND BIT(4) /*For Tx. */
80 #define COMP_MLME BIT(5) /*For MLME. */
81 #define COMP_SCAN BIT(6) /*For Scan. */
82 #define COMP_INTR BIT(7) /*For interrupt Related. */
83 #define COMP_LED BIT(8) /*For LED. */
84 #define COMP_SEC BIT(9) /*For sec. */
[all …]
Dpwrseqcmd.h46 #define PWR_INTF_SDIO_MSK BIT(0)
47 #define PWR_INTF_USB_MSK BIT(1)
48 #define PWR_INTF_PCI_MSK BIT(2)
49 #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
51 #define PWR_FAB_TSMC_MSK BIT(0)
52 #define PWR_FAB_UMC_MSK BIT(1)
53 #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
55 #define PWR_CUT_TESTCHIP_MSK BIT(0)
56 #define PWR_CUT_A_MSK BIT(1)
57 #define PWR_CUT_B_MSK BIT(2)
[all …]
/linux-4.1.27/drivers/misc/mei/
Dhw-txe-regs.h106 # define SEC_IPC_INPUT_STATUS_RDY BIT(0)
110 #define SEC_IPC_HOST_INT_STATUS_OUT_DB BIT(0)
111 #define SEC_IPC_HOST_INT_STATUS_IN_RDY BIT(1)
112 #define SEC_IPC_HOST_INT_STATUS_HDCP_M0_RCVD BIT(5)
113 #define SEC_IPC_HOST_INT_STATUS_ILL_MEM_ACCESS BIT(17)
114 #define SEC_IPC_HOST_INT_STATUS_AES_HKEY_ERR BIT(18)
115 #define SEC_IPC_HOST_INT_STATUS_DES_HKEY_ERR BIT(19)
116 #define SEC_IPC_HOST_INT_STATUS_TMRMTB_OVERFLOW BIT(21)
126 # define SEC_IPC_HOST_INT_MASK_OUT_DB BIT(0) /* Output Doorbell Int Mask */
127 # define SEC_IPC_HOST_INT_MASK_IN_RDY BIT(1) /* Input Ready Int Mask */
[all …]
/linux-4.1.27/drivers/scsi/pcmcia/
Dnsp_cs.h40 # define IRQCONTROL_RESELECT_CLEAR BIT(0)
41 # define IRQCONTROL_PHASE_CHANGE_CLEAR BIT(1)
42 # define IRQCONTROL_TIMER_CLEAR BIT(2)
43 # define IRQCONTROL_FIFO_CLEAR BIT(3)
52 # define IRQSTATUS_SCSI BIT(0)
53 # define IRQSTATUS_TIMER BIT(2)
54 # define IRQSTATUS_FIFO BIT(3)
58 # define IF_IFSEL BIT(0)
59 # define IF_REGSEL BIT(2)
64 # define FIFOSTATUS_FULL_EMPTY BIT(7)
[all …]
/linux-4.1.27/drivers/net/wireless/ath/carl9170/
Dhw.h115 #define AR9170_MAC_INT_TXC BIT(0)
116 #define AR9170_MAC_INT_RXC BIT(1)
117 #define AR9170_MAC_INT_RETRY_FAIL BIT(2)
118 #define AR9170_MAC_INT_WAKEUP BIT(3)
119 #define AR9170_MAC_INT_ATIM BIT(4)
120 #define AR9170_MAC_INT_DTIM BIT(5)
121 #define AR9170_MAC_INT_CFG_BCN BIT(6)
122 #define AR9170_MAC_INT_ABORT BIT(7)
123 #define AR9170_MAC_INT_QOS BIT(8)
124 #define AR9170_MAC_INT_MIMO_PS BIT(9)
[all …]
/linux-4.1.27/sound/soc/omap/
Dmcbsp.h98 #define RRST BIT(0)
99 #define RRDY BIT(1)
100 #define RFULL BIT(2)
101 #define RSYNC_ERR BIT(3)
103 #define ABIS BIT(6)
104 #define DXENA BIT(7)
107 #define ALB BIT(15)
108 #define DLB BIT(15)
111 #define XRST BIT(0)
112 #define XRDY BIT(1)
[all …]
/linux-4.1.27/drivers/thermal/ti-soc-thermal/
Ddra752-bandgap.h122 #define DRA752_BANDGAP_STATUS_1_ALERT_MASK BIT(31)
123 #define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5)
124 #define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4)
125 #define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3)
126 #define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2)
127 #define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1)
128 #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0)
131 #define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22)
132 #define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21)
133 #define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK BIT(19)
[all …]
Domap5xxx-bandgap.h91 #define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK BIT(12)
92 #define OMAP5430_BGAP_TEMPSOFF_MASK BIT(11)
93 #define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10)
99 #define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23)
100 #define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22)
101 #define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21)
102 #define OMAP5430_MASK_CLEAR_CORE_MASK BIT(20)
103 #define OMAP5430_MASK_CLEAR_GPU_MASK BIT(19)
104 #define OMAP5430_MASK_CLEAR_MPU_MASK BIT(18)
105 #define OMAP5430_MASK_CLEAR_ACCUM_CORE_MASK BIT(17)
[all …]
Domap4xxx-bandgap.h55 #define OMAP4430_BGAP_TEMPSOFF_MASK BIT(12)
56 #define OMAP4430_BGAP_TSHUT_MASK BIT(11)
57 #define OMAP4430_SINGLE_MODE_MASK BIT(10)
58 #define OMAP4430_BGAP_TEMP_SENSOR_SOC_MASK BIT(9)
59 #define OMAP4430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(8)
124 #define OMAP4460_BGAP_TEMPSOFF_MASK BIT(13)
125 #define OMAP4460_BGAP_TEMP_SENSOR_SOC_MASK BIT(11)
126 #define OMAP4460_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10)
130 #define OMAP4460_SINGLE_MODE_MASK BIT(31)
131 #define OMAP4460_MASK_HOT_MASK BIT(1)
[all …]
/linux-4.1.27/drivers/tty/serial/
Dsirfsoc_uart.h150 .sirfsoc_rx_done_en = BIT(0),
151 .sirfsoc_tx_done_en = BIT(1),
152 .sirfsoc_rx_oflow_en = BIT(2),
153 .sirfsoc_tx_allout_en = BIT(3),
154 .sirfsoc_rx_io_dma_en = BIT(4),
155 .sirfsoc_tx_io_dma_en = BIT(5),
156 .sirfsoc_rxfifo_full_en = BIT(6),
157 .sirfsoc_txfifo_empty_en = BIT(7),
158 .sirfsoc_rxfifo_thd_en = BIT(8),
159 .sirfsoc_txfifo_thd_en = BIT(9),
[all …]
/linux-4.1.27/drivers/staging/comedi/drivers/
Dz8536.h10 #define Z8536_INT_CTRL_MIE BIT(7) /* Master Interrupt Enable */
11 #define Z8536_INT_CTRL_DLC BIT(6) /* Disable Lower Chain */
12 #define Z8536_INT_CTRL_NV BIT(5) /* No Vector */
13 #define Z8536_INT_CTRL_PA_VIS BIT(4) /* Port A Vect Inc Status */
14 #define Z8536_INT_CTRL_PB_VIS BIT(3) /* Port B Vect Inc Status */
15 #define Z8536_INT_CTRL_VT_VIS BIT(2) /* C/T Vect Inc Status */
16 #define Z8536_INT_CTRL_RJA BIT(1) /* Right Justified Addresses */
17 #define Z8536_INT_CTRL_RESET BIT(0) /* Reset */
21 #define Z8536_CFG_CTRL_PBE BIT(7) /* Port B Enable */
22 #define Z8536_CFG_CTRL_CT1E BIT(6) /* C/T 1 Enable */
[all …]
/linux-4.1.27/drivers/usb/gadget/udc/
Dgr_udc.h51 #define GR_EPCTRL_PI BIT(20)
52 #define GR_EPCTRL_CB BIT(19)
53 #define GR_EPCTRL_CS BIT(18)
60 #define GR_EPCTRL_EH BIT(2)
61 #define GR_EPCTRL_ED BIT(1)
62 #define GR_EPCTRL_EV BIT(0)
64 #define GR_DMACTRL_AE BIT(10)
65 #define GR_DMACTRL_AD BIT(3)
66 #define GR_DMACTRL_AI BIT(2)
67 #define GR_DMACTRL_IE BIT(1)
[all …]
Dnet2280.c123 #define valid_bit cpu_to_le32(BIT(VALID_BIT))
124 #define dma_done_ie cpu_to_le32(BIT(DMA_DONE_INTERRUPT_ENABLE))
132 tmp |= BIT(ep->num); in enable_pciirqenb()
134 tmp |= BIT(ep_bit[ep->num]); in enable_pciirqenb()
200 writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat); in net2280_enable()
207 writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE), in net2280_enable()
226 tmp |= BIT(ENDPOINT_ENABLE); in net2280_enable()
232 tmp |= BIT(IN_ENDPOINT_ENABLE); in net2280_enable()
234 tmp |= BIT(ENDPOINT_DIRECTION); in net2280_enable()
237 tmp |= BIT(OUT_ENDPOINT_ENABLE); in net2280_enable()
[all …]
Dnet2280.h47 #define PLX_LEGACY BIT(0)
48 #define PLX_2280 BIT(1)
49 #define PLX_SUPERSPEED BIT(2)
120 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) | in allow_status()
121 BIT(CLEAR_NAK_OUT_PACKETS) | in allow_status()
122 BIT(CLEAR_NAK_OUT_PACKETS_MODE), in allow_status()
134 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp); in allow_status_338x()
196 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) | in set_halt()
199 BIT(SET_ENDPOINT_HALT), in set_halt()
206 writel(BIT(CLEAR_ENDPOINT_HALT) | in clear_halt()
[all …]
/linux-4.1.27/arch/mips/include/asm/mach-ralink/
Drt3883.h96 #define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
104 #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)
105 #define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)
106 #define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)
107 #define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)
108 #define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)
110 #define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)
111 #define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)
112 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
113 #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
[all …]
Drt288x.h38 #define RT2880_GPIO_MODE_I2C BIT(0)
39 #define RT2880_GPIO_MODE_UART0 BIT(1)
40 #define RT2880_GPIO_MODE_SPI BIT(2)
41 #define RT2880_GPIO_MODE_UART1 BIT(3)
42 #define RT2880_GPIO_MODE_JTAG BIT(4)
43 #define RT2880_GPIO_MODE_MDIO BIT(5)
44 #define RT2880_GPIO_MODE_SDRAM BIT(6)
45 #define RT2880_GPIO_MODE_PCI BIT(7)
47 #define CLKCFG_SRAM_CS_N_WDT BIT(9)
/linux-4.1.27/drivers/net/ethernet/sgi/
Dmeth.h117 #define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 cor…
118 #define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
119 #define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loo…
121 #define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */
122 #define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */
132 #define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link…
155 #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
156 #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
157 #define METH_DMA_RX_EN BIT(15) /* Enable RX */
158 #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
[all …]
/linux-4.1.27/drivers/net/wireless/ti/wl1251/
Devent.h39 RESERVED1_EVENT_ID = BIT(0),
40 RESERVED2_EVENT_ID = BIT(1),
41 MEASUREMENT_START_EVENT_ID = BIT(2),
42 SCAN_COMPLETE_EVENT_ID = BIT(3),
43 CALIBRATION_COMPLETE_EVENT_ID = BIT(4),
44 ROAMING_TRIGGER_LOW_RSSI_EVENT_ID = BIT(5),
45 PS_REPORT_EVENT_ID = BIT(6),
46 SYNCHRONIZATION_TIMEOUT_EVENT_ID = BIT(7),
47 HEALTH_REPORT_EVENT_ID = BIT(8),
48 ACI_DETECTION_EVENT_ID = BIT(9),
[all …]
/linux-4.1.27/drivers/net/ethernet/altera/
Daltera_sgdmahw.h54 #define SGDMA_STATUS_ERR BIT(0)
55 #define SGDMA_STATUS_LENGTH_ERR BIT(1)
56 #define SGDMA_STATUS_CRC_ERR BIT(2)
57 #define SGDMA_STATUS_TRUNC_ERR BIT(3)
58 #define SGDMA_STATUS_PHY_ERR BIT(4)
59 #define SGDMA_STATUS_COLL_ERR BIT(5)
60 #define SGDMA_STATUS_EOP BIT(7)
62 #define SGDMA_CONTROL_EOP BIT(0)
63 #define SGDMA_CONTROL_RD_FIXED BIT(1)
64 #define SGDMA_CONTROL_WR_FIXED BIT(2)
[all …]
Daltera_msgdmahw.h43 #define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
44 #define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
45 #define MSGDMA_DESC_CTL_PARK_READS BIT(10)
46 #define MSGDMA_DESC_CTL_PARK_WRITES BIT(11)
47 #define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
48 #define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
49 #define MSGDMA_DESC_CTL_TR_COMP_IRQ BIT(14)
50 #define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15)
52 #define MSGDMA_DESC_CTL_EARLY_DONE BIT(24)
56 #define MSGDMA_DESC_CTL_GO BIT(31)
[all …]
Daltera_tse.h67 #define MAC_CMDCFG_TX_ENA BIT(0)
68 #define MAC_CMDCFG_RX_ENA BIT(1)
69 #define MAC_CMDCFG_XON_GEN BIT(2)
70 #define MAC_CMDCFG_ETH_SPEED BIT(3)
71 #define MAC_CMDCFG_PROMIS_EN BIT(4)
72 #define MAC_CMDCFG_PAD_EN BIT(5)
73 #define MAC_CMDCFG_CRC_FWD BIT(6)
74 #define MAC_CMDCFG_PAUSE_FWD BIT(7)
75 #define MAC_CMDCFG_PAUSE_IGNORE BIT(8)
76 #define MAC_CMDCFG_TX_ADDR_INS BIT(9)
[all …]
/linux-4.1.27/include/linux/i2c/
Ddm355evm_msp.h30 # define MSP_STATUS_BAD_OFFSET BIT(0)
31 # define MSP_STATUS_BAD_COMMAND BIT(1)
32 # define MSP_STATUS_POWER_ERROR BIT(2)
33 # define MSP_STATUS_RXBUF_OVERRUN BIT(3)
35 # define MSP_RESET_DC5 BIT(0)
36 # define MSP_RESET_TVP5154 BIT(2)
37 # define MSP_RESET_IMAGER BIT(3)
38 # define MSP_RESET_ETHERNET BIT(4)
39 # define MSP_RESET_SYS BIT(5)
40 # define MSP_RESET_AIC33 BIT(7)
[all …]
/linux-4.1.27/sound/firewire/bebob/
Dbebob_command.c32 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_audio_set_selector()
33 BIT(6) | BIT(7) | BIT(8)); in avc_audio_set_selector()
68 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_audio_get_selector()
69 BIT(6) | BIT(8)); in avc_audio_get_selector()
121 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_bridgeco_get_plug_type()
122 BIT(6) | BIT(7) | BIT(9)); in avc_bridgeco_get_plug_type()
151 BIT(1) | BIT(2) | BIT(3) | BIT(4) | in avc_bridgeco_get_plug_ch_pos()
152 BIT(5) | BIT(6) | BIT(7) | BIT(9)); in avc_bridgeco_get_plug_ch_pos()
188 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_bridgeco_get_plug_section_type()
189 BIT(6) | BIT(7) | BIT(9) | BIT(10)); in avc_bridgeco_get_plug_section_type()
[all …]
/linux-4.1.27/include/video/
Dsstfb.h81 # define PCI_EN_INIT_WR BIT(0)
82 # define PCI_EN_FIFO_WR BIT(1)
83 # define PCI_REMAP_DAC BIT(2)
89 # define STATUS_FBI_BUSY BIT(7)
91 # define EN_CLIPPING BIT(0) /* enable clipping */
92 # define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */
93 # define EN_ALPHA_WRITE BIT(10)
94 # define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */
103 # define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/
104 # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
[all …]
Dtdfx.h90 #define AUTOINC_DSTX BIT(10)
91 #define AUTOINC_DSTY BIT(11)
97 #define STATUS_RETRACE BIT(6)
98 #define STATUS_BUSY BIT(9)
99 #define MISCINIT1_CLUT_INV BIT(0)
100 #define MISCINIT1_2DBLOCK_DIS BIT(15)
101 #define DRAMINIT0_SGRAM_NUM BIT(26)
102 #define DRAMINIT0_SGRAM_TYPE BIT(27)
103 #define DRAMINIT0_SGRAM_TYPE_MASK (BIT(27) | BIT(28) | BIT(29))
105 #define DRAMINIT1_MEM_SDRAM BIT(30)
[all …]
Ddisplay_timing.h16 DISPLAY_FLAGS_HSYNC_LOW = BIT(0),
17 DISPLAY_FLAGS_HSYNC_HIGH = BIT(1),
18 DISPLAY_FLAGS_VSYNC_LOW = BIT(2),
19 DISPLAY_FLAGS_VSYNC_HIGH = BIT(3),
22 DISPLAY_FLAGS_DE_LOW = BIT(4),
23 DISPLAY_FLAGS_DE_HIGH = BIT(5),
25 DISPLAY_FLAGS_PIXDATA_POSEDGE = BIT(6),
27 DISPLAY_FLAGS_PIXDATA_NEGEDGE = BIT(7),
28 DISPLAY_FLAGS_INTERLACED = BIT(8),
29 DISPLAY_FLAGS_DOUBLESCAN = BIT(9),
[all …]
/linux-4.1.27/drivers/input/mouse/
Dsentelic.h30 #define FSP_BIT_NO_ROTATION BIT(3)
35 #define FSP_BIT_EN_REG_CLK BIT(5)
38 #define FSP_BIT_EN_OPC_TAG BIT(7)
44 #define FSP_BIT_90_DEGREE BIT(0)
45 #define FSP_BIT_EN_MSID6 BIT(1)
46 #define FSP_BIT_EN_MSID7 BIT(2)
47 #define FSP_BIT_EN_MSID8 BIT(3)
48 #define FSP_BIT_EN_AUTO_MSID8 BIT(5)
49 #define FSP_BIT_EN_PKT_G0 BIT(6)
52 #define FSP_BIT_ONPAD_ENABLE BIT(0)
[all …]
/linux-4.1.27/drivers/net/wireless/iwlwifi/mvm/
Dfw-api-scan.h141 SCAN_CLIENT_SCHED_SCAN = BIT(0),
142 SCAN_CLIENT_NETDETECT = BIT(1),
143 SCAN_CLIENT_ASSET_TRACKING = BIT(2),
184 IWL_SCAN_OFFLOAD_CHANNEL_ACTIVE = BIT(0),
185 IWL_SCAN_OFFLOAD_CHANNEL_NARROW = BIT(22),
186 IWL_SCAN_OFFLOAD_CHANNEL_FULL = BIT(24),
187 IWL_SCAN_OFFLOAD_CHANNEL_PARTIAL = BIT(25),
299 IWL_SCAN_OFFLOAD_FLAG_PASS_ALL = BIT(0),
300 IWL_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = BIT(2),
301 IWL_SCAN_OFFLOAD_FLAG_EBS_QUICK_MODE = BIT(5),
[all …]
Dfw-api.h301 IWL_CALIB_CFG_XTAL_IDX = BIT(0),
302 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(1),
303 IWL_CALIB_CFG_VOLTAGE_READ_IDX = BIT(2),
304 IWL_CALIB_CFG_PAPD_IDX = BIT(3),
305 IWL_CALIB_CFG_TX_PWR_IDX = BIT(4),
306 IWL_CALIB_CFG_DC_IDX = BIT(5),
307 IWL_CALIB_CFG_BB_FILTER_IDX = BIT(6),
308 IWL_CALIB_CFG_LO_LEAKAGE_IDX = BIT(7),
309 IWL_CALIB_CFG_TX_IQ_IDX = BIT(8),
310 IWL_CALIB_CFG_TX_IQ_SKEW_IDX = BIT(9),
[all …]
Dfw-api-coex.h71 #define BITS(nb) (BIT(nb) - 1)
102 BT_COEX_SYNC2SCO = BIT(7),
103 BT_COEX_CORUNNING = BIT(8),
104 BT_COEX_MPLUT = BIT(9),
105 BT_COEX_TTC = BIT(20),
106 BT_COEX_RRC = BIT(21),
115 BT_VALID_ENABLE = BIT(0),
116 BT_VALID_BT_PRIO_BOOST = BIT(1),
117 BT_VALID_MAX_KILL = BIT(2),
118 BT_VALID_3W_TMRS = BIT(3),
[all …]
Dfw-api-sta.h93 STA_FLG_REDUCED_TX_PWR_CTRL = BIT(3),
94 STA_FLG_REDUCED_TX_PWR_DATA = BIT(6),
96 STA_FLG_DISABLE_TX = BIT(4),
98 STA_FLG_PS = BIT(8),
99 STA_FLG_DRAIN_FLOW = BIT(12),
100 STA_FLG_PAN = BIT(13),
101 STA_FLG_CLASS_AUTH = BIT(14),
102 STA_FLG_CLASS_ASSOC = BIT(15),
103 STA_FLG_RTS_MIMO_PROT = BIT(17),
163 STA_KEY_FLG_WEP_KEY_MAP = BIT(3),
[all …]
Dfw-api-d3.h73 IWL_WAKEUP_D3_CONFIG_FW_ERROR = BIT(0),
99 IWL_D3_PROTO_OFFLOAD_ARP = BIT(0),
100 IWL_D3_PROTO_OFFLOAD_NS = BIT(1),
225 IWL_WOWLAN_WAKEUP_MAGIC_PACKET = BIT(0),
226 IWL_WOWLAN_WAKEUP_PATTERN_MATCH = BIT(1),
227 IWL_WOWLAN_WAKEUP_BEACON_MISS = BIT(2),
228 IWL_WOWLAN_WAKEUP_LINK_CHANGE = BIT(3),
229 IWL_WOWLAN_WAKEUP_GTK_REKEY_FAIL = BIT(4),
230 IWL_WOWLAN_WAKEUP_EAP_IDENT_REQ = BIT(5),
231 IWL_WOWLAN_WAKEUP_4WAY_HANDSHAKE = BIT(6),
[all …]
Dfw-api-tx.h100 TX_CMD_FLG_PROT_REQUIRE = BIT(0),
101 TX_CMD_FLG_WRITE_TX_POWER = BIT(1),
102 TX_CMD_FLG_ACK = BIT(3),
103 TX_CMD_FLG_STA_RATE = BIT(4),
104 TX_CMD_FLG_BAR = BIT(6),
105 TX_CMD_FLG_TXOP_PROT = BIT(7),
106 TX_CMD_FLG_VHT_NDPA = BIT(8),
107 TX_CMD_FLG_HT_NDPA = BIT(9),
108 TX_CMD_FLG_CSI_FDBK2HOST = BIT(10),
110 TX_CMD_FLG_BT_DIS = BIT(12),
[all …]
Dfw-api-mac.h93 MAC_PROT_FLG_TGG_PROTECT = BIT(3),
94 MAC_PROT_FLG_HT_PROT = BIT(23),
95 MAC_PROT_FLG_FAT_PROT = BIT(24),
96 MAC_PROT_FLG_SELF_CTS_EN = BIT(30),
99 #define MAC_FLG_SHORT_SLOT BIT(4)
100 #define MAC_FLG_SHORT_PREAMBLE BIT(5)
270 MAC_FILTER_IN_PROMISC = BIT(0),
271 MAC_FILTER_IN_CONTROL_AND_MGMT = BIT(1),
272 MAC_FILTER_ACCEPT_GRP = BIT(2),
273 MAC_FILTER_DIS_DECRYPT = BIT(3),
[all …]
Dfw-api-power.h85 LTR_CFG_FLAG_FEATURE_ENABLE = BIT(0),
86 LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS = BIT(1),
87 LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH = BIT(2),
88 LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 = BIT(3),
89 LTR_CFG_FLAG_SW_SET_SHORT = BIT(4),
90 LTR_CFG_FLAG_SW_SET_LONG = BIT(5),
91 LTR_CFG_FLAG_DENIE_C10_ON_PD = BIT(6),
145 POWER_FLAGS_POWER_SAVE_ENA_MSK = BIT(0),
146 POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = BIT(1),
147 POWER_FLAGS_SKIP_OVER_DTIM_MSK = BIT(2),
[all …]
/linux-4.1.27/include/linux/rtc/
Dds1685.h136 #define RTC_HRS_AMPM_MASK BIT(7) /* Mask for the AM/PM bit */
154 #define RTC_CTRL_A_UIP BIT(7) /* Update In Progress */
155 #define RTC_CTRL_A_DV2 BIT(6) /* Countdown Chain */
156 #define RTC_CTRL_A_DV1 BIT(5) /* Oscillator Enable */
157 #define RTC_CTRL_A_DV0 BIT(4) /* Bank Select */
158 #define RTC_CTRL_A_RS2 BIT(2) /* Rate-Selection Bit 2 */
159 #define RTC_CTRL_A_RS3 BIT(3) /* Rate-Selection Bit 3 */
160 #define RTC_CTRL_A_RS1 BIT(1) /* Rate-Selection Bit 1 */
161 #define RTC_CTRL_A_RS0 BIT(0) /* Rate-Selection Bit 0 */
167 #define RTC_CTRL_B_SET BIT(7) /* SET Bit */
[all …]
/linux-4.1.27/sound/soc/fsl/
Dfsl_sai.h49 #define FSL_SAI_CSR_TERE BIT(31)
50 #define FSL_SAI_CSR_FR BIT(25)
51 #define FSL_SAI_CSR_SR BIT(24)
56 #define FSL_SAI_CSR_WSF BIT(20)
57 #define FSL_SAI_CSR_SEF BIT(19)
58 #define FSL_SAI_CSR_FEF BIT(18)
59 #define FSL_SAI_CSR_FWF BIT(17)
60 #define FSL_SAI_CSR_FRF BIT(16)
63 #define FSL_SAI_CSR_WSIE BIT(12)
64 #define FSL_SAI_CSR_SEIE BIT(11)
[all …]
/linux-4.1.27/drivers/gpu/drm/tilcdc/
Dtilcdc_regs.h28 #define LCDC_END_OF_FRAME1 BIT(9)
29 #define LCDC_END_OF_FRAME0 BIT(8)
30 #define LCDC_PL_LOAD_DONE BIT(6)
31 #define LCDC_FIFO_UNDERFLOW BIT(5)
32 #define LCDC_SYNC_LOST BIT(2)
33 #define LCDC_FRAME_DONE BIT(0)
42 #define LCDC_V1_END_OF_FRAME_INT_ENA BIT(2)
43 #define LCDC_V2_END_OF_FRAME0_INT_ENA BIT(8)
44 #define LCDC_V2_END_OF_FRAME1_INT_ENA BIT(9)
45 #define LCDC_DUAL_FRAME_BUFFER_ENABLE BIT(0)
[all …]
/linux-4.1.27/drivers/net/ethernet/smsc/
Dsmsc9420.h54 #define BUS_MODE_SWR_ (BIT(0))
55 #define BUS_MODE_DMA_BURST_LENGTH_1 (BIT(8))
56 #define BUS_MODE_DMA_BURST_LENGTH_2 (BIT(9))
57 #define BUS_MODE_DMA_BURST_LENGTH_4 (BIT(10))
58 #define BUS_MODE_DMA_BURST_LENGTH_8 (BIT(11))
59 #define BUS_MODE_DMA_BURST_LENGTH_16 (BIT(12))
60 #define BUS_MODE_DMA_BURST_LENGTH_32 (BIT(13))
61 #define BUS_MODE_DBO_ (BIT(20))
74 #define DMAC_STS_NIS_ (BIT(16))
75 #define DMAC_STS_AIS_ (BIT(15))
[all …]
/linux-4.1.27/drivers/mfd/
Ddbx500-prcmu-regs.h16 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
60 #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0)
61 #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16)
74 #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
75 #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
84 #define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16)
92 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0)
93 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1)
94 #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2)
112 #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11)
[all …]
/linux-4.1.27/drivers/clk/sunxi/
Dclk-usb.c49 writel(reg & ~BIT(id), data->reg); in sunxi_usb_reset_assert()
70 writel(reg | BIT(id), data->reg); in sunxi_usb_reset_deassert()
173 .clk_mask = BIT(8) | BIT(7) | BIT(6),
174 .reset_mask = BIT(2) | BIT(1) | BIT(0),
186 .clk_mask = BIT(8) | BIT(6),
187 .reset_mask = BIT(1) | BIT(0),
197 .clk_mask = BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8),
198 .reset_mask = BIT(2) | BIT(1) | BIT(0),
208 .clk_mask = BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
209 .reset_mask = BIT(19) | BIT(18) | BIT(17),
[all …]
/linux-4.1.27/drivers/net/wireless/ti/wl12xx/
Devent.h28 MEASUREMENT_START_EVENT_ID = BIT(8),
29 MEASUREMENT_COMPLETE_EVENT_ID = BIT(9),
30 SCAN_COMPLETE_EVENT_ID = BIT(10),
31 WFD_DISCOVERY_COMPLETE_EVENT_ID = BIT(11),
32 AP_DISCOVERY_COMPLETE_EVENT_ID = BIT(12),
33 RESERVED1 = BIT(13),
34 PSPOLL_DELIVERY_FAILURE_EVENT_ID = BIT(14),
35 ROLE_STOP_COMPLETE_EVENT_ID = BIT(15),
36 RADAR_DETECTED_EVENT_ID = BIT(16),
37 CHANNEL_SWITCH_COMPLETE_EVENT_ID = BIT(17),
[all …]
Dreg.h252 #define ACX_REG_EEPROM_START_BIT BIT(1)
383 #define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */
384 #define OFDM_RATE_BIT BIT(6)
385 #define PBCC_RATE_BIT BIT(7)
419 #define OCP_READY_MASK BIT(18)
420 #define OCP_STATUS_MASK (BIT(16) | BIT(17))
431 #define POLARITY_LOW BIT(1)
432 #define NO_PULL (BIT(14) | BIT(15))
444 #define MCS_PLL_CLK_SEL_FREF BIT(0)
446 #define WL_CLK_REQ_TYPE_FREF BIT(3)
[all …]
/linux-4.1.27/drivers/edac/
Damd8111_edac.h32 PCI_STSCMD_SSE = BIT(30),
33 PCI_STSCMD_RMA = BIT(29),
34 PCI_STSCMD_RTA = BIT(28),
35 PCI_STSCMD_SERREN = BIT(8),
46 MEM_LIMIT_DPE = BIT(31),
47 MEM_LIMIT_RSE = BIT(30),
48 MEM_LIMIT_RMA = BIT(29),
49 MEM_LIMIT_RTA = BIT(28),
50 MEM_LIMIT_STA = BIT(27),
51 MEM_LIMIT_MDPE = BIT(24),
[all …]
Damd8131_edac.h37 STS_CMD_SSE = BIT(30),
38 STS_CMD_SERREN = BIT(8)
46 INT_CTLR_DTSE = BIT(27),
47 INT_CTLR_DTS = BIT(26),
48 INT_CTLR_SERR = BIT(17),
49 INT_CTLR_PERR = BIT(16)
57 MEM_LIMIT_DPE = BIT(31),
58 MEM_LIMIT_RSE = BIT(30),
59 MEM_LIMIT_RMA = BIT(29),
60 MEM_LIMIT_RTA = BIT(28),
[all …]
/linux-4.1.27/drivers/gpu/drm/i2c/
Dadv7511.h90 #define ADV7511_CSC_ENABLE BIT(7)
91 #define ADV7511_CSC_UPDATE_MODE BIT(5)
93 #define ADV7511_INT0_HDP BIT(7)
94 #define ADV7511_INT0_VSYNC BIT(5)
95 #define ADV7511_INT0_AUDIO_FIFO_FULL BIT(4)
96 #define ADV7511_INT0_EDID_READY BIT(2)
97 #define ADV7511_INT0_HDCP_AUTHENTICATED BIT(1)
99 #define ADV7511_INT1_DDC_ERROR BIT(7)
100 #define ADV7511_INT1_BKSV BIT(6)
101 #define ADV7511_INT1_CEC_TX_READY BIT(5)
[all …]
/linux-4.1.27/drivers/staging/iio/accel/
Dadis16220.h74 #define ADIS16220_MSC_CTRL_SELF_TEST_EN BIT(8)
75 #define ADIS16220_MSC_CTRL_POWER_SUP_COM_AIN1 BIT(1)
76 #define ADIS16220_MSC_CTRL_POWER_SUP_COM_AIN2 BIT(0)
79 #define ADIS16220_MSC_CTRL_DIO2_BUSY_IND (BIT(5) | BIT(4))
80 #define ADIS16220_MSC_CTRL_DIO1_BUSY_IND (BIT(3) | BIT(2))
81 #define ADIS16220_MSC_CTRL_DIO2_ACT_HIGH BIT(1)
82 #define ADIS16220_MSC_CTRL_DIO1_ACT_HIGH BIT(0)
86 #define ADIS16220_DIAG_STAT_ALM_MAG2 BIT(14)
88 #define ADIS16220_DIAG_STAT_ALM_MAG1 BIT(13)
90 #define ADIS16220_DIAG_STAT_ALM_MAGA BIT(12)
[all …]
Dadis16240.h77 #define ADIS16240_MSC_CTRL_XYZPEAK_OUT_EN BIT(15)
79 #define ADIS16240_MSC_CTRL_X_Y_ZPEAK_OUT_EN BIT(14)
81 #define ADIS16240_MSC_CTRL_SELF_TEST_EN BIT(8)
83 #define ADIS16240_MSC_CTRL_DATA_RDY_EN BIT(2)
85 #define ADIS16240_MSC_CTRL_ACTIVE_HIGH BIT(1)
87 #define ADIS16240_MSC_CTRL_DATA_RDY_DIO2 BIT(0)
91 #define ADIS16240_DIAG_STAT_ALARM2 BIT(9)
93 #define ADIS16240_DIAG_STAT_ALARM1 BIT(8)
95 #define ADIS16240_DIAG_STAT_CPT_BUF_FUL BIT(7)
97 #define ADIS16240_DIAG_STAT_CHKSUM BIT(6)
[all …]
Dadis16203.h28 #define ADIS16203_MSC_CTRL_PWRUP_SELF_TEST BIT(10) /* Self-test at power-on: 1 = disabled, 0 = enab…
29 #define ADIS16203_MSC_CTRL_REVERSE_ROT_EN BIT(9) /* Reverses rotation of both inclination outputs …
30 #define ADIS16203_MSC_CTRL_SELF_TEST_EN BIT(8) /* Self-test enable */
31 #define ADIS16203_MSC_CTRL_DATA_RDY_EN BIT(2) /* Data-ready enable: 1 = enabled, 0 = disab…
32 #define ADIS16203_MSC_CTRL_ACTIVE_HIGH BIT(1) /* Data-ready polarity: 1 = active high, 0 =…
33 #define ADIS16203_MSC_CTRL_DATA_RDY_DIO1 BIT(0) /* Data-ready line selection: 1 = DIO1, 0 = DIO0 */
36 #define ADIS16203_DIAG_STAT_ALARM2 BIT(9) /* Alarm 2 status: 1 = alarm active, 0 = alarm ina…
37 #define ADIS16203_DIAG_STAT_ALARM1 BIT(8) /* Alarm 1 status: 1 = alarm active, 0 = alarm ina…
45 #define ADIS16203_GLOB_CMD_SW_RESET BIT(7)
46 #define ADIS16203_GLOB_CMD_CLEAR_STAT BIT(4)
[all …]
Dadis16204.h36 #define ADIS16204_MSC_CTRL_PWRUP_SELF_TEST BIT(10) /* Self-test at power-on: 1 = disabled, 0 = enab…
37 #define ADIS16204_MSC_CTRL_SELF_TEST_EN BIT(8) /* Self-test enable */
38 #define ADIS16204_MSC_CTRL_DATA_RDY_EN BIT(2) /* Data-ready enable: 1 = enabled, 0 = disab…
39 #define ADIS16204_MSC_CTRL_ACTIVE_HIGH BIT(1) /* Data-ready polarity: 1 = active high, 0 =…
40 #define ADIS16204_MSC_CTRL_DATA_RDY_DIO2 BIT(0) /* Data-ready line selection: 1 = DIO2, 0 = DIO1 */
43 #define ADIS16204_DIAG_STAT_ALARM2 BIT(9) /* Alarm 2 status: 1 = alarm active, 0 = alarm ina…
44 #define ADIS16204_DIAG_STAT_ALARM1 BIT(8) /* Alarm 1 status: 1 = alarm active, 0 = alarm ina…
53 #define ADIS16204_GLOB_CMD_SW_RESET BIT(7)
54 #define ADIS16204_GLOB_CMD_CLEAR_STAT BIT(4)
55 #define ADIS16204_GLOB_CMD_FACTORY_CAL BIT(1)
[all …]
Dadis16209.h63 #define ADIS16209_MSC_CTRL_PWRUP_SELF_TEST BIT(10)
65 #define ADIS16209_MSC_CTRL_SELF_TEST_EN BIT(8)
67 #define ADIS16209_MSC_CTRL_DATA_RDY_EN BIT(2)
69 #define ADIS16209_MSC_CTRL_ACTIVE_HIGH BIT(1)
71 #define ADIS16209_MSC_CTRL_DATA_RDY_DIO2 BIT(0)
75 #define ADIS16209_DIAG_STAT_ALARM2 BIT(9)
77 #define ADIS16209_DIAG_STAT_ALARM1 BIT(8)
90 #define ADIS16209_GLOB_CMD_SW_RESET BIT(7)
91 #define ADIS16209_GLOB_CMD_CLEAR_STAT BIT(4)
92 #define ADIS16209_GLOB_CMD_FACTORY_CAL BIT(1)
[all …]
/linux-4.1.27/drivers/staging/iio/frequency/
Dad9834.h14 #define AD9834_REG_FREQ0 BIT(14)
15 #define AD9834_REG_FREQ1 BIT(15)
16 #define AD9834_REG_PHASE0 (BIT(15) | BIT(14))
17 #define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13))
21 #define AD9834_B28 BIT(13)
22 #define AD9834_HLB BIT(12)
23 #define AD9834_FSEL BIT(11)
24 #define AD9834_PSEL BIT(10)
25 #define AD9834_PIN_SW BIT(9)
26 #define AD9834_RESET BIT(8)
[all …]
/linux-4.1.27/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_reg.h202 #define SXGBE_CORE_RSS_CTL_UDP4TE BIT(3)
203 #define SXGBE_CORE_RSS_CTL_TCP4TE BIT(2)
204 #define SXGBE_CORE_RSS_CTL_IP2TE BIT(1)
205 #define SXGBE_CORE_RSS_CTL_RSSE BIT(0)
266 #define SXGBE_MTL_SFMODE BIT(1)
281 #define SXGBE_RX_MTL_SFMODE BIT(5)
298 #define SXGBE_DMA_SOFT_RESET BIT(0)
300 #define SXGBE_DMA_AXI_UNDEF_BURST BIT(0)
301 #define SXGBE_DMA_ENHACE_ADDR_MODE BIT(11)
317 #define SXGBE_DMA_PBL_X8MODE BIT(16)
[all …]
/linux-4.1.27/drivers/net/wireless/iwlwifi/
Diwl-fw-file.h220 IWL_UCODE_TLV_FLAGS_PAN = BIT(0),
221 IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1),
222 IWL_UCODE_TLV_FLAGS_MFP = BIT(2),
223 IWL_UCODE_TLV_FLAGS_P2P = BIT(3),
224 IWL_UCODE_TLV_FLAGS_DW_BC_TABLE = BIT(4),
225 IWL_UCODE_TLV_FLAGS_SHORT_BL = BIT(7),
226 IWL_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = BIT(10),
227 IWL_UCODE_TLV_FLAGS_NO_BASIC_SSID = BIT(12),
228 IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = BIT(15),
229 IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = BIT(16),
[all …]
/linux-4.1.27/arch/arm/include/asm/hardware/
Dcache-l2x0.h94 #define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20)
95 #define L2C_AUX_CTRL_PARITY_ENABLE BIT(21)
96 #define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22)
109 #define L210_AUX_CTRL_WRAP_DISABLE BIT(12)
110 #define L210_AUX_CTRL_WA_OVERRIDE BIT(23)
111 #define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24)
113 #define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
116 #define L220_AUX_CTRL_NS_LOCKDOWN BIT(26)
117 #define L220_AUX_CTRL_NS_INT_CTRL BIT(27)
119 #define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
[all …]
/linux-4.1.27/drivers/crypto/ux500/cryp/
Dcryp_p.h68 #define CRYP_CR_SECURE_MASK BIT(0)
69 #define CRYP_CR_PRLG_MASK BIT(1)
70 #define CRYP_CR_ALGODIR_MASK BIT(2)
71 #define CRYP_CR_ALGOMODE_MASK (BIT(5) | BIT(4) | BIT(3))
72 #define CRYP_CR_DATATYPE_MASK (BIT(7) | BIT(6))
73 #define CRYP_CR_KEYSIZE_MASK (BIT(9) | BIT(8))
74 #define CRYP_CR_KEYRDEN_MASK BIT(10)
75 #define CRYP_CR_KSE_MASK BIT(11)
76 #define CRYP_CR_START_MASK BIT(12)
77 #define CRYP_CR_INIT_MASK BIT(13)
[all …]
/linux-4.1.27/drivers/clk/ux500/
Du8540_clk.c223 BIT(0), 0); in u8540_clk_init()
227 BIT(1), 0); in u8540_clk_init()
231 BIT(2), 0); in u8540_clk_init()
235 BIT(3), 0); in u8540_clk_init()
240 BIT(4), 0); in u8540_clk_init()
245 BIT(5), 0); in u8540_clk_init()
249 BIT(6), 0); in u8540_clk_init()
253 BIT(7), 0); in u8540_clk_init()
257 BIT(8), 0); in u8540_clk_init()
261 BIT(9), 0); in u8540_clk_init()
[all …]
Du8500_of_clk.c250 BIT(0), 0); in u8500_of_clk_init()
254 BIT(1), 0); in u8500_of_clk_init()
258 BIT(2), 0); in u8500_of_clk_init()
262 BIT(3), 0); in u8500_of_clk_init()
266 BIT(4), 0); in u8500_of_clk_init()
270 BIT(5), 0); in u8500_of_clk_init()
274 BIT(6), 0); in u8500_of_clk_init()
278 BIT(7), 0); in u8500_of_clk_init()
282 BIT(8), 0); in u8500_of_clk_init()
286 BIT(9), 0); in u8500_of_clk_init()
[all …]
Du8500_clk.c219 BIT(0), 0); in u8500_clk_init()
223 BIT(1), 0); in u8500_clk_init()
227 BIT(2), 0); in u8500_clk_init()
231 BIT(3), 0); in u8500_clk_init()
236 BIT(4), 0); in u8500_clk_init()
241 BIT(5), 0); in u8500_clk_init()
245 BIT(6), 0); in u8500_clk_init()
249 BIT(7), 0); in u8500_clk_init()
253 BIT(8), 0); in u8500_clk_init()
257 BIT(9), 0); in u8500_clk_init()
[all …]
/linux-4.1.27/include/linux/
Dedac.h114 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
115 #define DEV_FLAG_X1 BIT(DEV_X1)
116 #define DEV_FLAG_X2 BIT(DEV_X2)
117 #define DEV_FLAG_X4 BIT(DEV_X4)
118 #define DEV_FLAG_X8 BIT(DEV_X8)
119 #define DEV_FLAG_X16 BIT(DEV_X16)
120 #define DEV_FLAG_X32 BIT(DEV_X32)
121 #define DEV_FLAG_X64 BIT(DEV_X64)
225 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
226 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
[all …]
Domap-dma.h108 #define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
109 #define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
110 #define DMA_ERRATA_i378 BIT(0x2)
111 #define DMA_ERRATA_i541 BIT(0x3)
112 #define DMA_ERRATA_i88 BIT(0x4)
113 #define DMA_ERRATA_3_3 BIT(0x5)
114 #define DMA_ROMCODE_BUG BIT(0x6)
117 #define DMA_LINKED_LCH BIT(0x0)
118 #define GLOBAL_PRIORITY BIT(0x1)
119 #define RESERVE_CHANNEL BIT(0x2)
[all …]
Dif_bridge.h36 #define BR_HAIRPIN_MODE BIT(0)
37 #define BR_BPDU_GUARD BIT(1)
38 #define BR_ROOT_BLOCK BIT(2)
39 #define BR_MULTICAST_FAST_LEAVE BIT(3)
40 #define BR_ADMIN_COST BIT(4)
41 #define BR_LEARNING BIT(5)
42 #define BR_FLOOD BIT(6)
44 #define BR_PROMISC BIT(7)
45 #define BR_PROXYARP BIT(8)
46 #define BR_LEARNING_SYNC BIT(9)
[all …]
/linux-4.1.27/sound/soc/codecs/
Dsta350.h100 #define STA350_CONFA_TWRB BIT(5)
101 #define STA350_CONFA_TWAB BIT(6)
102 #define STA350_CONFA_FDRB BIT(7)
107 #define STA350_CONFB_SAIFB BIT(4)
108 #define STA350_CONFB_DSCKE BIT(5)
109 #define STA350_CONFB_C1IM BIT(6)
110 #define STA350_CONFB_C2IM BIT(7)
117 #define STA350_CONFC_OCRB BIT(7)
130 #define STA350_CONFE_MPCV BIT(0)
132 #define STA350_CONFE_MPC BIT(1)
[all …]
Dlm49453.h250 #define LM49453_PMC_SETUP_CHIP_EN (BIT(1)|BIT(0))
251 #define LM49453_PMC_SETUP_PLL_EN BIT(2)
252 #define LM49453_PMC_SETUP_PLL_P2_EN BIT(3)
253 #define LM49453_PMC_SETUP_PLL_FLL BIT(4)
254 #define LM49453_PMC_SETUP_MCLK_OVER BIT(5)
255 #define LM49453_PMC_SETUP_RTC_CLK_OVER BIT(6)
256 #define LM49453_PMC_SETUP_CHIP_ACTIVE BIT(7)
280 #define LM49453_ADC_DSP_ADC_MUTEL BIT(0)
281 #define LM49453_ADC_DSP_ADC_MUTER BIT(1)
282 #define LM49453_ADC_DSP_DMIC1_MUTEL BIT(2)
[all …]
Dsn95031.c51 snd_soc_write(codec, SN95031_VAUD, BIT(2)|BIT(1)|BIT(0)); in sn95031_enable_mic_bias()
52 snd_soc_update_bits(codec, SN95031_MICBIAS, BIT(2), BIT(2)); in sn95031_enable_mic_bias()
200 snd_soc_write(codec, SN95031_AUDPLLCTRL, BIT(5)); in sn95031_set_vaud_bias()
203 BIT(0), BIT(0)); in sn95031_set_vaud_bias()
212 BIT(2)|BIT(1)|BIT(0)); in sn95031_set_vaud_bias()
217 snd_soc_update_bits(codec, SN95031_PCM2C2, BIT(0), 0); in sn95031_set_vaud_bias()
225 snd_soc_write(codec, SN95031_VAUD, BIT(3)); in sn95031_set_vaud_bias()
276 ldo = BIT(5)|BIT(4); in sn95031_dmic12_event()
277 clk_dir = BIT(0); in sn95031_dmic12_event()
278 data_dir = BIT(7); in sn95031_dmic12_event()
[all …]
/linux-4.1.27/drivers/dma/hsu/
Dhsu.h41 #define HSU_CH_SR_DESCTO(x) BIT(8 + (x))
42 #define HSU_CH_SR_DESCTO_ANY (BIT(11) | BIT(10) | BIT(9) | BIT(8))
43 #define HSU_CH_SR_CHE BIT(15)
44 #define HSU_CH_SR_DESCE(x) BIT(16 + (x))
45 #define HSU_CH_SR_DESCE_ANY (BIT(19) | BIT(18) | BIT(17) | BIT(16))
46 #define HSU_CH_SR_CDESC_ANY (BIT(31) | BIT(30))
49 #define HSU_CH_CR_CHA BIT(0)
50 #define HSU_CH_CR_CHD BIT(1)
53 #define HSU_CH_DCR_DESCA(x) BIT(0 + (x))
54 #define HSU_CH_DCR_CHSOD(x) BIT(8 + (x))
[all …]
/linux-4.1.27/sound/soc/ux500/
Dux500_msp_i2s.h109 #define RX_ENABLE_MASK BIT(0)
110 #define RX_FIFO_ENABLE_MASK BIT(1)
111 #define RX_FSYNC_MASK BIT(2)
112 #define DIRECT_COMPANDING_MASK BIT(3)
113 #define RX_SYNC_SEL_MASK BIT(4)
114 #define RX_CLK_POL_MASK BIT(5)
115 #define RX_CLK_SEL_MASK BIT(6)
116 #define LOOPBACK_MASK BIT(7)
117 #define TX_ENABLE_MASK BIT(8)
118 #define TX_FIFO_ENABLE_MASK BIT(9)
[all …]
/linux-4.1.27/arch/sh/include/mach-sdk7786/mach/
Dfpga.h19 #define NMISR_MAN_NMI BIT(0)
20 #define NMISR_AUX_NMI BIT(1)
24 #define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */
25 #define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */
41 #define PCIECR_PCIEMUX1 BIT(15)
42 #define PCIECR_PCIEMUX0 BIT(14)
43 #define PCIECR_PRST4 BIT(12) /* slot 4 card present */
44 #define PCIECR_PRST3 BIT(11) /* slot 3 card present */
45 #define PCIECR_PRST2 BIT(10) /* slot 2 card present */
46 #define PCIECR_PRST1 BIT(9) /* slot 1 card present */
[all …]
/linux-4.1.27/drivers/phy/
Dphy-spear1310-miphy.c29 #define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31)
30 #define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30)
31 #define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29)
32 #define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27)
33 #define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26)
34 #define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25)
35 #define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24)
36 #define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23)
37 #define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22)
38 #define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21)
[all …]
Dphy-exynos4210-usb2.c23 #define EXYNOS_4210_UPHYPWR_PHY0_SUSPEND BIT(0)
24 #define EXYNOS_4210_UPHYPWR_PHY0_PWR BIT(3)
25 #define EXYNOS_4210_UPHYPWR_PHY0_OTG_PWR BIT(4)
26 #define EXYNOS_4210_UPHYPWR_PHY0_SLEEP BIT(5)
33 #define EXYNOS_4210_UPHYPWR_PHY1_SUSPEND BIT(6)
34 #define EXYNOS_4210_UPHYPWR_PHY1_PWR BIT(7)
35 #define EXYNOS_4210_UPHYPWR_PHY1_SLEEP BIT(8)
41 #define EXYNOS_4210_UPHYPWR_HSIC0_SUSPEND BIT(9)
42 #define EXYNOS_4210_UPHYPWR_HSIC0_SLEEP BIT(10)
47 #define EXYNOS_4210_UPHYPWR_HSIC1_SUSPEND BIT(11)
[all …]
Dphy-exynos5250-usb2.c34 #define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL BIT(31)
41 #define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNIN BIT(11)
42 #define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE BIT(10)
43 #define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N BIT(9)
48 #define EXYNOS_5250_HOSTPHYCTRL0_SIDDQ BIT(6)
49 #define EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEP BIT(5)
50 #define EXYNOS_5250_HOSTPHYCTRL0_FORCESUSPEND BIT(4)
51 #define EXYNOS_5250_HOSTPHYCTRL0_WORDINTERFACE BIT(3)
52 #define EXYNOS_5250_HOSTPHYCTRL0_UTMISWRST BIT(2)
53 #define EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST BIT(1)
[all …]
Dphy-exynos4x12-usb2.c23 #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0)
24 #define EXYNOS_4x12_UPHYPWR_PHY0_PWR BIT(3)
25 #define EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR BIT(4)
26 #define EXYNOS_4x12_UPHYPWR_PHY0_SLEEP BIT(5)
33 #define EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND BIT(6)
34 #define EXYNOS_4x12_UPHYPWR_PHY1_PWR BIT(7)
35 #define EXYNOS_4x12_UPHYPWR_PHY1_SLEEP BIT(8)
41 #define EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND BIT(9)
42 #define EXYNOS_4x12_UPHYPWR_HSIC0_PWR BIT(10)
43 #define EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP BIT(11)
[all …]
Dphy-berlin-usb.c34 #define CLK_STABLE BIT(0)
35 #define PLL_CTRL_PIN BIT(1)
36 #define PLL_CTRL_REG BIT(2)
37 #define PLL_ON BIT(3)
39 #define PHASE_OFF_TOL_250 BIT(5)
41 #define KVC0_REG_CTRL BIT(9)
44 #define CLK_BLK_EN BIT(13)
47 #define EXT_HS_RCAL_EN BIT(3)
48 #define EXT_FS_RCAL_EN BIT(4)
55 #define TX_VDD15_15 BIT(4)
[all …]
Dphy-s5pv210-usb2.c22 #define S5PV210_UPHYPWR_PHY0_SUSPEND BIT(0)
23 #define S5PV210_UPHYPWR_PHY0_PWR BIT(3)
24 #define S5PV210_UPHYPWR_PHY0_OTG_PWR BIT(4)
30 #define S5PV210_UPHYPWR_PHY1_SUSPEND BIT(6)
31 #define S5PV210_UPHYPWR_PHY1_PWR BIT(7)
44 #define S5PV210_UPHYCLK_PHY0_ID_PULLUP BIT(2)
45 #define S5PV210_UPHYCLK_PHY0_COMMON_ON BIT(4)
46 #define S5PV210_UPHYCLK_PHY1_COMMON_ON BIT(7)
51 #define S5PV210_URSTCON_PHY0 BIT(0)
52 #define S5PV210_URSTCON_OTG_HLINK BIT(1)
[all …]
/linux-4.1.27/drivers/net/wireless/ti/wlcore/
Ddebug.h36 DEBUG_IRQ = BIT(0),
37 DEBUG_SPI = BIT(1),
38 DEBUG_BOOT = BIT(2),
39 DEBUG_MAILBOX = BIT(3),
40 DEBUG_TESTMODE = BIT(4),
41 DEBUG_EVENT = BIT(5),
42 DEBUG_TX = BIT(6),
43 DEBUG_RX = BIT(7),
44 DEBUG_SCAN = BIT(8),
45 DEBUG_CRYPT = BIT(9),
[all …]
/linux-4.1.27/drivers/net/wireless/ath/ath6kl/
Ddebug.h25 ATH6KL_DBG_CREDIT = BIT(0),
27 ATH6KL_DBG_WLAN_TX = BIT(2), /* wlan tx */
28 ATH6KL_DBG_WLAN_RX = BIT(3), /* wlan rx */
29 ATH6KL_DBG_BMI = BIT(4), /* bmi tracing */
30 ATH6KL_DBG_HTC = BIT(5),
31 ATH6KL_DBG_HIF = BIT(6),
32 ATH6KL_DBG_IRQ = BIT(7), /* interrupt processing */
35 ATH6KL_DBG_WMI = BIT(10), /* wmi tracing */
36 ATH6KL_DBG_TRC = BIT(11), /* generic func tracing */
37 ATH6KL_DBG_SCATTER = BIT(12), /* hif scatter tracing */
[all …]
/linux-4.1.27/arch/mips/netlogic/xlp/
Dahci-init-xlp2.c89 #define SATA_RST_N BIT(0) /* Active low reset sata_core phy */
90 #define SataCtlReserve0 BIT(1)
91 #define M_CSYSREQ BIT(2) /* AXI master low power, not used */
92 #define S_CSYSREQ BIT(3) /* AXI slave low power, not used */
93 #define P0_CP_DET BIT(8) /* Reserved, bring in from pad */
94 #define P0_MP_SW BIT(9) /* Mech Switch */
95 #define P0_DISABLE BIT(10) /* disable p0 */
96 #define P0_ACT_LED_EN BIT(11) /* Active LED enable */
97 #define P0_IRST_HARD_SYNTH BIT(12) /* PHY hard synth reset */
98 #define P0_IRST_HARD_TXRX BIT(13) /* PHY lane hard reset */
[all …]
/linux-4.1.27/include/linux/bcma/
Dbcma_driver_chipcommon.h101 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
102 #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
103 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
104 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
105 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
106 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
503 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
504 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
505 #define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
506 #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
[all …]
/linux-4.1.27/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_layer.h32 #define ATMEL_HLCDC_LAYER_DMA_CHAN BIT(0)
33 #define ATMEL_HLCDC_LAYER_UPDATE BIT(1)
34 #define ATMEL_HLCDC_LAYER_A2Q BIT(2)
35 #define ATMEL_HLCDC_LAYER_RST BIT(8)
41 #define ATMEL_HLCDC_LAYER_DFETCH BIT(0)
42 #define ATMEL_HLCDC_LAYER_LFETCH BIT(1)
43 #define ATMEL_HLCDC_LAYER_DMA_IRQ BIT(2)
44 #define ATMEL_HLCDC_LAYER_DSCR_IRQ BIT(3)
45 #define ATMEL_HLCDC_LAYER_ADD_IRQ BIT(4)
46 #define ATMEL_HLCDC_LAYER_DONE_IRQ BIT(5)
[all …]
/linux-4.1.27/include/linux/power/
Dsmartreflex.h68 #define SRCONFIG_SRENABLE BIT(11)
69 #define SRCONFIG_SENENABLE BIT(10)
70 #define SRCONFIG_ERRGEN_EN BIT(9)
71 #define SRCONFIG_MINMAXAVG_EN BIT(8)
72 #define SRCONFIG_DELAYCTRL BIT(2)
93 #define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31)
94 #define ERRCONFIG_VPBOUNDINTST_V1 BIT(30)
95 #define ERRCONFIG_MCUACCUMINTEN BIT(29)
96 #define ERRCONFIG_MCUACCUMINTST BIT(28)
97 #define ERRCONFIG_MCUVALIDINTEN BIT(27)
[all …]
/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_runtime_pm.c104 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { in __intel_display_power_is_enabled()
265 BIT(POWER_DOMAIN_TRANSCODER_A) | \
266 BIT(POWER_DOMAIN_PIPE_B) | \
267 BIT(POWER_DOMAIN_TRANSCODER_B) | \
268 BIT(POWER_DOMAIN_PIPE_C) | \
269 BIT(POWER_DOMAIN_TRANSCODER_C) | \
270 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
271 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
272 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
273 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
[all …]
/linux-4.1.27/drivers/pwm/
Dpwm-tiehrpwm.c38 #define TBCTL_RUN_MASK (BIT(15) | BIT(14))
40 #define TBCTL_STOP_ON_CYCLE BIT(14)
41 #define TBCTL_FREE_RUN (BIT(15) | BIT(14))
42 #define TBCTL_PRDLD_MASK BIT(3)
44 #define TBCTL_PRDLD_IMDT BIT(3)
45 #define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \
46 BIT(8) | BIT(7))
47 #define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0))
49 #define TBCTL_CTRMODE_DOWN BIT(0)
50 #define TBCTL_CTRMODE_UPDOWN BIT(1)
[all …]
/linux-4.1.27/drivers/net/wireless/p54/
Dlmac.h52 #define P54_HDR_FLAG_CONTROL BIT(15)
53 #define P54_HDR_FLAG_CONTROL_OPSET (BIT(15) + BIT(0))
54 #define P54_HDR_FLAG_DATA_ALIGN BIT(14)
56 #define P54_HDR_FLAG_DATA_OUT_PROMISC BIT(0)
57 #define P54_HDR_FLAG_DATA_OUT_TIMESTAMP BIT(1)
58 #define P54_HDR_FLAG_DATA_OUT_SEQNR BIT(2)
59 #define P54_HDR_FLAG_DATA_OUT_BIT3 BIT(3)
60 #define P54_HDR_FLAG_DATA_OUT_BURST BIT(4)
61 #define P54_HDR_FLAG_DATA_OUT_NOCANCEL BIT(5)
62 #define P54_HDR_FLAG_DATA_OUT_CLEARTIM BIT(6)
[all …]
/linux-4.1.27/drivers/net/wireless/hostap/
Dhostap_wlan.h365 #define HFA384X_PCI_CTL_FROM_BAP (BIT(5) | BIT(1) | BIT(0))
366 #define HFA384X_PCI_CTL_TO_BAP (BIT(5) | BIT(0))
379 #define HFA384X_CMDCODE_ACCESS_WRITE (0x21 | BIT(8))
392 #define HFA384X_TEST_CFG_BIT_ALC BIT(3)
394 #define HFA384X_CMD_BUSY BIT(15)
396 #define HFA384X_CMD_TX_RECLAIM BIT(8)
398 #define HFA384X_OFFSET_ERR BIT(14)
399 #define HFA384X_OFFSET_BUSY BIT(15)
413 #define HFA384X_AUX_PORT_DISABLE BIT(14)
414 #define HFA384X_AUX_PORT_ENABLE BIT(15)
[all …]
/linux-4.1.27/drivers/media/i2c/
Dadv7180.c174 #define ADV7180_FLAG_RESET_POWERED BIT(0)
175 #define ADV7180_FLAG_V2 BIT(1)
176 #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
177 #define ADV7180_FLAG_I2P BIT(3)
359 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) { in adv7180_s_routing()
947 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
948 BIT(ADV7180_INPUT_CVBS_AIN2) |
949 BIT(ADV7180_INPUT_CVBS_AIN3) |
950 BIT(ADV7180_INPUT_CVBS_AIN4) |
951 BIT(ADV7180_INPUT_CVBS_AIN5) |
[all …]
/linux-4.1.27/arch/c6x/include/asm/
Dclock.h58 #define PLLPREDIV_EN BIT(15)
62 #define PLLCTL_PLLEN BIT(0)
63 #define PLLCTL_PLLPWRDN BIT(1)
64 #define PLLCTL_PLLRST BIT(3)
65 #define PLLCTL_PLLDIS BIT(4)
66 #define PLLCTL_PLLENSRC BIT(5)
67 #define PLLCTL_CLKMODE BIT(8)
70 #define PLLCMD_GOSTAT BIT(0)
73 #define PLLSTAT_GOSTAT BIT(0)
76 #define PLLDIV_EN BIT(15)
[all …]
/linux-4.1.27/sound/firewire/oxfw/
Doxfw-command.c35 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_stream_set_format()
36 BIT(6) | BIT(7) | BIT(8)); in avc_stream_set_format()
78 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_stream_get_format()
79 BIT(6) | BIT(7)); in avc_stream_get_format()
141 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5)); in avc_general_inquiry_sig_fmt()
/linux-4.1.27/drivers/net/wireless/cw1200/
Dhwio.h125 #define ST90TDS_CONT_WUP_BIT (BIT(12))
126 #define ST90TDS_CONT_RDY_BIT (BIT(13))
127 #define ST90TDS_CONT_IRQ_ENABLE (BIT(14))
128 #define ST90TDS_CONT_RDY_ENABLE (BIT(15))
129 #define ST90TDS_CONT_IRQ_RDY_ENABLE (BIT(14)|BIT(15))
132 #define ST90TDS_CONFIG_FRAME_BIT (BIT(2))
133 #define ST90TDS_CONFIG_WORD_MODE_BITS (BIT(3)|BIT(4))
134 #define ST90TDS_CONFIG_WORD_MODE_1 (BIT(3))
135 #define ST90TDS_CONFIG_WORD_MODE_2 (BIT(4))
136 #define ST90TDS_CONFIG_ERROR_0_BIT (BIT(5))
[all …]
Dwsm.h112 #define WSM_SCAN_FLAG_FORCE_BACKGROUND (BIT(0))
116 #define WSM_SCAN_FLAG_SPLIT_METHOD (BIT(1))
119 #define WSM_SCAN_FLAG_SHORT_PREAMBLE (BIT(2))
122 #define WSM_SCAN_FLAG_11N_GREENFIELD (BIT(3))
136 #define WSM_PSM_PS BIT(0)
139 #define WSM_PSM_FAST_PS_FLAG BIT(7)
142 #define WSM_PSM_FAST_PS (BIT(0) | BIT(7))
148 #define WSM_PSM_UNKNOWN BIT(1)
174 #define WSM_HT_TX_STBC (BIT(7))
195 #define WSM_TX_STATUS_AGGREGATION (BIT(0))
[all …]
/linux-4.1.27/drivers/net/wireless/ti/wl18xx/
Devent.h28 SCAN_COMPLETE_EVENT_ID = BIT(8),
29 RADAR_DETECTED_EVENT_ID = BIT(9),
30 CHANNEL_SWITCH_COMPLETE_EVENT_ID = BIT(10),
31 BSS_LOSS_EVENT_ID = BIT(11),
32 MAX_TX_FAILURE_EVENT_ID = BIT(12),
33 DUMMY_PACKET_EVENT_ID = BIT(13),
34 INACTIVE_STA_EVENT_ID = BIT(14),
35 PEER_REMOVE_COMPLETE_EVENT_ID = BIT(15),
36 PERIODIC_SCAN_COMPLETE_EVENT_ID = BIT(16),
37 BA_SESSION_RX_CONSTRAINT_EVENT_ID = BIT(17),
[all …]
/linux-4.1.27/include/linux/usb/
Dquirks.h11 #define USB_QUIRK_STRING_FETCH_255 BIT(0)
14 #define USB_QUIRK_RESET_RESUME BIT(1)
17 #define USB_QUIRK_NO_SET_INTF BIT(2)
20 #define USB_QUIRK_CONFIG_INTF_STRINGS BIT(3)
23 #define USB_QUIRK_RESET BIT(4)
27 #define USB_QUIRK_HONOR_BNUMINTERFACES BIT(5)
31 #define USB_QUIRK_DELAY_INIT BIT(6)
42 #define USB_QUIRK_LINEAR_UFRAME_INTR_BINTERVAL BIT(7)
45 #define USB_QUIRK_DEVICE_QUALIFIER BIT(8)
48 #define USB_QUIRK_IGNORE_REMOTE_WAKEUP BIT(9)
[all …]
/linux-4.1.27/arch/arm/mach-rockchip/
Dpm.c100 mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) | in rk3288_slp_mode_set()
101 BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) | in rk3288_slp_mode_set()
102 BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) | in rk3288_slp_mode_set()
103 BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) | in rk3288_slp_mode_set()
104 BIT(PMU_SCU_EN); in rk3288_slp_mode_set()
106 mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP); in rk3288_slp_mode_set()
110 mode_set |= BIT(PMU_BUS_PD_EN) | in rk3288_slp_mode_set()
111 BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) | in rk3288_slp_mode_set()
112 BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) | in rk3288_slp_mode_set()
113 BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN); in rk3288_slp_mode_set()
[all …]
/linux-4.1.27/drivers/net/dsa/
Dmv88e6xxx.h15 #define SMI_CMD_BUSY BIT(15)
16 #define SMI_CMD_CLAUSE_22 BIT(12)
27 #define PORT_STATUS_PAUSE_EN BIT(15)
28 #define PORT_STATUS_MY_PAUSE BIT(14)
29 #define PORT_STATUS_HD_FLOW BIT(13)
30 #define PORT_STATUS_PHY_DETECT BIT(12)
31 #define PORT_STATUS_LINK BIT(11)
32 #define PORT_STATUS_DUPLEX BIT(10)
37 #define PORT_STATUS_EEE BIT(6) /* 6352 */
38 #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */
[all …]
/linux-4.1.27/drivers/iio/pressure/
Dbmp280.c40 #define BMP280_FILTER_MASK (BIT(4) | BIT(3) | BIT(2))
42 #define BMP280_FILTER_2X BIT(2)
43 #define BMP280_FILTER_4X BIT(3)
44 #define BMP280_FILTER_8X (BIT(3) | BIT(2))
45 #define BMP280_FILTER_16X BIT(4)
47 #define BMP280_OSRS_TEMP_MASK (BIT(7) | BIT(6) | BIT(5))
49 #define BMP280_OSRS_TEMP_1X BIT(5)
50 #define BMP280_OSRS_TEMP_2X BIT(6)
51 #define BMP280_OSRS_TEMP_4X (BIT(6) | BIT(5))
52 #define BMP280_OSRS_TEMP_8X BIT(7)
[all …]
/linux-4.1.27/drivers/hwtracing/coresight/
Dcoresight-etm.h89 #define ETMCR_PWD_DWN BIT(0)
90 #define ETMCR_STALL_MODE BIT(7)
91 #define ETMCR_ETM_PRG BIT(10)
92 #define ETMCR_ETM_EN BIT(11)
93 #define ETMCR_CYC_ACC BIT(12)
94 #define ETMCR_CTXID_SIZE (BIT(14)|BIT(15))
95 #define ETMCR_TIMESTAMP_EN BIT(28)
97 #define ETMCCR_FIFOFULL BIT(23)
99 #define ETMPDCR_PWD_UP BIT(3)
101 #define ETMTECR1_ADDR_COMP_1 BIT(0)
[all …]
/linux-4.1.27/drivers/infiniband/hw/ocrdma/
Docrdma_sli.h242 OCRDMA_MQE_HDR_EMB_MASK = BIT(0),
308 OCRDMA_CREATE_EQ_VALID = BIT(29),
349 OCRDMA_MCQE_CONS_MASK = BIT(27),
351 OCRDMA_MCQE_CMPL_MASK = BIT(28),
353 OCRDMA_MCQE_AE_MASK = BIT(30),
355 OCRDMA_MCQE_VALID_MASK = BIT(31)
366 OCRDMA_AE_MCQE_QPVALID = BIT(31),
369 OCRDMA_AE_MCQE_CQVALID = BIT(31),
371 OCRDMA_AE_MCQE_VALID = BIT(31),
372 OCRDMA_AE_MCQE_AE = BIT(30),
[all …]
/linux-4.1.27/arch/arm/mach-davinci/
Dclock.h21 #define PLLCTL_PLLEN BIT(0)
22 #define PLLCTL_PLLPWRDN BIT(1)
23 #define PLLCTL_PLLRST BIT(3)
24 #define PLLCTL_PLLDIS BIT(4)
25 #define PLLCTL_PLLENSRC BIT(5)
26 #define PLLCTL_CLKMODE BIT(8)
50 #define PLLDIV_EN BIT(15)
73 #define PLLSTAT_GOSTAT BIT(0)
74 #define PLLCMD_GOSET BIT(0)
112 #define ALWAYS_ENABLED BIT(1)
[all …]
/linux-4.1.27/arch/arm/mach-shmobile/
Dsetup-r8a7779.c492 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */
493 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */
495 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */
496 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */
498 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */
499 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */
501 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */
502 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */
504 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */
505 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */
[all …]
/linux-4.1.27/drivers/net/ethernet/apm/xgene/
Dxgene_enet_hw.h52 #define OVERWRITE BIT(31)
53 #define IS_BUFFER_POOL BIT(20)
54 #define PREFETCH_BUF_EN BIT(21)
96 #define ACCEPTLERR BIT(19)
97 #define QCOHERENT BIT(4)
98 #define RECOMBBUF BIT(27)
125 #define BUSY_MASK BIT(0)
126 #define READ_CYCLE_MASK BIT(0)
138 #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)
139 #define RESUME_TX BIT(0)
[all …]
/linux-4.1.27/drivers/net/wireless/mwifiex/
Dwmm.h24 MWIFIEX_AIFSN = (BIT(0) | BIT(1) | BIT(2) | BIT(3)),
25 MWIFIEX_ACM = BIT(4),
26 MWIFIEX_ACI = (BIT(5) | BIT(6)),
30 MWIFIEX_ECW_MIN = (BIT(0) | BIT(1) | BIT(2) | BIT(3)),
31 MWIFIEX_ECW_MAX = (BIT(4) | BIT(5) | BIT(6) | BIT(7)),
/linux-4.1.27/drivers/gpu/drm/gma500/
Dmdfld_dsi_pkg_sender.c98 return wait_for_gen_fifo_empty(sender, (BIT(2) | BIT(10) | BIT(18) | in wait_for_all_fifos_empty()
99 BIT(26) | BIT(27) | BIT(28))); in wait_for_all_fifos_empty()
104 return wait_for_gen_fifo_empty(sender, (BIT(10) | BIT(26))); in wait_for_lp_fifos_empty()
109 return wait_for_gen_fifo_empty(sender, (BIT(2) | BIT(18))); in wait_for_hs_fifos_empty()
120 case BIT(0): in handle_dsi_error()
121 case BIT(1): in handle_dsi_error()
122 case BIT(2): in handle_dsi_error()
123 case BIT(3): in handle_dsi_error()
124 case BIT(4): in handle_dsi_error()
125 case BIT(5): in handle_dsi_error()
[all …]
/linux-4.1.27/include/linux/platform_data/
Ddma-rcar-hpbdma.h57 #define HPB_DMAE_ASYNCRSTR_ASRST41 BIT(10)
58 #define HPB_DMAE_ASYNCRSTR_ASRST40 BIT(9)
59 #define HPB_DMAE_ASYNCRSTR_ASRST39 BIT(8)
60 #define HPB_DMAE_ASYNCRSTR_ASRST27 BIT(7)
61 #define HPB_DMAE_ASYNCRSTR_ASRST26 BIT(6)
62 #define HPB_DMAE_ASYNCRSTR_ASRST25 BIT(5)
63 #define HPB_DMAE_ASYNCRSTR_ASRST24 BIT(4)
64 #define HPB_DMAE_ASYNCRSTR_ASRST23 BIT(3)
65 #define HPB_DMAE_ASYNCRSTR_ASRST22 BIT(2)
66 #define HPB_DMAE_ASYNCRSTR_ASRST21 BIT(1)
[all …]
/linux-4.1.27/drivers/crypto/qce/
Dcommon.h39 #define QCE_ALG_DES BIT(0)
40 #define QCE_ALG_3DES BIT(1)
41 #define QCE_ALG_AES BIT(2)
44 #define QCE_HASH_SHA1 BIT(3)
45 #define QCE_HASH_SHA256 BIT(4)
46 #define QCE_HASH_SHA1_HMAC BIT(5)
47 #define QCE_HASH_SHA256_HMAC BIT(6)
48 #define QCE_HASH_AES_CMAC BIT(7)
51 #define QCE_MODE_CBC BIT(8)
52 #define QCE_MODE_ECB BIT(9)
[all …]
/linux-4.1.27/drivers/input/serio/
Dsun4i-ps2.c30 #define PS2_GCTL_INTFLAG BIT(4)
31 #define PS2_GCTL_INTEN BIT(3)
32 #define PS2_GCTL_RESET BIT(2)
33 #define PS2_GCTL_MASTER BIT(1)
34 #define PS2_GCTL_BUSEN BIT(0)
37 #define PS2_LCTL_NOACK BIT(18)
38 #define PS2_LCTL_TXDTOEN BIT(8)
39 #define PS2_LCTL_STOPERREN BIT(3)
40 #define PS2_LCTL_ACKERREN BIT(2)
41 #define PS2_LCTL_PARERREN BIT(1)
[all …]
/linux-4.1.27/drivers/usb/musb/
Ddavinci.h19 #define USBPHY_DATAPOL BIT(11) /* (dm355) switch D+/D- */
20 #define USBPHY_PHYCLKGD BIT(8)
21 #define USBPHY_SESNDEN BIT(7) /* v(sess_end) comparator */
22 #define USBPHY_VBDTCTEN BIT(6) /* v(bus) comparator */
23 #define USBPHY_VBUSSENS BIT(5) /* (dm355,ro) is vbus > 0.5V */
24 #define USBPHY_PHYPLLON BIT(4) /* override pll suspend */
25 #define USBPHY_CLKO1SEL BIT(3)
26 #define USBPHY_OSCPDWN BIT(2)
27 #define USBPHY_OTGPDWN BIT(1)
28 #define USBPHY_PHYPDWN BIT(0)
[all …]
/linux-4.1.27/arch/arm/mach-exynos/
Dregs-pmu.h36 #define S5P_USE_DELAYED_RESET_ASSERTION BIT(12)
160 #define EXYNOS5_USE_RETENTION BIT(4)
162 #define EXYNOS5_L2RSTDISABLE_VALUE BIT(3)
356 #define EXYNOS5_USE_RETENTION BIT(4)
498 #define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3)
502 #define EXYNOS5420_UFS BIT(8)
503 #define EXYNOS5420_ATB_KFC BIT(13)
504 #define EXYNOS5420_ATB_ISP_ARM BIT(19)
505 #define EXYNOS5420_EMULATION BIT(31)
506 #define ATB_ISP_ARM BIT(12)
[all …]
/linux-4.1.27/drivers/pinctrl/
Dpinctrl-amd.c57 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_direction_input()
59 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_direction_input()
62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_input()
78 pin_reg |= BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_output()
80 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
99 return !!(pin_reg & BIT(PIN_STS_OFF)); in amd_gpio_get_value()
111 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
[all …]
/linux-4.1.27/include/net/
Dmac80211.h130 IEEE80211_MAX_QUEUE_MAP = BIT(IEEE80211_MAX_QUEUES) - 1,
190 IEEE80211_CHANCTX_CHANGE_WIDTH = BIT(0),
191 IEEE80211_CHANCTX_CHANGE_RX_CHAINS = BIT(1),
192 IEEE80211_CHANCTX_CHANGE_RADAR = BIT(2),
193 IEEE80211_CHANCTX_CHANGE_CHANNEL = BIT(3),
194 IEEE80211_CHANCTX_CHANGE_MIN_WIDTH = BIT(4),
631 IEEE80211_TX_CTL_REQ_TX_STATUS = BIT(0),
632 IEEE80211_TX_CTL_ASSIGN_SEQ = BIT(1),
633 IEEE80211_TX_CTL_NO_ACK = BIT(2),
634 IEEE80211_TX_CTL_CLEAR_PS_FILT = BIT(3),
[all …]
/linux-4.1.27/drivers/media/usb/gspca/stv06xx/
Dstv06xx_vv6410.h238 {VV6410_SETUP1, BIT(6)},
240 {VV6410_FGMODES, BIT(6) | BIT(4) | BIT(2) | BIT(0)},
243 {VV6410_DATAFORMAT, BIT(7) | BIT(0)},
249 {VV6410_AS0, BIT(6) | BIT(4) | BIT(3) | BIT(2) | BIT(1)},
252 {VV6410_AT1, BIT(4) | BIT(0)},
Dstv06xx_hdcs.h195 {HDCS_STATUS, BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)},
198 {HDCS_PCTRL, BIT(6) | BIT(5) | BIT(1) | BIT(0)},
200 {HDCS_ICTRL, BIT(5)},
201 {HDCS_ITMG, BIT(4) | BIT(1)},
/linux-4.1.27/drivers/net/wireless/ath/wil6210/
Dwil6210.h130 #define BIT_BL_READY BIT(0)
144 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */
146 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */
151 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */
152 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */
158 #define BIT_HPAL_PERST_FROM_PAD BIT(6)
159 #define BIT_CAR_PERST_RST BIT(7)
161 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18)
165 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2)
168 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0)
[all …]
/linux-4.1.27/drivers/regulator/
Dpbias-regulator.c63 .enable = BIT(1),
64 .enable_mask = BIT(1),
65 .vmode = BIT(0),
72 .enable = BIT(9),
73 .enable_mask = BIT(9),
74 .vmode = BIT(8),
80 .enable = BIT(26) | BIT(22),
81 .enable_mask = BIT(26) | BIT(25) | BIT(22),
82 .disable_val = BIT(25),
83 .vmode = BIT(21),
[all …]
Dtps6524x-regulator.c49 #define DCDCDCDC1_PG_MSK BIT(1)
51 #define DCDCDCDC2_PG_MSK BIT(3)
53 #define DCDCDCDC3_PG_MSK BIT(5)
62 #define USB_IWARN_SD BIT(6)
63 #define USB_FAST_LOOP BIT(7)
66 #define ALARM_LDO1 BIT(0)
67 #define ALARM_DCDC1 BIT(1)
68 #define ALARM_DCDC2 BIT(2)
69 #define ALARM_DCDC3 BIT(3)
70 #define ALARM_LDO2 BIT(4)
[all …]
/linux-4.1.27/arch/mips/lantiq/xway/
Dsysctrl.c45 #define PMU_USB0_P BIT(0)
46 #define PMU_PCI BIT(4)
47 #define PMU_DMA BIT(5)
48 #define PMU_USB0 BIT(6)
49 #define PMU_ASC0 BIT(7)
50 #define PMU_EPHY BIT(7) /* ase */
51 #define PMU_SPI BIT(8)
52 #define PMU_DFE BIT(9)
53 #define PMU_EBU BIT(10)
54 #define PMU_STP BIT(11)
[all …]
/linux-4.1.27/include/linux/phy/
Domap_control_phy.h51 #define OMAP_CTRL_DEV_PHY_PD BIT(0)
53 #define OMAP_CTRL_DEV_AVALID BIT(0)
54 #define OMAP_CTRL_DEV_BVALID BIT(1)
55 #define OMAP_CTRL_DEV_VBUSVALID BIT(2)
56 #define OMAP_CTRL_DEV_SESSEND BIT(3)
57 #define OMAP_CTRL_DEV_IDDIG BIT(4)
71 #define OMAP_CTRL_USB2_PHY_PD BIT(28)
73 #define AM437X_CTRL_USB2_PHY_PD BIT(0)
74 #define AM437X_CTRL_USB2_OTG_PD BIT(1)
75 #define AM437X_CTRL_USB2_OTGVDET_EN BIT(19)
[all …]
/linux-4.1.27/drivers/iio/magnetometer/
Dhid-sensor-magn-3d.c77 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
78 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |
79 BIT(IIO_CHAN_INFO_SCALE) |
80 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
81 BIT(IIO_CHAN_INFO_HYSTERESIS),
86 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
87 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |
88 BIT(IIO_CHAN_INFO_SCALE) |
89 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
90 BIT(IIO_CHAN_INFO_HYSTERESIS),
[all …]
/linux-4.1.27/drivers/scsi/fnic/
Dfnic.h58 #define FNIC_TAG_ABORT BIT(30) /* tag bit indicating abort */
59 #define FNIC_TAG_DEV_RST BIT(29) /* indicates device reset */
60 #define FNIC_TAG_MASK (BIT(24) - 1) /* mask for lookup */
68 #define FNIC_IO_INITIALIZED BIT(0)
69 #define FNIC_IO_ISSUED BIT(1)
70 #define FNIC_IO_DONE BIT(2)
71 #define FNIC_IO_REQ_NULL BIT(3)
72 #define FNIC_IO_ABTS_PENDING BIT(4)
73 #define FNIC_IO_ABORTED BIT(5)
74 #define FNIC_IO_ABTS_ISSUED BIT(6)
[all …]
/linux-4.1.27/drivers/power/
Dbq24190_charger.c27 #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7)
29 #define BQ24190_REG_ISC_VINDPM_MASK (BIT(6) | BIT(5) | BIT(4) | \
30 BIT(3))
32 #define BQ24190_REG_ISC_IINLIM_MASK (BIT(2) | BIT(1) | BIT(0))
36 #define BQ24190_REG_POC_RESET_MASK BIT(7)
38 #define BQ24190_REG_POC_WDT_RESET_MASK BIT(6)
40 #define BQ24190_REG_POC_CHG_CONFIG_MASK (BIT(5) | BIT(4))
42 #define BQ24190_REG_POC_SYS_MIN_MASK (BIT(3) | BIT(2) | BIT(1))
44 #define BQ24190_REG_POC_BOOST_LIM_MASK BIT(0)
48 #define BQ24190_REG_CCC_ICHG_MASK (BIT(7) | BIT(6) | BIT(5) | \
[all …]
/linux-4.1.27/drivers/devfreq/event/
Dexynos-ppmu.h76 #define PPMU_PMNC_START_MODE_MASK BIT(16)
77 #define PPMU_PMNC_CC_DIVIDER_MASK BIT(3)
78 #define PPMU_PMNC_CC_RESET_MASK BIT(2)
79 #define PPMU_PMNC_COUNTER_RESET_MASK BIT(1)
80 #define PPMU_PMNC_ENABLE_MASK BIT(0)
83 #define PPMU_CCNT_MASK BIT(31)
84 #define PPMU_PMCNT3_MASK BIT(3)
85 #define PPMU_PMCNT2_MASK BIT(2)
86 #define PPMU_PMCNT1_MASK BIT(1)
87 #define PPMU_PMCNT0_MASK BIT(0)
/linux-4.1.27/drivers/i2c/busses/
Di2c-st.c54 #define SSC_CTL_HB BIT(4)
55 #define SSC_CTL_PH BIT(5)
56 #define SSC_CTL_PO BIT(6)
57 #define SSC_CTL_SR BIT(7)
58 #define SSC_CTL_MS BIT(8)
59 #define SSC_CTL_EN BIT(9)
60 #define SSC_CTL_LPB BIT(10)
61 #define SSC_CTL_EN_TX_FIFO BIT(11)
62 #define SSC_CTL_EN_RX_FIFO BIT(12)
63 #define SSC_CTL_EN_CLST_RX BIT(13)
[all …]
/linux-4.1.27/drivers/extcon/
Dextcon-rt8973a.h187 #define RT8973A_INT1_ATTACH_MASK BIT(0)
188 #define RT8973A_INT1_DETACH_MASK BIT(1)
189 #define RT8973A_INT1_CHGDET_MASK BIT(2)
190 #define RT8973A_INT1_DCD_T_MASK BIT(3)
191 #define RT8973A_INT1_OVP_MASK BIT(4)
192 #define RT8973A_INT1_CONNECT_MASK BIT(5)
193 #define RT8973A_INT1_ADC_CHG_MASK BIT(6)
194 #define RT8973A_INT1_OTP_MASK BIT(7)
195 #define RT8973A_INT2_UVLOT_MASK BIT(0)
196 #define RT8973A_INT2_POR_MASK BIT(1)
[all …]
/linux-4.1.27/drivers/usb/phy/
Dphy-mxs-usb.c41 #define BM_USBPHY_CTRL_SFTRST BIT(31)
42 #define BM_USBPHY_CTRL_CLKGATE BIT(30)
43 #define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27)
44 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26)
45 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25)
46 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23)
47 #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22)
48 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21)
49 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20)
50 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19)
[all …]
/linux-4.1.27/arch/mips/include/asm/mach-jz4740/
Dtimer.h37 #define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
38 #define JZ_TIMER_IRQ_FULL(x) BIT(x)
40 #define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
41 #define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
42 #define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
54 #define JZ_TIMER_CTRL_SRC_EXT BIT(2)
55 #define JZ_TIMER_CTRL_SRC_RTC BIT(1)
56 #define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
66 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_stop()
71 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); in jz4740_timer_start()
[all …]
/linux-4.1.27/net/batman-adv/
Dpacket.h78 BATADV_NOT_BEST_NEXT_HOP = BIT(0),
79 BATADV_PRIMARIES_FIRST_HOP = BIT(1),
80 BATADV_DIRECTLINK = BIT(2),
100 BATADV_MCAST_WANT_ALL_UNSNOOPABLES = BIT(0),
101 BATADV_MCAST_WANT_ALL_IPV4 = BIT(1),
102 BATADV_MCAST_WANT_ALL_IPV6 = BIT(2),
116 BATADV_TT_OGM_DIFF = BIT(0),
117 BATADV_TT_REQUEST = BIT(1),
118 BATADV_TT_RESPONSE = BIT(2),
119 BATADV_TT_FULL_TABLE = BIT(4),
[all …]
/linux-4.1.27/drivers/dma/
Dqcom_bam_dma.c61 #define DESC_FLAG_INT BIT(15)
62 #define DESC_FLAG_EOT BIT(14)
63 #define DESC_FLAG_EOB BIT(13)
64 #define DESC_FLAG_NWD BIT(12)
204 #define BAM_SW_RST BIT(0)
205 #define BAM_EN BIT(1)
206 #define BAM_EN_ACCUM BIT(4)
211 #define BAM_CACHED_DESC_STORE BIT(15)
212 #define IBC_DISABLE BIT(16)
219 #define CE_BUFFER_SIZE BIT(13)
[all …]

12345678910