Lines Matching refs:BIT

109 #define RX_ENABLE_MASK		BIT(0)
110 #define RX_FIFO_ENABLE_MASK	BIT(1)
111 #define RX_FSYNC_MASK		BIT(2)
112 #define DIRECT_COMPANDING_MASK	BIT(3)
113 #define RX_SYNC_SEL_MASK	BIT(4)
114 #define RX_CLK_POL_MASK		BIT(5)
115 #define RX_CLK_SEL_MASK		BIT(6)
116 #define LOOPBACK_MASK		BIT(7)
117 #define TX_ENABLE_MASK		BIT(8)
118 #define TX_FIFO_ENABLE_MASK	BIT(9)
119 #define TX_FSYNC_MASK		BIT(10)
120 #define TX_MSP_TDR_TSR		BIT(11)
121 #define TX_SYNC_SEL_MASK	(BIT(12) | BIT(11))
122 #define TX_CLK_POL_MASK		BIT(13)
123 #define TX_CLK_SEL_MASK		BIT(14)
124 #define TX_EXTRA_DELAY_MASK	BIT(15)
125 #define SRG_ENABLE_MASK		BIT(16)
126 #define SRG_CLK_POL_MASK	BIT(17)
127 #define SRG_CLK_SEL_MASK	(BIT(19) | BIT(18))
128 #define FRAME_GEN_EN_MASK	BIT(20)
129 #define SPI_CLK_MODE_MASK	(BIT(22) | BIT(21))
130 #define SPI_BURST_MODE_MASK	BIT(23)
154 #define RCKPOL_MASK		BIT(0)
155 #define TCKPOL_MASK		BIT(0)
156 #define SPICKM_MASK		(BIT(1) | BIT(0))
202 #define RX_BUSY			BIT(0)
203 #define RX_FIFO_EMPTY		BIT(1)
204 #define RX_FIFO_FULL		BIT(2)
205 #define TX_BUSY			BIT(3)
206 #define TX_FIFO_EMPTY		BIT(4)
207 #define TX_FIFO_FULL		BIT(5)
233 #define RX_DMA_ENABLE		BIT(0)
234 #define TX_DMA_ENABLE		BIT(1)
240 #define RX_SERVICE_INT		BIT(0)
241 #define RX_OVERRUN_ERROR_INT	BIT(1)
242 #define RX_FSYNC_ERR_INT	BIT(2)
243 #define RX_FSYNC_INT		BIT(3)
244 #define TX_SERVICE_INT		BIT(4)
245 #define TX_UNDERRUN_ERR_INT	BIT(5)
246 #define TX_FSYNC_ERR_INT	BIT(6)
247 #define TX_FSYNC_INT		BIT(7)
251 #define MSP_ITCR_ITEN		BIT(0)
252 #define MSP_ITCR_TESTFIFO	BIT(1)