Lines Matching refs:BIT
21 #define PLLCTL_PLLEN BIT(0)
22 #define PLLCTL_PLLPWRDN BIT(1)
23 #define PLLCTL_PLLRST BIT(3)
24 #define PLLCTL_PLLDIS BIT(4)
25 #define PLLCTL_PLLENSRC BIT(5)
26 #define PLLCTL_CLKMODE BIT(8)
50 #define PLLDIV_EN BIT(15)
73 #define PLLSTAT_GOSTAT BIT(0)
74 #define PLLCMD_GOSET BIT(0)
112 #define ALWAYS_ENABLED BIT(1)
113 #define CLK_PSC BIT(2)
114 #define CLK_PLL BIT(3) /* PLL-derived clock */
115 #define PRE_PLL BIT(4) /* source is before PLL mult/div */
116 #define PSC_SWRSTDISABLE BIT(5) /* Disable state is SwRstDisable */
117 #define PSC_FORCE BIT(6) /* Force module state transtition */
118 #define PSC_LRST BIT(8) /* Use local reset on enable/disable */