1/* 2 * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support 3 * Copyright (c) 2008 Marvell Semiconductor 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 */ 10 11#ifndef __MV88E6XXX_H 12#define __MV88E6XXX_H 13 14#define SMI_CMD 0x00 15#define SMI_CMD_BUSY BIT(15) 16#define SMI_CMD_CLAUSE_22 BIT(12) 17#define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 18#define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 19#define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) 20#define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) 21#define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) 22#define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) 23#define SMI_DATA 0x01 24 25#define REG_PORT(p) (0x10 + (p)) 26#define PORT_STATUS 0x00 27#define PORT_STATUS_PAUSE_EN BIT(15) 28#define PORT_STATUS_MY_PAUSE BIT(14) 29#define PORT_STATUS_HD_FLOW BIT(13) 30#define PORT_STATUS_PHY_DETECT BIT(12) 31#define PORT_STATUS_LINK BIT(11) 32#define PORT_STATUS_DUPLEX BIT(10) 33#define PORT_STATUS_SPEED_MASK 0x0300 34#define PORT_STATUS_SPEED_10 0x0000 35#define PORT_STATUS_SPEED_100 0x0100 36#define PORT_STATUS_SPEED_1000 0x0200 37#define PORT_STATUS_EEE BIT(6) /* 6352 */ 38#define PORT_STATUS_AM_DIS BIT(6) /* 6165 */ 39#define PORT_STATUS_MGMII BIT(6) /* 6185 */ 40#define PORT_STATUS_TX_PAUSED BIT(5) 41#define PORT_STATUS_FLOW_CTRL BIT(4) 42#define PORT_PCS_CTRL 0x01 43#define PORT_SWITCH_ID 0x03 44#define PORT_SWITCH_ID_6085 0x04a0 45#define PORT_SWITCH_ID_6095 0x0950 46#define PORT_SWITCH_ID_6123 0x1210 47#define PORT_SWITCH_ID_6123_A1 0x1212 48#define PORT_SWITCH_ID_6123_A2 0x1213 49#define PORT_SWITCH_ID_6131 0x1060 50#define PORT_SWITCH_ID_6131_B2 0x1066 51#define PORT_SWITCH_ID_6152 0x1a40 52#define PORT_SWITCH_ID_6155 0x1a50 53#define PORT_SWITCH_ID_6161 0x1610 54#define PORT_SWITCH_ID_6161_A1 0x1612 55#define PORT_SWITCH_ID_6161_A2 0x1613 56#define PORT_SWITCH_ID_6165 0x1650 57#define PORT_SWITCH_ID_6165_A1 0x1652 58#define PORT_SWITCH_ID_6165_A2 0x1653 59#define PORT_SWITCH_ID_6171 0x1710 60#define PORT_SWITCH_ID_6172 0x1720 61#define PORT_SWITCH_ID_6176 0x1760 62#define PORT_SWITCH_ID_6182 0x1a60 63#define PORT_SWITCH_ID_6185 0x1a70 64#define PORT_SWITCH_ID_6352 0x3520 65#define PORT_SWITCH_ID_6352_A0 0x3521 66#define PORT_SWITCH_ID_6352_A1 0x3522 67#define PORT_CONTROL 0x04 68#define PORT_CONTROL_STATE_MASK 0x03 69#define PORT_CONTROL_STATE_DISABLED 0x00 70#define PORT_CONTROL_STATE_BLOCKING 0x01 71#define PORT_CONTROL_STATE_LEARNING 0x02 72#define PORT_CONTROL_STATE_FORWARDING 0x03 73#define PORT_CONTROL_1 0x05 74#define PORT_BASE_VLAN 0x06 75#define PORT_DEFAULT_VLAN 0x07 76#define PORT_CONTROL_2 0x08 77#define PORT_RATE_CONTROL 0x09 78#define PORT_RATE_CONTROL_2 0x0a 79#define PORT_ASSOC_VECTOR 0x0b 80#define PORT_IN_DISCARD_LO 0x10 81#define PORT_IN_DISCARD_HI 0x11 82#define PORT_IN_FILTERED 0x12 83#define PORT_OUT_FILTERED 0x13 84#define PORT_TAG_REGMAP_0123 0x19 85#define PORT_TAG_REGMAP_4567 0x1a 86 87#define REG_GLOBAL 0x1b 88#define GLOBAL_STATUS 0x00 89#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */ 90/* Two bits for 6165, 6185 etc */ 91#define GLOBAL_STATUS_PPU_MASK (0x3 << 14) 92#define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14) 93#define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14) 94#define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14) 95#define GLOBAL_STATUS_PPU_POLLING (0x3 << 14) 96#define GLOBAL_MAC_01 0x01 97#define GLOBAL_MAC_23 0x02 98#define GLOBAL_MAC_45 0x03 99#define GLOBAL_CONTROL 0x04 100#define GLOBAL_CONTROL_SW_RESET BIT(15) 101#define GLOBAL_CONTROL_PPU_ENABLE BIT(14) 102#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */ 103#define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */ 104#define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */ 105#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */ 106#define GLOBAL_CONTROL_DEVICE_EN BIT(7) 107#define GLOBAL_CONTROL_STATS_DONE_EN BIT(6) 108#define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5) 109#define GLOBAL_CONTROL_VTU_DONE_EN BIT(4) 110#define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3) 111#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) 112#define GLOBAL_CONTROL_TCAM_EN BIT(1) 113#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) 114#define GLOBAL_VTU_OP 0x05 115#define GLOBAL_VTU_VID 0x06 116#define GLOBAL_VTU_DATA_0_3 0x07 117#define GLOBAL_VTU_DATA_4_7 0x08 118#define GLOBAL_VTU_DATA_8_11 0x09 119#define GLOBAL_ATU_CONTROL 0x0a 120#define GLOBAL_ATU_OP 0x0b 121#define GLOBAL_ATU_OP_BUSY BIT(15) 122#define GLOBAL_ATU_OP_NOP (0 << 12) 123#define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) 124#define GLOBAL_ATU_OP_FLUSH_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY) 125#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) 126#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) 127#define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) 128#define GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) 129#define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY) 130#define GLOBAL_ATU_DATA 0x0c 131#define GLOBAL_ATU_DATA_STATE_MASK 0x0f 132#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 133#define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d 134#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e 135#define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f 136#define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05 137#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 138#define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e 139#define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f 140#define GLOBAL_ATU_MAC_01 0x0d 141#define GLOBAL_ATU_MAC_23 0x0e 142#define GLOBAL_ATU_MAC_45 0x0f 143#define GLOBAL_IP_PRI_0 0x10 144#define GLOBAL_IP_PRI_1 0x11 145#define GLOBAL_IP_PRI_2 0x12 146#define GLOBAL_IP_PRI_3 0x13 147#define GLOBAL_IP_PRI_4 0x14 148#define GLOBAL_IP_PRI_5 0x15 149#define GLOBAL_IP_PRI_6 0x16 150#define GLOBAL_IP_PRI_7 0x17 151#define GLOBAL_IEEE_PRI 0x18 152#define GLOBAL_CORE_TAG_TYPE 0x19 153#define GLOBAL_MONITOR_CONTROL 0x1a 154#define GLOBAL_CONTROL_2 0x1c 155#define GLOBAL_STATS_OP 0x1d 156#define GLOBAL_STATS_OP_BUSY BIT(15) 157#define GLOBAL_STATS_OP_NOP (0 << 12) 158#define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY) 159#define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY) 160#define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY) 161#define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY) 162#define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY) 163#define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY) 164#define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY) 165#define GLOBAL_STATS_COUNTER_32 0x1e 166#define GLOBAL_STATS_COUNTER_01 0x1f 167 168#define REG_GLOBAL2 0x1c 169#define GLOBAL2_INT_SOURCE 0x00 170#define GLOBAL2_INT_MASK 0x01 171#define GLOBAL2_MGMT_EN_2X 0x02 172#define GLOBAL2_MGMT_EN_0X 0x03 173#define GLOBAL2_FLOW_CONTROL 0x04 174#define GLOBAL2_SWITCH_MGMT 0x05 175#define GLOBAL2_DEVICE_MAPPING 0x06 176#define GLOBAL2_TRUNK_MASK 0x07 177#define GLOBAL2_TRUNK_MAPPING 0x08 178#define GLOBAL2_INGRESS_OP 0x09 179#define GLOBAL2_INGRESS_DATA 0x0a 180#define GLOBAL2_PVT_ADDR 0x0b 181#define GLOBAL2_PVT_DATA 0x0c 182#define GLOBAL2_SWITCH_MAC 0x0d 183#define GLOBAL2_SWITCH_MAC_BUSY BIT(15) 184#define GLOBAL2_ATU_STATS 0x0e 185#define GLOBAL2_PRIO_OVERRIDE 0x0f 186#define GLOBAL2_EEPROM_OP 0x14 187#define GLOBAL2_EEPROM_OP_BUSY BIT(15) 188#define GLOBAL2_EEPROM_OP_LOAD BIT(11) 189#define GLOBAL2_EEPROM_DATA 0x15 190#define GLOBAL2_PTP_AVB_OP 0x16 191#define GLOBAL2_PTP_AVB_DATA 0x17 192#define GLOBAL2_SMI_OP 0x18 193#define GLOBAL2_SMI_OP_BUSY BIT(15) 194#define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12) 195#define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \ 196 GLOBAL2_SMI_OP_CLAUSE_22) 197#define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \ 198 GLOBAL2_SMI_OP_CLAUSE_22) 199#define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY) 200#define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY) 201#define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY) 202#define GLOBAL2_SMI_DATA 0x19 203#define GLOBAL2_SCRATCH_MISC 0x1a 204#define GLOBAL2_WDOG_CONTROL 0x1b 205#define GLOBAL2_QOS_WEIGHT 0x1c 206#define GLOBAL2_MISC 0x1d 207 208struct mv88e6xxx_priv_state { 209 /* When using multi-chip addressing, this mutex protects 210 * access to the indirect access registers. (In single-chip 211 * mode, this mutex is effectively useless.) 212 */ 213 struct mutex smi_mutex; 214 215#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU 216 /* Handles automatic disabling and re-enabling of the PHY 217 * polling unit. 218 */ 219 struct mutex ppu_mutex; 220 int ppu_disabled; 221 struct work_struct ppu_work; 222 struct timer_list ppu_timer; 223#endif 224 225 /* This mutex serialises access to the statistics unit. 226 * Hold this mutex over snapshot + dump sequences. 227 */ 228 struct mutex stats_mutex; 229 230 /* This mutex serializes phy access for chips with 231 * indirect phy addressing. It is unused for chips 232 * with direct phy access. 233 */ 234 struct mutex phy_mutex; 235 236 /* This mutex serializes eeprom access for chips with 237 * eeprom support. 238 */ 239 struct mutex eeprom_mutex; 240 241 int id; /* switch product id */ 242 int num_ports; /* number of switch ports */ 243 244 /* hw bridging */ 245 246 u32 fid_mask; 247 u8 fid[DSA_MAX_PORTS]; 248 u16 bridge_mask[DSA_MAX_PORTS]; 249 250 unsigned long port_state_update_mask; 251 u8 port_state[DSA_MAX_PORTS]; 252 253 struct work_struct bridge_work; 254}; 255 256struct mv88e6xxx_hw_stat { 257 char string[ETH_GSTRING_LEN]; 258 int sizeof_stat; 259 int reg; 260}; 261 262int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active); 263int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port); 264int mv88e6xxx_setup_common(struct dsa_switch *ds); 265int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg); 266int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg); 267int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr, 268 int reg, u16 val); 269int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val); 270int mv88e6xxx_config_prio(struct dsa_switch *ds); 271int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr); 272int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr); 273int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum); 274int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val); 275int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum); 276int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum, 277 u16 val); 278void mv88e6xxx_ppu_state_init(struct dsa_switch *ds); 279int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum); 280int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr, 281 int regnum, u16 val); 282void mv88e6xxx_poll_link(struct dsa_switch *ds); 283void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data); 284void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 285 uint64_t *data); 286int mv88e6xxx_get_sset_count(struct dsa_switch *ds); 287int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds); 288int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port); 289void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 290 struct ethtool_regs *regs, void *_p); 291int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp); 292int mv88e6xxx_phy_wait(struct dsa_switch *ds); 293int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds); 294int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds); 295int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum); 296int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum, 297 u16 val); 298int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e); 299int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, 300 struct phy_device *phydev, struct ethtool_eee *e); 301int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask); 302int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask); 303int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state); 304int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 305 const unsigned char *addr, u16 vid); 306int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 307 const unsigned char *addr, u16 vid); 308int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port, 309 unsigned char *addr, bool *is_static); 310int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg); 311int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, 312 int reg, int val); 313extern struct dsa_switch_driver mv88e6131_switch_driver; 314extern struct dsa_switch_driver mv88e6123_61_65_switch_driver; 315extern struct dsa_switch_driver mv88e6352_switch_driver; 316extern struct dsa_switch_driver mv88e6171_switch_driver; 317 318#define REG_READ(addr, reg) \ 319 ({ \ 320 int __ret; \ 321 \ 322 __ret = mv88e6xxx_reg_read(ds, addr, reg); \ 323 if (__ret < 0) \ 324 return __ret; \ 325 __ret; \ 326 }) 327 328#define REG_WRITE(addr, reg, val) \ 329 ({ \ 330 int __ret; \ 331 \ 332 __ret = mv88e6xxx_reg_write(ds, addr, reg, val); \ 333 if (__ret < 0) \ 334 return __ret; \ 335 }) 336 337 338 339#endif 340