Lines Matching refs:BIT
23 #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0)
24 #define EXYNOS_4x12_UPHYPWR_PHY0_PWR BIT(3)
25 #define EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR BIT(4)
26 #define EXYNOS_4x12_UPHYPWR_PHY0_SLEEP BIT(5)
33 #define EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND BIT(6)
34 #define EXYNOS_4x12_UPHYPWR_PHY1_PWR BIT(7)
35 #define EXYNOS_4x12_UPHYPWR_PHY1_SLEEP BIT(8)
41 #define EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND BIT(9)
42 #define EXYNOS_4x12_UPHYPWR_HSIC0_PWR BIT(10)
43 #define EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP BIT(11)
49 #define EXYNOS_4x12_UPHYPWR_HSIC1_SUSPEND BIT(12)
50 #define EXYNOS_4x12_UPHYPWR_HSIC1_PWR BIT(13)
51 #define EXYNOS_4x12_UPHYPWR_HSIC1_SLEEP BIT(14)
72 #define EXYNOS_4x12_UPHYCLK_PHY0_ID_PULLUP BIT(3)
73 #define EXYNOS_4x12_UPHYCLK_PHY0_COMMON_ON BIT(4)
74 #define EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON BIT(7)
87 #define EXYNOS_4x12_URSTCON_PHY0 BIT(0)
88 #define EXYNOS_4x12_URSTCON_OTG_HLINK BIT(1)
89 #define EXYNOS_4x12_URSTCON_OTG_PHYLINK BIT(2)
90 #define EXYNOS_4x12_URSTCON_HOST_PHY BIT(3)
101 #define EXYNOS_4x12_URSTCON_PHY1 BIT(4)
102 #define EXYNOS_4x12_URSTCON_HSIC0 BIT(6)
103 #define EXYNOS_4x12_URSTCON_HSIC1 BIT(5)
104 #define EXYNOS_4x12_URSTCON_HOST_LINK_ALL BIT(7)
105 #define EXYNOS_4x12_URSTCON_HOST_LINK_P0 BIT(10)
106 #define EXYNOS_4x12_URSTCON_HOST_LINK_P1 BIT(9)
107 #define EXYNOS_4x12_URSTCON_HOST_LINK_P2 BIT(8)
111 #define EXYNOS_4x12_USB_ISOL_OTG BIT(0)
113 #define EXYNOS_4x12_USB_ISOL_HSIC0 BIT(0)
115 #define EXYNOS_4x12_USB_ISOL_HSIC1 BIT(0)