Lines Matching refs:BIT
68 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
71 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},\
74 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
77 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
85 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
99 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0},
107 BIT(4)|BIT(3), (BIT(4)|BIT(3))},\
113 BIT(3)|BIT(4), BIT(3)}, \
117 PWR_CMD_WRITE, BIT(3)|BIT(4), \
118 BIT(3)|BIT(4)}, \
122 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
126 PWR_CMD_POLLING, BIT(1), 0},
134 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
137 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
140 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
149 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
153 PWR_CMD_WRITE, BIT(2), BIT(2)}, \
157 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
161 PWR_CMD_POLLING, BIT(1), 0},
170 PWR_CMD_WRITE, BIT(0), 0}, \
174 PWR_CMD_POLLING, BIT(1), BIT(1)},\
178 PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
189 PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
192 PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
199 PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
230 PWR_CMD_WRITE, BIT(0), 0},\
236 PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \
242 PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
246 PWR_CMD_WRITE, BIT(5), BIT(5)},\
266 PWR_CMD_WRITE, BIT(4), 0}, \
270 PWR_CMD_POLLING, BIT(7), 0}, \
274 PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\
278 PWR_CMD_WRITE, BIT(1), BIT(1)},\
286 PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\