100 	mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |  in rk3288_slp_mode_set()
101 		   BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |  in rk3288_slp_mode_set()
102 		   BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |  in rk3288_slp_mode_set()
103 		   BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) |  in rk3288_slp_mode_set()
104 		   BIT(PMU_SCU_EN);  in rk3288_slp_mode_set()
106 	mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP);  in rk3288_slp_mode_set()
110 		mode_set |= BIT(PMU_BUS_PD_EN) |  in rk3288_slp_mode_set()
111 			    BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |  in rk3288_slp_mode_set()
112 			    BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) |  in rk3288_slp_mode_set()
113 			    BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);  in rk3288_slp_mode_set()
115 		mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |  in rk3288_slp_mode_set()
116 			     BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);  in rk3288_slp_mode_set()
123 		mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);  in rk3288_slp_mode_set()