1/*
2 * linux/mfd/tps65218.h
3 *
4 * Functions to access TPS65219 power management chip.
5 *
6 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether expressed or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License version 2 for more details.
16 */
17
18#ifndef __LINUX_MFD_TPS65218_H
19#define __LINUX_MFD_TPS65218_H
20
21#include <linux/i2c.h>
22#include <linux/regulator/driver.h>
23#include <linux/regulator/machine.h>
24#include <linux/bitops.h>
25
26/* TPS chip id list */
27#define TPS65218			0xF0
28
29/* I2C ID for TPS65218 part */
30#define TPS65218_I2C_ID			0x24
31
32/* All register addresses */
33#define TPS65218_REG_CHIPID		0x00
34#define TPS65218_REG_INT1		0x01
35#define TPS65218_REG_INT2		0x02
36#define TPS65218_REG_INT_MASK1		0x03
37#define TPS65218_REG_INT_MASK2		0x04
38#define TPS65218_REG_STATUS		0x05
39#define TPS65218_REG_CONTROL		0x06
40#define TPS65218_REG_FLAG		0x07
41
42#define TPS65218_REG_PASSWORD		0x10
43#define TPS65218_REG_ENABLE1		0x11
44#define TPS65218_REG_ENABLE2		0x12
45#define TPS65218_REG_CONFIG1		0x13
46#define TPS65218_REG_CONFIG2		0x14
47#define TPS65218_REG_CONFIG3		0x15
48#define TPS65218_REG_CONTROL_DCDC1	0x16
49#define TPS65218_REG_CONTROL_DCDC2	0x17
50#define TPS65218_REG_CONTROL_DCDC3	0x18
51#define TPS65218_REG_CONTROL_DCDC4	0x19
52#define TPS65218_REG_CONTRL_SLEW_RATE	0x1A
53#define TPS65218_REG_CONTROL_LDO1	0x1B
54#define TPS65218_REG_SEQ1		0x20
55#define TPS65218_REG_SEQ2		0x21
56#define TPS65218_REG_SEQ3		0x22
57#define TPS65218_REG_SEQ4		0x23
58#define TPS65218_REG_SEQ5		0x24
59#define TPS65218_REG_SEQ6		0x25
60#define TPS65218_REG_SEQ7		0x26
61
62/* Register field definitions */
63#define TPS65218_CHIPID_CHIP_MASK	0xF8
64#define TPS65218_CHIPID_REV_MASK	0x07
65
66#define TPS65218_INT1_VPRG		BIT(5)
67#define TPS65218_INT1_AC		BIT(4)
68#define TPS65218_INT1_PB		BIT(3)
69#define TPS65218_INT1_HOT		BIT(2)
70#define TPS65218_INT1_CC_AQC		BIT(1)
71#define TPS65218_INT1_PRGC		BIT(0)
72
73#define TPS65218_INT2_LS3_F		BIT(5)
74#define TPS65218_INT2_LS2_F		BIT(4)
75#define TPS65218_INT2_LS1_F		BIT(3)
76#define TPS65218_INT2_LS3_I		BIT(2)
77#define TPS65218_INT2_LS2_I		BIT(1)
78#define TPS65218_INT2_LS1_I		BIT(0)
79
80#define TPS65218_INT_MASK1_VPRG		BIT(5)
81#define TPS65218_INT_MASK1_AC		BIT(4)
82#define TPS65218_INT_MASK1_PB		BIT(3)
83#define TPS65218_INT_MASK1_HOT		BIT(2)
84#define TPS65218_INT_MASK1_CC_AQC	BIT(1)
85#define TPS65218_INT_MASK1_PRGC		BIT(0)
86
87#define TPS65218_INT_MASK2_LS3_F	BIT(5)
88#define TPS65218_INT_MASK2_LS2_F	BIT(4)
89#define TPS65218_INT_MASK2_LS1_F	BIT(3)
90#define TPS65218_INT_MASK2_LS3_I	BIT(2)
91#define TPS65218_INT_MASK2_LS2_I	BIT(1)
92#define TPS65218_INT_MASK2_LS1_I	BIT(0)
93
94#define TPS65218_STATUS_FSEAL		BIT(7)
95#define TPS65218_STATUS_EE		BIT(6)
96#define TPS65218_STATUS_AC_STATE	BIT(5)
97#define TPS65218_STATUS_PB_STATE	BIT(4)
98#define TPS65218_STATUS_STATE_MASK	0xC
99#define TPS65218_STATUS_CC_STAT		0x3
100
101#define TPS65218_CONTROL_OFFNPFO	BIT(1)
102#define TPS65218_CONTROL_CC_AQ	BIT(0)
103
104#define TPS65218_FLAG_GPO3_FLG		BIT(7)
105#define TPS65218_FLAG_GPO2_FLG		BIT(6)
106#define TPS65218_FLAG_GPO1_FLG		BIT(5)
107#define TPS65218_FLAG_LDO1_FLG		BIT(4)
108#define TPS65218_FLAG_DC4_FLG		BIT(3)
109#define TPS65218_FLAG_DC3_FLG		BIT(2)
110#define TPS65218_FLAG_DC2_FLG		BIT(1)
111#define TPS65218_FLAG_DC1_FLG		BIT(0)
112
113#define TPS65218_ENABLE1_DC6_EN		BIT(5)
114#define TPS65218_ENABLE1_DC5_EN		BIT(4)
115#define TPS65218_ENABLE1_DC4_EN		BIT(3)
116#define TPS65218_ENABLE1_DC3_EN		BIT(2)
117#define TPS65218_ENABLE1_DC2_EN		BIT(1)
118#define TPS65218_ENABLE1_DC1_EN		BIT(0)
119
120#define TPS65218_ENABLE2_GPIO3		BIT(6)
121#define TPS65218_ENABLE2_GPIO2		BIT(5)
122#define TPS65218_ENABLE2_GPIO1		BIT(4)
123#define TPS65218_ENABLE2_LS3_EN		BIT(3)
124#define TPS65218_ENABLE2_LS2_EN		BIT(2)
125#define TPS65218_ENABLE2_LS1_EN		BIT(1)
126#define TPS65218_ENABLE2_LDO1_EN	BIT(0)
127
128
129#define TPS65218_CONFIG1_TRST		BIT(7)
130#define TPS65218_CONFIG1_GPO2_BUF	BIT(6)
131#define TPS65218_CONFIG1_IO1_SEL	BIT(5)
132#define TPS65218_CONFIG1_PGDLY_MASK	0x18
133#define TPS65218_CONFIG1_STRICT		BIT(2)
134#define TPS65218_CONFIG1_UVLO_MASK	0x3
135
136#define TPS65218_CONFIG2_DC12_RST	BIT(7)
137#define TPS65218_CONFIG2_UVLOHYS	BIT(6)
138#define TPS65218_CONFIG2_LS3ILIM_MASK	0xC
139#define TPS65218_CONFIG2_LS2ILIM_MASK	0x3
140
141#define TPS65218_CONFIG3_LS3NPFO	BIT(5)
142#define TPS65218_CONFIG3_LS2NPFO	BIT(4)
143#define TPS65218_CONFIG3_LS1NPFO	BIT(3)
144#define TPS65218_CONFIG3_LS3DCHRG	BIT(2)
145#define TPS65218_CONFIG3_LS2DCHRG	BIT(1)
146#define TPS65218_CONFIG3_LS1DCHRG	BIT(0)
147
148#define TPS65218_CONTROL_DCDC1_PFM	BIT(7)
149#define TPS65218_CONTROL_DCDC1_MASK	0x7F
150
151#define TPS65218_CONTROL_DCDC2_PFM	BIT(7)
152#define TPS65218_CONTROL_DCDC2_MASK	0x3F
153
154#define TPS65218_CONTROL_DCDC3_PFM	BIT(7)
155#define TPS65218_CONTROL_DCDC3_MASK	0x3F
156
157#define TPS65218_CONTROL_DCDC4_PFM	BIT(7)
158#define TPS65218_CONTROL_DCDC4_MASK	0x3F
159
160#define TPS65218_SLEW_RATE_GO		BIT(7)
161#define TPS65218_SLEW_RATE_GODSBL	BIT(6)
162#define TPS65218_SLEW_RATE_SLEW_MASK	0x7
163
164#define TPS65218_CONTROL_LDO1_MASK	0x3F
165
166#define TPS65218_SEQ1_DLY8		BIT(7)
167#define TPS65218_SEQ1_DLY7		BIT(6)
168#define TPS65218_SEQ1_DLY6		BIT(5)
169#define TPS65218_SEQ1_DLY5		BIT(4)
170#define TPS65218_SEQ1_DLY4		BIT(3)
171#define TPS65218_SEQ1_DLY3		BIT(2)
172#define TPS65218_SEQ1_DLY2		BIT(1)
173#define TPS65218_SEQ1_DLY1		BIT(0)
174
175#define TPS65218_SEQ2_DLYFCTR		BIT(7)
176#define TPS65218_SEQ2_DLY9		BIT(0)
177
178#define TPS65218_SEQ3_DC2_SEQ_MASK	0xF0
179#define TPS65218_SEQ3_DC1_SEQ_MASK	0xF
180
181#define TPS65218_SEQ4_DC4_SEQ_MASK	0xF0
182#define TPS65218_SEQ4_DC3_SEQ_MASK	0xF
183
184#define TPS65218_SEQ5_DC6_SEQ_MASK	0xF0
185#define TPS65218_SEQ5_DC5_SEQ_MASK	0xF
186
187#define TPS65218_SEQ6_LS1_SEQ_MASK	0xF0
188#define TPS65218_SEQ6_LDO1_SEQ_MASK	0xF
189
190#define TPS65218_SEQ7_GPO3_SEQ_MASK	0xF0
191#define TPS65218_SEQ7_GPO1_SEQ_MASK	0xF
192#define TPS65218_PROTECT_NONE		0
193#define TPS65218_PROTECT_L1		1
194
195enum tps65218_regulator_id {
196	/* DCDC's */
197	TPS65218_DCDC_1,
198	TPS65218_DCDC_2,
199	TPS65218_DCDC_3,
200	TPS65218_DCDC_4,
201	TPS65218_DCDC_5,
202	TPS65218_DCDC_6,
203	/* LDOs */
204	TPS65218_LDO_1,
205};
206
207#define TPS65218_MAX_REG_ID		TPS65218_LDO_1
208
209/* Number of step-down converters available */
210#define TPS65218_NUM_DCDC		6
211/* Number of LDO voltage regulators available */
212#define TPS65218_NUM_LDO		1
213/* Number of total regulators available */
214#define TPS65218_NUM_REGULATOR		(TPS65218_NUM_DCDC + TPS65218_NUM_LDO)
215
216/* Define the TPS65218 IRQ numbers */
217enum tps65218_irqs {
218	/* INT1 registers */
219	TPS65218_PRGC_IRQ,
220	TPS65218_CC_AQC_IRQ,
221	TPS65218_HOT_IRQ,
222	TPS65218_PB_IRQ,
223	TPS65218_AC_IRQ,
224	TPS65218_VPRG_IRQ,
225	TPS65218_INVALID1_IRQ,
226	TPS65218_INVALID2_IRQ,
227	/* INT2 registers */
228	TPS65218_LS1_I_IRQ,
229	TPS65218_LS2_I_IRQ,
230	TPS65218_LS3_I_IRQ,
231	TPS65218_LS1_F_IRQ,
232	TPS65218_LS2_F_IRQ,
233	TPS65218_LS3_F_IRQ,
234	TPS65218_INVALID3_IRQ,
235	TPS65218_INVALID4_IRQ,
236};
237
238/**
239 * struct tps_info - packages regulator constraints
240 * @id:			Id of the regulator
241 * @name:		Voltage regulator name
242 * @min_uV:		minimum micro volts
243 * @max_uV:		minimum micro volts
244 *
245 * This data is used to check the regualtor voltage limits while setting.
246 */
247struct tps_info {
248	int id;
249	const char *name;
250	int min_uV;
251	int max_uV;
252};
253
254/**
255 * struct tps65218 - tps65218 sub-driver chip access routines
256 *
257 * Device data may be used to access the TPS65218 chip
258 */
259
260struct tps65218 {
261	struct device *dev;
262	unsigned int id;
263
264	struct mutex tps_lock;		/* lock guarding the data structure */
265	/* IRQ Data */
266	int irq;
267	u32 irq_mask;
268	struct regmap_irq_chip_data *irq_data;
269	struct regulator_desc desc[TPS65218_NUM_REGULATOR];
270	struct tps_info *info[TPS65218_NUM_REGULATOR];
271	struct regmap *regmap;
272};
273
274int tps65218_reg_read(struct tps65218 *tps, unsigned int reg,
275					unsigned int *val);
276int tps65218_reg_write(struct tps65218 *tps, unsigned int reg,
277			unsigned int val, unsigned int level);
278int tps65218_set_bits(struct tps65218 *tps, unsigned int reg,
279		unsigned int mask, unsigned int val, unsigned int level);
280int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg,
281		unsigned int mask, unsigned int level);
282
283#endif /*  __LINUX_MFD_TPS65218_H */
284