Lines Matching refs:BIT
101 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
102 #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
103 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
104 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
105 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
106 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
503 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
504 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
505 #define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
506 #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
507 #define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */
508 #define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */
509 #define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */
510 #define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout …
511 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */
512 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
513 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
514 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
515 #define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
516 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
517 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
528 #define BCMA_CHIPCTL_5357_EXTPA BIT(14)
529 #define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
530 #define BCMA_CHIPCTL_5357_NFLASH BIT(16)
531 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
532 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
534 #define BCMA_RES_4314_LPLDO_PU BIT(0)
535 #define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
536 #define BCMA_RES_4314_PMU_BG_PU BIT(2)
537 #define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
538 #define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
539 #define BCMA_RES_4314_CLDO_PU BIT(5)
540 #define BCMA_RES_4314_LPLDO2_LVM BIT(6)
541 #define BCMA_RES_4314_WL_PMU_PU BIT(7)
542 #define BCMA_RES_4314_LNLDO_PU BIT(8)
543 #define BCMA_RES_4314_LDO3P3_PU BIT(9)
544 #define BCMA_RES_4314_OTP_PU BIT(10)
545 #define BCMA_RES_4314_XTAL_PU BIT(11)
546 #define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
547 #define BCMA_RES_4314_LQ_AVAIL BIT(13)
548 #define BCMA_RES_4314_LOGIC_RET BIT(14)
549 #define BCMA_RES_4314_MEM_SLEEP BIT(15)
550 #define BCMA_RES_4314_MACPHY_RET BIT(16)
551 #define BCMA_RES_4314_WL_CORE_READY BIT(17)
552 #define BCMA_RES_4314_ILP_REQ BIT(18)
553 #define BCMA_RES_4314_ALP_AVAIL BIT(19)
554 #define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
555 #define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
556 #define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
557 #define BCMA_RES_4314_RADIO_PU BIT(23)
558 #define BCMA_RES_4314_VCO_LDO_PU BIT(24)
559 #define BCMA_RES_4314_AFE_LDO_PU BIT(25)
560 #define BCMA_RES_4314_RX_LDO_PU BIT(26)
561 #define BCMA_RES_4314_TX_LDO_PU BIT(27)
562 #define BCMA_RES_4314_HT_AVAIL BIT(28)
563 #define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)