Lines Matching refs:BIT
123 #define valid_bit cpu_to_le32(BIT(VALID_BIT))
124 #define dma_done_ie cpu_to_le32(BIT(DMA_DONE_INTERRUPT_ENABLE))
132 tmp |= BIT(ep->num); in enable_pciirqenb()
134 tmp |= BIT(ep_bit[ep->num]); in enable_pciirqenb()
200 writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat); in net2280_enable()
207 writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE), in net2280_enable()
226 tmp |= BIT(ENDPOINT_ENABLE); in net2280_enable()
232 tmp |= BIT(IN_ENDPOINT_ENABLE); in net2280_enable()
234 tmp |= BIT(ENDPOINT_DIRECTION); in net2280_enable()
237 tmp |= BIT(OUT_ENDPOINT_ENABLE); in net2280_enable()
250 writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp); in net2280_enable()
255 writel(BIT(CLEAR_NAK_OUT_PACKETS) | in net2280_enable()
256 BIT(CLEAR_NAK_OUT_PACKETS_MODE), &ep->regs->ep_rsp); in net2280_enable()
265 tmp = BIT(DATA_PACKET_RECEIVED_INTERRUPT_ENABLE) | in net2280_enable()
266 BIT(DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE); in net2280_enable()
271 tmp = BIT((8 + ep->num)); /* completion */ in net2280_enable()
280 tmp = BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE); in net2280_enable()
335 writel(BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) | in ep_reset_228x()
336 BIT(DMA_TRANSACTION_DONE_INTERRUPT) | in ep_reset_228x()
337 BIT(DMA_ABORT), in ep_reset_228x()
341 tmp &= ~BIT(ep->num); in ep_reset_228x()
345 tmp &= ~BIT((8 + ep->num)); /* completion */ in ep_reset_228x()
354 tmp = BIT(SET_NAK_OUT_PACKETS_MODE) | in ep_reset_228x()
355 BIT(SET_NAK_OUT_PACKETS) | in ep_reset_228x()
356 BIT(CLEAR_EP_HIDE_STATUS_PHASE) | in ep_reset_228x()
357 BIT(CLEAR_INTERRUPT_MODE); in ep_reset_228x()
360 tmp = BIT(CLEAR_NAK_OUT_PACKETS_MODE) | in ep_reset_228x()
361 BIT(CLEAR_NAK_OUT_PACKETS) | in ep_reset_228x()
362 BIT(CLEAR_EP_HIDE_STATUS_PHASE) | in ep_reset_228x()
363 BIT(CLEAR_INTERRUPT_MODE); in ep_reset_228x()
367 tmp |= BIT(CLEAR_ENDPOINT_TOGGLE) | in ep_reset_228x()
368 BIT(CLEAR_ENDPOINT_HALT); in ep_reset_228x()
374 tmp = BIT(FIFO_OVERFLOW) | in ep_reset_228x()
375 BIT(FIFO_UNDERFLOW); in ep_reset_228x()
379 writel(tmp | BIT(TIMEOUT) | in ep_reset_228x()
380 BIT(USB_STALL_SENT) | in ep_reset_228x()
381 BIT(USB_IN_NAK_SENT) | in ep_reset_228x()
382 BIT(USB_IN_ACK_RCVD) | in ep_reset_228x()
383 BIT(USB_OUT_PING_NAK_SENT) | in ep_reset_228x()
384 BIT(USB_OUT_ACK_SENT) | in ep_reset_228x()
385 BIT(FIFO_FLUSH) | in ep_reset_228x()
386 BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) | in ep_reset_228x()
387 BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) | in ep_reset_228x()
388 BIT(DATA_PACKET_RECEIVED_INTERRUPT) | in ep_reset_228x()
389 BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | in ep_reset_228x()
390 BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in ep_reset_228x()
391 BIT(DATA_IN_TOKEN_INTERRUPT), in ep_reset_228x()
411 writel(BIT(DMA_ABORT_DONE_INTERRUPT) | in ep_reset_338x()
412 BIT(DMA_PAUSE_DONE_INTERRUPT) | in ep_reset_338x()
413 BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) | in ep_reset_338x()
414 BIT(DMA_TRANSACTION_DONE_INTERRUPT), in ep_reset_338x()
426 tmp &= ~BIT(ep_bit[ep->num]); in ep_reset_338x()
431 tmp &= ~BIT((8 + ep->num)); /* completion */ in ep_reset_338x()
437 writel(BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) | in ep_reset_338x()
438 BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) | in ep_reset_338x()
439 BIT(FIFO_OVERFLOW) | in ep_reset_338x()
440 BIT(DATA_PACKET_RECEIVED_INTERRUPT) | in ep_reset_338x()
441 BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | in ep_reset_338x()
442 BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in ep_reset_338x()
443 BIT(DATA_IN_TOKEN_INTERRUPT), &ep->regs->ep_stat); in ep_reset_338x()
612 if (tmp & BIT(NAK_OUT_PACKETS)) { in out_flush()
615 writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp); in out_flush()
618 writel(BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in out_flush()
619 BIT(DATA_PACKET_RECEIVED_INTERRUPT), in out_flush()
621 writel(BIT(FIFO_FLUSH), statp); in out_flush()
625 if (tmp & BIT(DATA_OUT_PING_TOKEN_INTERRUPT) && in out_flush()
631 handshake(statp, BIT(USB_OUT_PING_NAK_SENT), in out_flush()
632 BIT(USB_OUT_PING_NAK_SENT), usec); in out_flush()
658 if ((tmp & BIT(NAK_OUT_PACKETS))) in read_fifo()
660 else if ((tmp & BIT(FIFO_FULL))) { in read_fifo()
677 if (count == 0 && (tmp & BIT(NAK_OUT_PACKETS)) == 0) in read_fifo()
723 writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp); in read_fifo()
744 dmacount |= BIT(DMA_DIRECTION); in fill_dma_desc()
747 dmacount |= BIT(END_OF_CHAIN); in fill_dma_desc()
751 dmacount |= BIT(VALID_BIT); in fill_dma_desc()
752 dmacount |= BIT(DMA_DONE_INTERRUPT_ENABLE); in fill_dma_desc()
763 BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) |
764 BIT(DMA_CLEAR_COUNT_ENABLE) |
767 BIT(DMA_VALID_BIT_POLLING_ENABLE) |
768 BIT(DMA_VALID_BIT_ENABLE) |
769 BIT(DMA_SCATTER_GATHER_ENABLE) |
771 BIT(DMA_ENABLE);
775 handshake(&dma->dmactl, BIT(DMA_ENABLE), 0, 50); in spin_stop_dma()
780 writel(readl(&dma->dmactl) & ~BIT(DMA_ENABLE), &dma->dmactl); in stop_dma()
787 unsigned int tmp = BIT(VALID_BIT) | (ep->is_in << DMA_DIRECTION); in start_queue()
790 tmp |= BIT(END_OF_CHAIN); in start_queue()
797 dmactl |= BIT(DMA_REQUEST_OUTSTANDING); in start_queue()
803 writel(BIT(DMA_START), &dma->dmastat); in start_queue()
817 WARN_ON(readl(&dma->dmactl) & BIT(DMA_ENABLE)); in start_dma()
822 BIT(NAK_OUT_PACKETS))) { in start_dma()
823 writel(BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT), in start_dma()
836 writel(BIT(DMA_DONE_INTERRUPT_ENABLE) | tmp, in start_dma()
841 writel(BIT(DMA_ENABLE), &dma->dmactl); in start_dma()
842 writel(BIT(DMA_START), &dma->dmastat); in start_dma()
856 tmp |= BIT(DMA_FIFO_VALIDATE); in start_dma()
866 req->td->dmacount |= cpu_to_le32(BIT(END_OF_CHAIN)); in start_dma()
981 (readl(&ep->regs->ep_rsp) & BIT(CLEAR_ENDPOINT_HALT)))) { in net2280_queue()
1003 if ((s & BIT(FIFO_EMPTY)) == 0) { in net2280_queue()
1025 if (req && (s & BIT(NAK_OUT_PACKETS))) in net2280_queue()
1026 writel(BIT(CLEAR_NAK_OUT_PACKETS), in net2280_queue()
1086 if ((tmp & BIT(VALID_BIT)) != 0) in scan_dma_completions()
1110 if ((tmp & BIT(NAK_OUT_PACKETS)) == 0) { in scan_dma_completions()
1147 writel(BIT(DMA_ABORT), &ep->dma->dmastat); in abort_dma()
1350 avail = readl(&ep->regs->ep_avail) & (BIT(12) - 1); in net2280_fifo_status()
1376 writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat); in net2280_fifo_flush()
1425 if (tmp & BIT(DEVICE_REMOTE_WAKEUP_ENABLE)) in net2280_wakeup()
1426 writel(BIT(GENERATE_RESUME), &dev->usb->usbstat); in net2280_wakeup()
1446 tmp |= BIT(SELF_POWERED_STATUS); in net2280_set_selfpowered()
1449 tmp &= ~BIT(SELF_POWERED_STATUS); in net2280_set_selfpowered()
1472 tmp |= BIT(USB_DETECT_ENABLE); in net2280_pullup()
1474 tmp &= ~BIT(USB_DETECT_ENABLE); in net2280_pullup()
1557 if (t1 & BIT(VBUS_PIN)) { in registers_show()
1558 if (t2 & BIT(HIGH_SPEED)) in registers_show()
1593 (t2 & BIT(CLEAR_NAK_OUT_PACKETS)) in registers_show()
1595 (t2 & BIT(CLEAR_EP_HIDE_STATUS_PHASE)) in registers_show()
1597 (t2 & BIT(CLEAR_EP_FORCE_CRC_ERROR)) in registers_show()
1599 (t2 & BIT(CLEAR_INTERRUPT_MODE)) in registers_show()
1601 (t2 & BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE)) in registers_show()
1603 (t2 & BIT(CLEAR_NAK_OUT_PACKETS_MODE)) in registers_show()
1605 (t2 & BIT(CLEAR_ENDPOINT_TOGGLE)) in registers_show()
1607 (t2 & BIT(CLEAR_ENDPOINT_HALT)) in registers_show()
1834 tmp_reg &= ~BIT(NON_CTRL_IN_TOLERATE_BAD_DIR); in defect7374_disable_data_eps()
1837 tmp_reg |= BIT(EP_INITIALIZED); in defect7374_disable_data_eps()
1860 tmp = ((0 << ENDPOINT_NUMBER) | BIT(ENDPOINT_DIRECTION) | in defect7374_enable_data_eps_zero()
1863 BIT(OUT_ENDPOINT_ENABLE) : BIT(ENDPOINT_ENABLE)) | in defect7374_enable_data_eps_zero()
1864 BIT(IN_ENDPOINT_ENABLE)); in defect7374_enable_data_eps_zero()
1870 tmp = ((0 << ENDPOINT_NUMBER) | BIT(ENDPOINT_ENABLE)); in defect7374_enable_data_eps_zero()
1887 BIT(CLEAR_ACK_ERROR_CODE) | 0); in defect7374_enable_data_eps_zero()
1897 BIT(NON_CTRL_IN_TOLERATE_BAD_DIR) | 0); in defect7374_enable_data_eps_zero()
1901 ~BIT(EP_INITIALIZED); in defect7374_enable_data_eps_zero()
1945 writel(~(u32)BIT(SUSPEND_REQUEST_INTERRUPT), &dev->regs->irqstat1), in usb_reset_228x()
1949 BIT(PCI_ENABLE) | in usb_reset_228x()
1950 BIT(FIFO_SOFT_RESET) | in usb_reset_228x()
1951 BIT(USB_SOFT_RESET) | in usb_reset_228x()
1952 BIT(M8051_RESET); in usb_reset_228x()
1988 BIT(PCI_ENABLE) | in usb_reset_338x()
1989 BIT(FIFO_SOFT_RESET) | in usb_reset_338x()
1990 BIT(USB_SOFT_RESET) | in usb_reset_338x()
1991 BIT(M8051_RESET); in usb_reset_338x()
2088 ~(BIT(U1_ENABLE) | BIT(U2_ENABLE) | BIT(LTM_ENABLE)); in usb_reinit_338x()
2127 val |= BIT(RECOVERY_IDLE_TO_RECOVER_FMW); in usb_reinit_338x()
2150 writel(BIT(CLEAR_EP_HIDE_STATUS_PHASE) | in ep0_start_228x()
2151 BIT(CLEAR_NAK_OUT_PACKETS) | in ep0_start_228x()
2152 BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), in ep0_start_228x()
2161 writel(BIT(SET_TEST_MODE) | in ep0_start_228x()
2162 BIT(SET_ADDRESS) | in ep0_start_228x()
2163 BIT(DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP) | in ep0_start_228x()
2164 BIT(GET_DEVICE_STATUS) | in ep0_start_228x()
2165 BIT(GET_INTERFACE_STATUS), in ep0_start_228x()
2167 writel(BIT(USB_ROOT_PORT_WAKEUP_ENABLE) | in ep0_start_228x()
2168 BIT(SELF_POWERED_USB_DEVICE) | in ep0_start_228x()
2169 BIT(REMOTE_WAKEUP_SUPPORT) | in ep0_start_228x()
2171 BIT(SELF_POWERED_STATUS), in ep0_start_228x()
2175 writel(BIT(SETUP_PACKET_INTERRUPT_ENABLE) | in ep0_start_228x()
2176 BIT(ENDPOINT_0_INTERRUPT_ENABLE), in ep0_start_228x()
2178 writel(BIT(PCI_INTERRUPT_ENABLE) | in ep0_start_228x()
2179 BIT(PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE) | in ep0_start_228x()
2180 BIT(PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE) | in ep0_start_228x()
2181 BIT(PCI_RETRY_ABORT_INTERRUPT_ENABLE) | in ep0_start_228x()
2182 BIT(VBUS_INTERRUPT_ENABLE) | in ep0_start_228x()
2183 BIT(ROOT_PORT_RESET_INTERRUPT_ENABLE) | in ep0_start_228x()
2184 BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE), in ep0_start_228x()
2195 writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE) | in ep0_start_338x()
2196 BIT(SET_EP_HIDE_STATUS_PHASE), in ep0_start_338x()
2205 writel(BIT(SET_ISOCHRONOUS_DELAY) | in ep0_start_338x()
2206 BIT(SET_SEL) | in ep0_start_338x()
2207 BIT(SET_TEST_MODE) | in ep0_start_338x()
2208 BIT(SET_ADDRESS) | in ep0_start_338x()
2209 BIT(GET_INTERFACE_STATUS) | in ep0_start_338x()
2210 BIT(GET_DEVICE_STATUS), in ep0_start_338x()
2213 writel(BIT(USB_ROOT_PORT_WAKEUP_ENABLE) | in ep0_start_338x()
2215 BIT(DEVICE_REMOTE_WAKEUP_ENABLE), in ep0_start_338x()
2219 writel(BIT(SETUP_PACKET_INTERRUPT_ENABLE) | in ep0_start_338x()
2220 BIT(ENDPOINT_0_INTERRUPT_ENABLE), in ep0_start_338x()
2222 writel(BIT(PCI_INTERRUPT_ENABLE) | in ep0_start_338x()
2223 BIT(ROOT_PORT_RESET_INTERRUPT_ENABLE) | in ep0_start_338x()
2224 BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE) | in ep0_start_338x()
2225 BIT(VBUS_INTERRUPT_ENABLE), in ep0_start_338x()
2369 writel(t & ~BIT(NAK_OUT_PACKETS), &ep->regs->ep_stat); in handle_ep_small()
2387 if (t & BIT(DATA_OUT_PING_TOKEN_INTERRUPT)) { in handle_ep_small()
2396 } else if (t & BIT(DATA_IN_TOKEN_INTERRUPT)) { in handle_ep_small()
2407 if (t & BIT(DATA_IN_TOKEN_INTERRUPT)) { in handle_ep_small()
2414 } else if (((t & BIT(DATA_OUT_PING_TOKEN_INTERRUPT)) && in handle_ep_small()
2433 if (t & BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT)) { in handle_ep_small()
2459 if (likely(t & BIT(FIFO_EMPTY))) { in handle_ep_small()
2471 writel(BIT(DMA_ABORT), &ep->dma->dmastat); in handle_ep_small()
2501 } else if (t & BIT(DATA_PACKET_RECEIVED_INTERRUPT)) { in handle_ep_small()
2506 } else if (t & BIT(DATA_PACKET_TRANSMITTED_INTERRUPT)) { in handle_ep_small()
2555 if (t & BIT(DATA_PACKET_TRANSMITTED_INTERRUPT)) in handle_ep_small()
2595 if (!(readl(&dev->usb->usbstat) & BIT(SUPER_SPEED_MODE))) { in defect7374_workaround()
2663 val |= BIT(SEQUENCE_NUMBER_RESET); in ep_clear_seqnum()
2691 status |= BIT(0); in handle_stat0_irqs_superspeed()
2705 BIT(CLEAR_ENDPOINT_HALT); in handle_stat0_irqs_superspeed()
2725 ~BIT(U1_ENABLE), in handle_stat0_irqs_superspeed()
2733 ~BIT(U2_ENABLE), in handle_stat0_irqs_superspeed()
2741 ~BIT(LTM_ENABLE), in handle_stat0_irqs_superspeed()
2753 ~BIT(DEVICE_REMOTE_WAKEUP_ENABLE), in handle_stat0_irqs_superspeed()
2791 BIT(U1_ENABLE), in handle_stat0_irqs_superspeed()
2799 BIT(U2_ENABLE), in handle_stat0_irqs_superspeed()
2807 BIT(LTM_ENABLE), in handle_stat0_irqs_superspeed()
2819 BIT(DEVICE_REMOTE_WAKEUP_ENABLE), in handle_stat0_irqs_superspeed()
2883 stat &= ~BIT(INTA_ASSERTED); in handle_stat0_irqs()
2889 if (unlikely(stat & BIT(SETUP_PACKET_INTERRUPT))) { in handle_stat0_irqs()
2899 if (val & BIT(SUPER_SPEED)) { in handle_stat0_irqs()
2903 } else if (val & BIT(HIGH_SPEED)) { in handle_stat0_irqs()
2921 stat &= ~BIT(ENDPOINT_0_INTERRUPT); in handle_stat0_irqs()
2932 tmp = BIT(FIFO_OVERFLOW) | in handle_stat0_irqs()
2933 BIT(FIFO_UNDERFLOW); in handle_stat0_irqs()
2937 writel(tmp | BIT(TIMEOUT) | in handle_stat0_irqs()
2938 BIT(USB_STALL_SENT) | in handle_stat0_irqs()
2939 BIT(USB_IN_NAK_SENT) | in handle_stat0_irqs()
2940 BIT(USB_IN_ACK_RCVD) | in handle_stat0_irqs()
2941 BIT(USB_OUT_PING_NAK_SENT) | in handle_stat0_irqs()
2942 BIT(USB_OUT_ACK_SENT) | in handle_stat0_irqs()
2943 BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) | in handle_stat0_irqs()
2944 BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) | in handle_stat0_irqs()
2945 BIT(DATA_PACKET_RECEIVED_INTERRUPT) | in handle_stat0_irqs()
2946 BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | in handle_stat0_irqs()
2947 BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in handle_stat0_irqs()
2948 BIT(DATA_IN_TOKEN_INTERRUPT), in handle_stat0_irqs()
2967 writel(BIT(SETUP_PACKET_INTERRUPT), &dev->regs->irqstat0); in handle_stat0_irqs()
2968 stat ^= BIT(SETUP_PACKET_INTERRUPT); in handle_stat0_irqs()
2977 scratch = BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) | in handle_stat0_irqs()
2978 BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in handle_stat0_irqs()
2979 BIT(DATA_IN_TOKEN_INTERRUPT); in handle_stat0_irqs()
2982 scratch = BIT(DATA_PACKET_RECEIVED_INTERRUPT) | in handle_stat0_irqs()
2983 BIT(DATA_OUT_PING_TOKEN_INTERRUPT) | in handle_stat0_irqs()
2984 BIT(DATA_IN_TOKEN_INTERRUPT); in handle_stat0_irqs()
3009 if (readl(&e->regs->ep_rsp) & BIT(SET_ENDPOINT_HALT)) in handle_stat0_irqs()
3108 t = BIT(num); in handle_stat0_irqs()
3121 #define DMA_INTERRUPTS (BIT(DMA_D_INTERRUPT) | \
3122 BIT(DMA_C_INTERRUPT) | \
3123 BIT(DMA_B_INTERRUPT) | \
3124 BIT(DMA_A_INTERRUPT))
3126 BIT(PCI_MASTER_ABORT_RECEIVED_INTERRUPT) | \
3127 BIT(PCI_TARGET_ABORT_RECEIVED_INTERRUPT) | \
3128 BIT(PCI_RETRY_ABORT_INTERRUPT))
3138 tmp = BIT(VBUS_INTERRUPT) | BIT(ROOT_PORT_RESET_INTERRUPT); in handle_stat1_irqs()
3139 mask = BIT(SUPER_SPEED) | BIT(HIGH_SPEED) | BIT(FULL_SPEED); in handle_stat1_irqs()
3156 if ((stat & BIT(VBUS_INTERRUPT)) && in handle_stat1_irqs()
3158 BIT(VBUS_PIN)) == 0) { in handle_stat1_irqs()
3162 } else if ((stat & BIT(ROOT_PORT_RESET_INTERRUPT)) && in handle_stat1_irqs()
3196 tmp = BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT); in handle_stat1_irqs()
3199 if (stat & BIT(SUSPEND_REQUEST_INTERRUPT)) { in handle_stat1_irqs()
3203 stat &= ~BIT(SUSPEND_REQUEST_INTERRUPT); in handle_stat1_irqs()
3218 stat &= ~(BIT(CONTROL_STATUS_INTERRUPT) | in handle_stat1_irqs()
3219 BIT(SUSPEND_REQUEST_INTERRUPT) | in handle_stat1_irqs()
3220 BIT(RESUME_INTERRUPT) | in handle_stat1_irqs()
3221 BIT(SOF_INTERRUPT)); in handle_stat1_irqs()
3223 stat &= ~(BIT(CONTROL_STATUS_INTERRUPT) | in handle_stat1_irqs()
3224 BIT(RESUME_INTERRUPT) | in handle_stat1_irqs()
3225 BIT(SOF_DOWN_INTERRUPT) | in handle_stat1_irqs()
3226 BIT(SOF_INTERRUPT)); in handle_stat1_irqs()
3239 tmp = BIT(num); in handle_stat1_irqs()
3258 (tmp & BIT(DMA_TRANSACTION_DONE_INTERRUPT))) in handle_stat1_irqs()
3262 if (!(tmp & BIT(DMA_TRANSACTION_DONE_INTERRUPT))) { in handle_stat1_irqs()
3313 (!(readl(&dev->regs->irqstat0) & BIT(INTA_ASSERTED)))) in net2280_irq()
3465 dev->enhanced_mode = !!(usbstat & BIT(11)); in net2280_probe()
3533 writel(BIT(DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE) | in net2280_probe()
3538 BIT(DMA_READ_MULTIPLE_ENABLE) | in net2280_probe()
3539 BIT(DMA_READ_LINE_ENABLE), in net2280_probe()