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Searched refs:reg_offset (Results 1 – 154 of 154) sorted by relevance

/linux-4.1.27/drivers/mfd/
Dsec-irq.c29 .reg_offset = 0,
33 .reg_offset = 0,
37 .reg_offset = 0,
41 .reg_offset = 0,
45 .reg_offset = 0,
49 .reg_offset = 0,
53 .reg_offset = 0,
57 .reg_offset = 0,
61 .reg_offset = 1,
65 .reg_offset = 1,
[all …]
Dda9063-irq.c40 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
44 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
48 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
52 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
56 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
61 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
65 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
69 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
73 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
77 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
[all …]
Dda9052-irq.c40 .reg_offset = 0,
44 .reg_offset = 0,
48 .reg_offset = 0,
52 .reg_offset = 0,
56 .reg_offset = 0,
60 .reg_offset = 0,
64 .reg_offset = 0,
68 .reg_offset = 0,
72 .reg_offset = 1,
76 .reg_offset = 1,
[all …]
Dwm5110-tables.c301 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
302 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
303 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
304 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
307 .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1
310 .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1
313 .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1
316 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
319 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
322 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
[all …]
Dpalmas.c78 .reg_offset = 1,
82 .reg_offset = 1,
86 .reg_offset = 1,
90 .reg_offset = 1,
94 .reg_offset = 1,
98 .reg_offset = 1,
102 .reg_offset = 1,
106 .reg_offset = 1,
111 .reg_offset = 2,
115 .reg_offset = 2,
[all …]
Dtps65910.c61 .reg_offset = 0,
65 .reg_offset = 0,
69 .reg_offset = 0,
73 .reg_offset = 0,
77 .reg_offset = 0,
81 .reg_offset = 0,
85 .reg_offset = 0,
89 .reg_offset = 0,
95 .reg_offset = 1,
99 .reg_offset = 1,
[all …]
Dmax8907.c119 { .reg_offset = 0, .mask = 1 << 0, },
120 { .reg_offset = 0, .mask = 1 << 1, },
121 { .reg_offset = 0, .mask = 1 << 2, },
122 { .reg_offset = 1, .mask = 1 << 0, },
123 { .reg_offset = 1, .mask = 1 << 1, },
124 { .reg_offset = 1, .mask = 1 << 2, },
125 { .reg_offset = 1, .mask = 1 << 3, },
126 { .reg_offset = 1, .mask = 1 << 4, },
127 { .reg_offset = 1, .mask = 1 << 5, },
128 { .reg_offset = 1, .mask = 1 << 6, },
[all …]
Dwm8994-irq.c33 .reg_offset = 1,
37 .reg_offset = 1,
41 .reg_offset = 1,
45 .reg_offset = 1,
49 .reg_offset = 1,
53 .reg_offset = 1,
57 .reg_offset = 1,
61 .reg_offset = 1,
65 .reg_offset = 1,
69 .reg_offset = 1,
[all …]
Das3722.c112 .reg_offset = 1,
116 .reg_offset = 1,
120 .reg_offset = 1,
124 .reg_offset = 1,
128 .reg_offset = 1,
132 .reg_offset = 1,
136 .reg_offset = 1,
140 .reg_offset = 1,
146 .reg_offset = 2,
150 .reg_offset = 2,
[all …]
Dmax14577.c203 { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
204 { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
205 { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
207 { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
208 { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
209 { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
210 { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
211 { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
213 { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
214 { .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
[all …]
Dda9150-core.c169 .reg_offset = 0,
173 .reg_offset = 0,
177 .reg_offset = 0,
181 .reg_offset = 0,
185 .reg_offset = 0,
189 .reg_offset = 1,
193 .reg_offset = 1,
197 .reg_offset = 1,
201 .reg_offset = 1,
205 .reg_offset = 1,
[all …]
Dwm5102-tables.c127 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
128 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
129 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
130 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
133 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
136 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
139 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
143 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
146 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
149 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
[all …]
Dwm8997-tables.c63 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
64 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
65 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
66 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
69 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1
72 .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1
75 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
78 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
81 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
84 .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
[all …]
Dmax77686.c137 { .reg_offset = 0, .mask = MAX77686_INT1_PWRONF_MSK, },
138 { .reg_offset = 0, .mask = MAX77686_INT1_PWRONR_MSK, },
139 { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBF_MSK, },
140 { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBR_MSK, },
141 { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBF_MSK, },
142 { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBR_MSK, },
143 { .reg_offset = 0, .mask = MAX77686_INT1_ONKEY1S_MSK, },
144 { .reg_offset = 0, .mask = MAX77686_INT1_MRSTB_MSK, },
146 { .reg_offset = 1, .mask = MAX77686_INT2_140C_MSK, },
147 { .reg_offset = 1, .mask = MAX77686_INT2_120C_MSK, },
[all …]
Dmax77693.c126 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, },
127 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, },
128 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_ERR, },
129 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, },
131 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, },
132 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGDETREUN, },
133 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, },
134 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, },
135 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, },
136 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VIDRM, },
[all …]
Drk808.c101 .reg_offset = 0,
105 .reg_offset = 0,
109 .reg_offset = 0,
113 .reg_offset = 0,
117 .reg_offset = 0,
121 .reg_offset = 0,
125 .reg_offset = 0,
131 .reg_offset = 1,
135 .reg_offset = 1,
Dtps65090.c101 .reg_offset = 1,
105 .reg_offset = 1,
109 .reg_offset = 1,
113 .reg_offset = 1,
117 .reg_offset = 1,
121 .reg_offset = 1,
125 .reg_offset = 1,
129 .reg_offset = 1,
D88pm800.c189 .reg_offset = 1,
193 .reg_offset = 1,
197 .reg_offset = 1,
201 .reg_offset = 1,
206 .reg_offset = 2,
210 .reg_offset = 2,
214 .reg_offset = 2,
218 .reg_offset = 2,
222 .reg_offset = 2,
227 .reg_offset = 3,
[all …]
D88pm805.c111 .reg_offset = 1,
115 .reg_offset = 1,
119 .reg_offset = 1,
123 .reg_offset = 1,
127 .reg_offset = 1,
131 .reg_offset = 1,
Dtps65218.c172 .reg_offset = 1,
176 .reg_offset = 1,
180 .reg_offset = 1,
184 .reg_offset = 1,
188 .reg_offset = 1,
192 .reg_offset = 1,
Dda9055-core.c227 .reg_offset = 0,
231 .reg_offset = 0,
235 .reg_offset = 0,
239 .reg_offset = 0,
243 .reg_offset = 1,
Dmax77843.c57 { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSUVLO_INT, },
58 { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSOVLO_INT, },
59 { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TSHDN_INT, },
60 { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TM_INT, },
Dtwl6040.c600 { .reg_offset = 0, .mask = TWL6040_THINT, },
601 { .reg_offset = 0, .mask = TWL6040_PLUGINT | TWL6040_UNPLUGINT, },
602 { .reg_offset = 0, .mask = TWL6040_HOOKINT, },
603 { .reg_offset = 0, .mask = TWL6040_HFINT, },
604 { .reg_offset = 0, .mask = TWL6040_VIBINT, },
605 { .reg_offset = 0, .mask = TWL6040_READYINT, },
Daxp20x.c142 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
Dmc13xxx-core.c428 mc13xxx->irqs[i].reg_offset = i / MC13XXX_IRQ_PER_REG; in mc13xxx_common_init()
Dtps80031.c85 .reg_offset = (TPS80031_INT_MSK_LINE_##_reg) - \
/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_i2c.c213 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_wait_hw_status() local
223 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); in gmbus_wait_hw_status()
229 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); in gmbus_wait_hw_status()
237 I915_WRITE(GMBUS4 + reg_offset, 0); in gmbus_wait_hw_status()
250 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_wait_idle() local
252 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) in gmbus_wait_idle()
258 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); in gmbus_wait_idle()
263 I915_WRITE(GMBUS4 + reg_offset, 0); in gmbus_wait_idle()
277 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_read_chunk() local
279 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer_read_chunk()
[all …]
/linux-4.1.27/drivers/gpu/drm/gma500/
Dintel_gmbus.c253 int i, reg_offset; in gmbus_xfer() local
259 reg_offset = 0; in gmbus_xfer()
261 GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0); in gmbus_xfer()
268 GMBUS_REG_WRITE(GMBUS1 + reg_offset, in gmbus_xfer()
274 GMBUS_REG_READ(GMBUS2+reg_offset); in gmbus_xfer()
278 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & in gmbus_xfer()
281 if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) in gmbus_xfer()
284 val = GMBUS_REG_READ(GMBUS3 + reg_offset); in gmbus_xfer()
298 GMBUS_REG_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer()
299 GMBUS_REG_WRITE(GMBUS1 + reg_offset, in gmbus_xfer()
[all …]
/linux-4.1.27/drivers/gpu/drm/radeon/
Dcik_sdma.c252 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
261 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_stop()
263 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop()
264 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
266 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
267 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); in cik_sdma_gfx_stop()
306 uint32_t reg_offset, value; in cik_sdma_ctx_switch_enable() local
311 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
313 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
314 value = RREG32(SDMA0_CNTL + reg_offset); in cik_sdma_ctx_switch_enable()
[all …]
Dni_dma.c192 u32 reg_offset, wb_offset; in cayman_dma_resume() local
198 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
202 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
206 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
207 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
215 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
218 WREG32(DMA_RB_RPTR + reg_offset, 0); in cayman_dma_resume()
219 WREG32(DMA_RB_WPTR + reg_offset, 0); in cayman_dma_resume()
222 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, in cayman_dma_resume()
224 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, in cayman_dma_resume()
[all …]
Dcik.c2323 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; in cik_tiling_mode_table_init() local
2346 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { in cik_tiling_mode_table_init()
2347 switch (reg_offset) { in cik_tiling_mode_table_init()
2472 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2473 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2475 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in cik_tiling_mode_table_init()
2476 switch (reg_offset) { in cik_tiling_mode_table_init()
2565 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2566 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2569 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { in cik_tiling_mode_table_init()
[all …]
Drv770_dpm.h282 u16 reg_offset, u32 value);
Dsi.c2443 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; in si_tiling_mode_table_init() local
2460 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { in si_tiling_mode_table_init()
2461 switch (reg_offset) { in si_tiling_mode_table_init()
2696 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden; in si_tiling_mode_table_init()
2697 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in si_tiling_mode_table_init()
2702 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { in si_tiling_mode_table_init()
2703 switch (reg_offset) { in si_tiling_mode_table_init()
2938 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden; in si_tiling_mode_table_init()
2939 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in si_tiling_mode_table_init()
Drv770_dpm.c236 u16 reg_offset, u32 *value)
241 pi->soft_regs_start + reg_offset,
247 u16 reg_offset, u32 value) in rv770_write_smc_soft_register() argument
252 pi->soft_regs_start + reg_offset, in rv770_write_smc_soft_register()
Dkv_dpm.c1334 u16 reg_offset, u32 value)
1338 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1343 u16 reg_offset, u32 *value)
1347 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
Dsi_dpm.c1751 u16 reg_offset, u32 value);
3123 u16 reg_offset, u32 *value)
3128 si_pi->soft_regs_start + reg_offset, value,
3134 u16 reg_offset, u32 value) in si_write_smc_soft_register() argument
3139 si_pi->soft_regs_start + reg_offset, in si_write_smc_soft_register()
Dci_dpm.c1273 u16 reg_offset, u32 *value)
1278 pi->soft_regs_start + reg_offset,
1284 u16 reg_offset, u32 value) in ci_write_smc_soft_register() argument
1289 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
/linux-4.1.27/arch/tile/kernel/
Dpci_gx.c217 unsigned int reg_offset; in tile_pcie_open() local
224 reg_offset = in tile_pcie_open()
232 __gxio_mmio_read(context->mmio_base_mac + reg_offset); in tile_pcie_open()
313 unsigned int reg_offset; in trio_handle_level_irq() local
322 reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS << in trio_handle_level_irq()
330 __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask); in trio_handle_level_irq()
395 unsigned int reg_offset; in strapped_for_rc() local
398 reg_offset = in strapped_for_rc()
405 __gxio_mmio_read(trio_context->mmio_base_mac + reg_offset); in strapped_for_rc()
562 unsigned int reg_offset; in fixup_read_and_payload_sizes() local
[all …]
/linux-4.1.27/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-socfpga.c44 u32 reg_offset; member
85 u32 reg_offset, reg_shift; in socfpga_dwmac_parse_data() local
107 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset); in socfpga_dwmac_parse_data()
133 dwmac->reg_offset = reg_offset; in socfpga_dwmac_parse_data()
145 u32 reg_offset = dwmac->reg_offset; in socfpga_dwmac_setup() local
170 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); in socfpga_dwmac_setup()
174 regmap_write(sys_mgr_base_addr, reg_offset, ctrl); in socfpga_dwmac_setup()
/linux-4.1.27/arch/arm/mach-omap2/
Dmux.c93 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { in omap_mux_write_array()
95 board_mux->reg_offset); in omap_mux_write_array()
136 old_mode = omap_mux_read(partition, gpio_mux->reg_offset); in _omap_mux_init_gpio()
141 omap_mux_write(partition, mux_mode, gpio_mux->reg_offset); in _omap_mux_init_gpio()
253 old_mode = omap_mux_read(partition, mux->reg_offset); in omap_mux_init_signal()
257 omap_mux_write(partition, mux_mode, mux->reg_offset); in omap_mux_init_signal()
383 val = omap_mux_read(pad->partition, pad->mux->reg_offset); in omap_hwmod_mux_scan_wakeups()
443 pad->mux->reg_offset); in omap_hwmod_mux()
458 pad->mux->reg_offset); in omap_hwmod_mux()
493 pad->mux->reg_offset); in omap_hwmod_mux()
[all …]
Dmux.h132 u16 reg_offset; member
148 u16 reg_offset; member
158 u16 reg_offset; member
Dboard-rx51.c86 { .reg_offset = OMAP_MUX_TERMINATOR },
Dserial.c151 tx_mode = omap_mux_read(tx_partition, tx_mux->reg_offset); in omap_serial_check_wakeup()
152 rx_mode = omap_mux_read(rx_partition, rx_mux->reg_offset); in omap_serial_check_wakeup()
Dmux34xx.c19 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
28 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
36 .reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
699 { .reg_offset = OMAP_MUX_TERMINATOR },
707 { .reg_offset = OMAP_MUX_TERMINATOR },
924 { .reg_offset = OMAP_MUX_TERMINATOR },
1068 { .reg_offset = OMAP_MUX_TERMINATOR },
1262 { .reg_offset = OMAP_MUX_TERMINATOR },
1381 { .reg_offset = OMAP_MUX_TERMINATOR },
1593 { .reg_offset = OMAP_MUX_TERMINATOR },
[all …]
Dboard-omap3logic.c199 { .reg_offset = OMAP_MUX_TERMINATOR },
Dmux34xx.h14 .reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
Dboard-ldp.c359 { .reg_offset = OMAP_MUX_TERMINATOR },
Dboard-overo.c482 { .reg_offset = OMAP_MUX_TERMINATOR },
Dboard-omap3beagle.c488 { .reg_offset = OMAP_MUX_TERMINATOR },
Dhsmmc.c255 mmc->reg_offset = 0; in omap_hsmmc_pdata_init()
Dboard-rx51-peripherals.c462 { .reg_offset = OMAP_MUX_TERMINATOR },
476 { .reg_offset = OMAP_MUX_TERMINATOR },
Dboard-omap3pandora.c591 { .reg_offset = OMAP_MUX_TERMINATOR },
Dboard-cm-t35.c671 { .reg_offset = OMAP_MUX_TERMINATOR },
/linux-4.1.27/arch/powerpc/boot/
Dns16550.c58 u32 reg_offset; in ns16550_console_init() local
63 n = getprop(devp, "reg-offset", &reg_offset, sizeof(reg_offset)); in ns16550_console_init()
64 if (n == sizeof(reg_offset)) in ns16550_console_init()
65 reg_base += reg_offset; in ns16550_console_init()
Dvirtex.c31 u32 reg_shift, reg_offset, clk, spd; in virtex_ns16550_console_init() local
38 n = getprop(devp, "reg-offset", &reg_offset, sizeof(reg_offset)); in virtex_ns16550_console_init()
39 if (n == sizeof(reg_offset)) in virtex_ns16550_console_init()
40 reg_base += reg_offset; in virtex_ns16550_console_init()
/linux-4.1.27/drivers/phy/
Dphy-rockchip-usb.c40 unsigned int reg_offset; member
49 return regmap_write(phy->reg_base, phy->reg_offset, in rockchip_usb_phy_power()
100 unsigned int reg_offset; in rockchip_usb_phy_probe() local
113 if (of_property_read_u32(child, "reg", &reg_offset)) { in rockchip_usb_phy_probe()
119 rk_phy->reg_offset = reg_offset; in rockchip_usb_phy_probe()
Dphy-qcom-ufs-i.h47 .reg_offset = reg, \
69 u32 reg_offset; member
Dphy-qcom-ufs.c49 ufs_qcom_phy->mmio + tbl_A[i].reg_offset); in ufs_qcom_phy_calibrate()
67 ufs_qcom_phy->mmio + tbl_B[i].reg_offset); in ufs_qcom_phy_calibrate()
/linux-4.1.27/drivers/staging/comedi/drivers/
Dcomedi_8254.c135 unsigned int reg_offset = (reg * i8254->iosize) << i8254->regshift; in __i8254_read() local
142 val = readb(i8254->mmio + reg_offset); in __i8254_read()
144 val = inb(i8254->iobase + reg_offset); in __i8254_read()
148 val = readw(i8254->mmio + reg_offset); in __i8254_read()
150 val = inw(i8254->iobase + reg_offset); in __i8254_read()
154 val = readl(i8254->mmio + reg_offset); in __i8254_read()
156 val = inl(i8254->iobase + reg_offset); in __i8254_read()
165 unsigned int reg_offset = (reg * i8254->iosize) << i8254->regshift; in __i8254_write() local
171 writeb(val, i8254->mmio + reg_offset); in __i8254_write()
173 outb(val, i8254->iobase + reg_offset); in __i8254_write()
[all …]
/linux-4.1.27/drivers/net/ethernet/natsemi/
Dmacsonic.c70 + lp->reg_offset))
72 + lp->reg_offset))
358 lp->reg_offset = 0; in mac_onboard_sonic_probe()
367 lp->reg_offset = 2; in mac_onboard_sonic_probe()
376 lp->reg_offset = 0; in mac_onboard_sonic_probe()
381 lp->reg_offset = 2; in mac_onboard_sonic_probe()
387 dev_name(lp->device), sr, lp->dma_bitmode?32:16, lp->reg_offset); in mac_onboard_sonic_probe()
464 int reg_offset, dma_bitmode; in mac_nubus_sonic_probe() local
489 reg_offset = 2; in mac_nubus_sonic_probe()
496 reg_offset = 0; in mac_nubus_sonic_probe()
[all …]
Dsonic.h294 int reg_offset; member
/linux-4.1.27/drivers/extcon/
Dextcon-rt8973a.c188 { .reg_offset = 0, .mask = RT8973A_INT1_ATTACH_MASK, },
189 { .reg_offset = 0, .mask = RT8973A_INT1_DETACH_MASK, },
190 { .reg_offset = 0, .mask = RT8973A_INT1_CHGDET_MASK, },
191 { .reg_offset = 0, .mask = RT8973A_INT1_DCD_T_MASK, },
192 { .reg_offset = 0, .mask = RT8973A_INT1_OVP_MASK, },
193 { .reg_offset = 0, .mask = RT8973A_INT1_CONNECT_MASK, },
194 { .reg_offset = 0, .mask = RT8973A_INT1_ADC_CHG_MASK, },
195 { .reg_offset = 0, .mask = RT8973A_INT1_OTP_MASK, },
198 { .reg_offset = 1, .mask = RT8973A_INT2_UVLOT_MASK,},
199 { .reg_offset = 1, .mask = RT8973A_INT2_POR_MASK, },
[all …]
Dextcon-sm5502.c178 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_ATTACH_MASK, },
179 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_DETACH_MASK, },
180 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_KP_MASK, },
181 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKP_MASK, },
182 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKR_MASK, },
183 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_EVENT_MASK, },
184 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OCP_EVENT_MASK, },
185 { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_OCP_DIS_MASK, },
188 { .reg_offset = 1, .mask = SM5502_IRQ_INT2_VBUS_DET_MASK,},
189 { .reg_offset = 1, .mask = SM5502_IRQ_INT2_REV_ACCE_MASK, },
[all …]
Dextcon-max77843.c186 { .reg_offset = 0, .mask = MAX77843_MUIC_ADC, },
187 { .reg_offset = 0, .mask = MAX77843_MUIC_ADCERROR, },
188 { .reg_offset = 0, .mask = MAX77843_MUIC_ADC1K, },
191 { .reg_offset = 1, .mask = MAX77843_MUIC_CHGTYP, },
192 { .reg_offset = 1, .mask = MAX77843_MUIC_CHGDETRUN, },
193 { .reg_offset = 1, .mask = MAX77843_MUIC_DCDTMR, },
194 { .reg_offset = 1, .mask = MAX77843_MUIC_DXOVP, },
195 { .reg_offset = 1, .mask = MAX77843_MUIC_VBVOLT, },
198 { .reg_offset = 2, .mask = MAX77843_MUIC_VBADC, },
199 { .reg_offset = 2, .mask = MAX77843_MUIC_VDNMON, },
[all …]
/linux-4.1.27/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_ethtool.c465 int reg_offset; in sxgbe_get_regs() local
472 for (reg_offset = START_MAC_REG_OFFSET; in sxgbe_get_regs()
473 reg_offset <= MAX_MAC_REG_OFFSET; reg_offset += 4) { in sxgbe_get_regs()
474 reg_space[reg_ix] = readl(ioaddr + reg_offset); in sxgbe_get_regs()
479 for (reg_offset = START_MTL_REG_OFFSET; in sxgbe_get_regs()
480 reg_offset <= MAX_MTL_REG_OFFSET; reg_offset += 4) { in sxgbe_get_regs()
481 reg_space[reg_ix] = readl(ioaddr + reg_offset); in sxgbe_get_regs()
486 for (reg_offset = START_DMA_REG_OFFSET; in sxgbe_get_regs()
487 reg_offset <= MAX_DMA_REG_OFFSET; reg_offset += 4) { in sxgbe_get_regs()
488 reg_space[reg_ix] = readl(ioaddr + reg_offset); in sxgbe_get_regs()
/linux-4.1.27/arch/powerpc/include/asm/
Dtsi108.h107 static inline u32 tsi108_read_reg(u32 reg_offset) in tsi108_read_reg() argument
109 return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset)); in tsi108_read_reg()
112 static inline void tsi108_write_reg(u32 reg_offset, u32 val) in tsi108_write_reg() argument
114 out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val); in tsi108_write_reg()
/linux-4.1.27/drivers/pci/host/
Dpci-keystone-dw.c66 static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset, in update_reg_offset_bit_pos() argument
69 *reg_offset = offset % 8; in update_reg_offset_bit_pos()
105 u32 offset, reg_offset, bit_pos; in ks_dw_pcie_msi_irq_ack() local
115 update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos); in ks_dw_pcie_msi_irq_ack()
118 ks_pcie->va_app_base + MSI0_IRQ_STATUS + (reg_offset << 4)); in ks_dw_pcie_msi_irq_ack()
119 writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI); in ks_dw_pcie_msi_irq_ack()
124 u32 reg_offset, bit_pos; in ks_dw_pcie_msi_set_irq() local
127 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos); in ks_dw_pcie_msi_set_irq()
129 ks_pcie->va_app_base + MSI0_IRQ_ENABLE_SET + (reg_offset << 4)); in ks_dw_pcie_msi_set_irq()
134 u32 reg_offset, bit_pos; in ks_dw_pcie_msi_clear_irq() local
[all …]
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
Dhtc_drv_init.c230 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset) in ath9k_regread() argument
235 __be32 val, reg = cpu_to_be32(reg_offset); in ath9k_regread()
244 reg_offset, r); in ath9k_regread()
298 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) in ath9k_regwrite_single() argument
304 cpu_to_be32(reg_offset), in ath9k_regwrite_single()
315 reg_offset, r); in ath9k_regwrite_single()
319 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) in ath9k_regwrite_buffer() argument
329 cpu_to_be32(reg_offset); in ath9k_regwrite_buffer()
342 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset) in ath9k_regwrite() argument
349 ath9k_regwrite_buffer(hw_priv, val, reg_offset); in ath9k_regwrite()
[all …]
Dinit.c116 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) in ath9k_iowrite32() argument
125 iowrite32(val, sc->mem + reg_offset); in ath9k_iowrite32()
128 iowrite32(val, sc->mem + reg_offset); in ath9k_iowrite32()
131 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) in ath9k_ioread32() argument
141 val = ioread32(sc->mem + reg_offset); in ath9k_ioread32()
144 val = ioread32(sc->mem + reg_offset); in ath9k_ioread32()
158 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, in __ath9k_reg_rmw() argument
163 val = ioread32(sc->mem + reg_offset); in __ath9k_reg_rmw()
166 iowrite32(val, sc->mem + reg_offset); in __ath9k_reg_rmw()
171 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) in ath9k_reg_rmw() argument
[all …]
/linux-4.1.27/drivers/gpio/
Dgpio-bcm-kona.c131 u32 val, reg_offset; in bcm_kona_gpio_set() local
146 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); in bcm_kona_gpio_set()
148 val = readl(reg_base + reg_offset); in bcm_kona_gpio_set()
150 writel(val, reg_base + reg_offset); in bcm_kona_gpio_set()
162 u32 val, reg_offset; in bcm_kona_gpio_get() local
174 reg_offset = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ? in bcm_kona_gpio_get()
176 val = readl(reg_base + reg_offset); in bcm_kona_gpio_get()
227 u32 val, reg_offset; in bcm_kona_gpio_direction_output() local
238 reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); in bcm_kona_gpio_direction_output()
240 val = readl(reg_base + reg_offset); in bcm_kona_gpio_direction_output()
[all …]
Dgpio-lynxpoint.c101 int reg_offset; in lp_gpio_reg() local
105 reg_offset = offset * 8; in lp_gpio_reg()
108 reg_offset = (offset / 32) * 4; in lp_gpio_reg()
110 return lg->reg_base + reg + reg_offset; in lp_gpio_reg()
Dgpio-zynq.c185 unsigned int reg_offset, bank_num, bank_pin_num; in zynq_gpio_set_value() local
193 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); in zynq_gpio_set_value()
195 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); in zynq_gpio_set_value()
206 writel_relaxed(state, gpio->base_addr + reg_offset); in zynq_gpio_set_value()
/linux-4.1.27/arch/m32r/kernel/
Dptrace.c62 static int reg_offset[] = { variable
227 reg2 = get_stack_long(child, reg_offset[regno2]); in check_condition_src()
231 reg1 = get_stack_long(child, reg_offset[regno1]); in check_condition_src()
234 reg1 = get_stack_long(child, reg_offset[regno1]); in check_condition_src()
328 reg_offset[regno]); in compute_next_pc_for_16bit_insn()
336 reg_offset[regno]); in compute_next_pc_for_16bit_insn()
345 reg_offset[regno]); in compute_next_pc_for_16bit_insn()
/linux-4.1.27/drivers/net/ethernet/renesas/
Dsh_eth.h502 const u16 *reg_offset; member
555 u16 offset = mdp->reg_offset[enum_index]; in sh_eth_write()
566 u16 offset = mdp->reg_offset[enum_index]; in sh_eth_read()
577 return mdp->tsu_addr + mdp->reg_offset[enum_index]; in sh_eth_tsu_get_offset()
583 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]); in sh_eth_tsu_write()
588 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]); in sh_eth_tsu_read()
Dsh_eth.c409 return mdp->reg_offset == sh_eth_offset_gigabit; in sh_eth_is_gether()
414 return mdp->reg_offset == sh_eth_offset_fast_rz; in sh_eth_is_rz_fast_ether()
1561 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) { in sh_eth_rx()
1983 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ in __sh_eth_get_regs()
2091 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) { in __sh_eth_get_regs()
2102 mdp->reg_offset[TSU_ADRH0] + in __sh_eth_get_regs()
2540 void *reg_offset; in sh_eth_tsu_enable_cam_entry_post() local
2542 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); in sh_eth_tsu_enable_cam_entry_post()
2543 tmp = ioread32(reg_offset); in sh_eth_tsu_enable_cam_entry_post()
2544 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); in sh_eth_tsu_enable_cam_entry_post()
[all …]
/linux-4.1.27/drivers/media/platform/omap3isp/
Disp.h289 u32 reg_offset) in isp_reg_readl() argument
291 return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset); in isp_reg_readl()
303 enum isp_mem_resources isp_mmio_range, u32 reg_offset) in isp_reg_writel() argument
305 __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset); in isp_reg_writel()
/linux-4.1.27/drivers/clocksource/
Dtimer-atmel-pit.c62 static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset) in pit_read() argument
64 return readl_relaxed(base + reg_offset); in pit_read()
67 static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value) in pit_write() argument
69 writel_relaxed(value, base + reg_offset); in pit_write()
/linux-4.1.27/drivers/base/regmap/
Dregmap-irq.c148 d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask; in regmap_irq_enable()
157 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; in regmap_irq_disable()
168 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
173 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
285 if (data->status_buf[chip->irqs[i].reg_offset / in regmap_irq_thread()
354 if (chip->irqs[i].reg_offset % map->reg_stride) in regmap_add_irq_chip()
356 if (chip->irqs[i].reg_offset / map->reg_stride >= in regmap_add_irq_chip()
419 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride] in regmap_add_irq_chip()
Dregmap-debugfs.c93 unsigned int reg_offset; in regmap_debugfs_get_dump_start() local
157 reg_offset = fpos_offset / map->debugfs_tot_len; in regmap_debugfs_get_dump_start()
158 *pos = c->min + (reg_offset * map->debugfs_tot_len); in regmap_debugfs_get_dump_start()
160 return c->base_reg + (reg_offset * map->reg_stride); in regmap_debugfs_get_dump_start()
/linux-4.1.27/drivers/pinctrl/freescale/
Dpinctrl-imx1-core.c92 u32 value, u32 reg_offset) in imx1_write_2bit() argument
94 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; in imx1_write_2bit()
119 u32 value, u32 reg_offset) in imx1_write_bit() argument
121 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; in imx1_write_bit()
139 u32 reg_offset) in imx1_read_2bit() argument
141 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; in imx1_read_2bit()
152 u32 reg_offset) in imx1_read_bit() argument
154 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset; in imx1_read_bit()
/linux-4.1.27/drivers/gpu/host1x/hw/
Dsyncpt_hw.c83 u32 reg_offset = sp->id / 32; in syncpt_cpu_incr() local
89 HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset)); in syncpt_cpu_incr()
/linux-4.1.27/drivers/power/
Dsbs-battery.c361 int reg_offset, enum power_supply_property psp, in sbs_get_battery_property() argument
367 ret = sbs_read_word_data(client, sbs_data[reg_offset].addr); in sbs_get_battery_property()
372 if (sbs_data[reg_offset].min_value < 0) in sbs_get_battery_property()
375 if (ret >= sbs_data[reg_offset].min_value && in sbs_get_battery_property()
376 ret <= sbs_data[reg_offset].max_value) { in sbs_get_battery_property()
408 int reg_offset, enum power_supply_property psp, char *val) in sbs_get_battery_string_property() argument
412 ret = sbs_read_string_data(client, sbs_data[reg_offset].addr, val); in sbs_get_battery_string_property()
493 int reg_offset, enum power_supply_property psp, in sbs_get_battery_capacity() argument
506 ret = sbs_read_word_data(client, sbs_data[reg_offset].addr); in sbs_get_battery_capacity()
/linux-4.1.27/arch/x86/kernel/
Dpmc_atom.c104 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset) in pmc_reg_read() argument
106 return readl(pmc->regmap + reg_offset); in pmc_reg_read()
109 static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val) in pmc_reg_write() argument
111 writel(val, pmc->regmap + reg_offset); in pmc_reg_write()
/linux-4.1.27/drivers/input/keyboard/
Domap4-keypad.c80 u32 reg_offset; member
91 keypad_data->reg_offset + offset); in kbd_readl()
97 keypad_data->base + keypad_data->reg_offset + offset); in kbd_writel()
301 keypad_data->reg_offset = 0x00; in omap4_keypad_probe()
305 keypad_data->reg_offset = 0x10; in omap4_keypad_probe()
/linux-4.1.27/drivers/net/ethernet/intel/ixgbe/
Dixgbe_mbx.c299 u32 reg_offset = (vf_number < 32) ? 0 : 1; in ixgbe_check_for_rst_pf() local
305 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset)); in ixgbe_check_for_rst_pf()
310 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset)); in ixgbe_check_for_rst_pf()
317 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift)); in ixgbe_check_for_rst_pf()
Dixgbe_sriov.c426 u32 reg_offset, vf_shift, vfre; in ixgbe_set_vf_lpe() local
459 reg_offset = vf / 32; in ixgbe_set_vf_lpe()
462 vfre = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); in ixgbe_set_vf_lpe()
467 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), vfre); in ixgbe_set_vf_lpe()
656 u32 reg, reg_offset, vf_shift; in ixgbe_vf_reset_msg() local
672 reg_offset = vf / 32; in ixgbe_vf_reset_msg()
675 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset)); in ixgbe_vf_reset_msg()
677 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg); in ixgbe_vf_reset_msg()
683 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); in ixgbe_vf_reset_msg()
702 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg); in ixgbe_vf_reset_msg()
[all …]
Dixgbe_main.c1235 u16 reg_offset; in ixgbe_update_tx_dca() local
1239 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1243 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1260 IXGBE_WRITE_REG(hw, reg_offset, txctrl); in ixgbe_update_tx_dca()
3593 u32 reg_offset, vf_shift; in ixgbe_configure_virtualization() local
3608 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; in ixgbe_configure_virtualization()
3611 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); in ixgbe_configure_virtualization()
3612 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); in ixgbe_configure_virtualization()
3613 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); in ixgbe_configure_virtualization()
3614 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); in ixgbe_configure_virtualization()
/linux-4.1.27/include/linux/
Dirq.h856 u32 val, int reg_offset) in irq_reg_writel() argument
859 gc->reg_writel(val, gc->reg_base + reg_offset); in irq_reg_writel()
861 writel(val, gc->reg_base + reg_offset); in irq_reg_writel()
865 int reg_offset) in irq_reg_readl() argument
868 return gc->reg_readl(gc->reg_base + reg_offset); in irq_reg_readl()
870 return readl(gc->reg_base + reg_offset); in irq_reg_readl()
Dregmap.h516 unsigned int reg_offset; member
/linux-4.1.27/sound/pci/
Dintel8x0m.c170 unsigned long reg_offset; /* offset to bmaddr */ member
399 unsigned long port = ichdev->reg_offset; in snd_intel8x0m_setup_periods()
449 unsigned long port = ichdev->reg_offset; in snd_intel8x0m_update()
541 unsigned long port = ichdev->reg_offset; in snd_intel8x0m_pcm_trigger()
588 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; in snd_intel8x0m_pcm_pointer()
983 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); in snd_intel8x0m_chip_init()
986 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); in snd_intel8x0m_chip_init()
989 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); in snd_intel8x0m_chip_init()
1001 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); in snd_intel8x0m_free()
1004 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); in snd_intel8x0m_free()
[all …]
Dintel8x0.c357 unsigned long reg_offset; /* offset to bmaddr */ member
685 unsigned long port = ichdev->reg_offset; in snd_intel8x0_setup_periods()
756 unsigned long port = ichdev->reg_offset; in snd_intel8x0_update()
852 unsigned long port = ichdev->reg_offset; in snd_intel8x0_pcm_trigger()
889 unsigned long port = ichdev->reg_offset; in snd_intel8x0_ali_trigger()
1078 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); in snd_intel8x0_pcm_pointer()
1079 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); in snd_intel8x0_pcm_pointer()
1085 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV)) in snd_intel8x0_pcm_pointer()
1096 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) in snd_intel8x0_pcm_pointer()
2592 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); in snd_intel8x0_chip_init()
[all …]
Dvia82xx.c325 unsigned int reg_offset; member
986 ((viadev->reg_offset & 0x10) == 0 ? VIA_REG_TYPE_INT_LSAMPLE : 0) | in via686_setup_format()
1051 if (chip->spdif_on && viadev->reg_offset == 0x30) in snd_via8233_playback_prepare()
1062 outb(chip->playback_volume[viadev->reg_offset / 0x10][0], in snd_via8233_playback_prepare()
1064 outb(chip->playback_volume[viadev->reg_offset / 0x10][1], in snd_via8233_playback_prepare()
1192 if (chip->spdif_on && viadev->reg_offset == 0x30) { in snd_via82xx_pcm_open()
1196 } else if (chip->dxs_fixed && viadev->reg_offset < 0x40) { in snd_via82xx_pcm_open()
1200 } else if (chip->dxs_src && viadev->reg_offset < 0x40) { in snd_via82xx_pcm_open()
1263 stream = viadev->reg_offset / 0x10; in snd_via8233_playback_open()
1357 stream = viadev->reg_offset / 0x10; in snd_via8233_playback_close()
[all …]
Dvia82xx_modem.c220 unsigned int reg_offset; member
833 static void init_viadev(struct via82xx_modem *chip, int idx, unsigned int reg_offset, in init_viadev() argument
836 chip->devs[idx].reg_offset = reg_offset; in init_viadev()
838 chip->devs[idx].port = chip->port + reg_offset; in init_viadev()
/linux-4.1.27/drivers/net/wireless/ath/
Dath.h128 unsigned int (*read)(void *, u32 reg_offset);
130 void (*write)(void *, u32 val, u32 reg_offset);
133 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
/linux-4.1.27/drivers/gpu/drm/exynos/
Dexynos_drm_g2d.c586 static enum g2d_reg_type g2d_get_reg_type(int reg_offset) in g2d_get_reg_type() argument
590 switch (reg_offset) { in g2d_get_reg_type()
617 DRM_ERROR("Unknown register offset![%d]\n", reg_offset); in g2d_get_reg_type()
947 int reg_offset; in g2d_check_reg_offset() local
959 reg_offset = cmdlist->data[index] & ~0xfffff000; in g2d_check_reg_offset()
960 if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END) in g2d_check_reg_offset()
962 if (reg_offset % 4) in g2d_check_reg_offset()
965 switch (reg_offset) { in g2d_check_reg_offset()
975 reg_type = g2d_get_reg_type(reg_offset); in g2d_check_reg_offset()
991 reg_type = g2d_get_reg_type(reg_offset); in g2d_check_reg_offset()
[all …]
Dexynos_hdmi.c635 u32 reg_offset, u8 value) in hdmiphy_reg_writeb() argument
641 buffer[0] = reg_offset; in hdmiphy_reg_writeb()
649 writeb(value, hdata->regs_hdmiphy + (reg_offset<<2)); in hdmiphy_reg_writeb()
655 u32 reg_offset, const u8 *buf, u32 len) in hdmiphy_reg_write_buf() argument
657 if ((reg_offset + len) > 32) in hdmiphy_reg_write_buf()
671 ((reg_offset + i)<<2)); in hdmiphy_reg_write_buf()
/linux-4.1.27/drivers/net/ethernet/8390/
Dmac8390.c47 #define EI_SHIFT(x) (ei_local->reg_offset[x])
566 ei_status.reg_offset = back4_offsets; in mac8390_initdev()
575 ei_status.reg_offset = back4_offsets; in mac8390_initdev()
590 ei_status.reg_offset = back4_offsets; in mac8390_initdev()
599 ei_status.reg_offset = fwrd2_offsets; in mac8390_initdev()
610 ei_status.reg_offset = fwrd4_offsets; in mac8390_initdev()
619 ei_status.reg_offset = fwrd4_offsets; in mac8390_initdev()
Dhydra.c33 #define EI_SHIFT(x) (ei_local->reg_offset[x])
166 ei_status.reg_offset = hydra_offsets; in hydra_init()
Dzorro8390.c38 #define EI_SHIFT(x) (ei_local->reg_offset[x])
387 ei_status.reg_offset = zorro8390_offsets; in zorro8390_init()
Dax88796.c56 #define EI_SHIFT(x) (ei_local->reg_offset[(x)])
890 ei_local->reg_offset = ax->plat->reg_offsets; in ax_probe()
892 ei_local->reg_offset = ax->reg_offsets; in ax_probe()
936 ei_local->reg_offset[0x1f] = ax->map2 - ei_local->mem; in ax_probe()
Detherh.c52 #define EI_SHIFT(x) (ei_local->reg_offset[x])
745 ei_local->reg_offset = etherm_regoffsets; in etherh_probe()
748 ei_local->reg_offset = etherh_regoffsets; in etherh_probe()
D8390.h93 u32 *reg_offset; /* Register mapping table */ member
Dmcf8390.c393 ei_local->reg_offset = offsets; in mcf8390_init()
/linux-4.1.27/drivers/xen/xen-pciback/
Dconf_space_header.c367 #define CFG_FIELD_BAR(reg_offset) \ argument
369 .offset = reg_offset, \
378 #define CFG_FIELD_ROM(reg_offset) \ argument
380 .offset = reg_offset, \
/linux-4.1.27/drivers/pinctrl/samsung/
Dpinctrl-s3c64xx.c73 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
78 .reg_offset = { 0x00, 0x04, 0x08, },
83 .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
88 .reg_offset = { 0x00, 0x08, 0x0c, },
93 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
98 .reg_offset = { 0x00, 0x04, 0x08, },
Dpinctrl-samsung.c394 data = readl(reg + type->reg_offset[PINCFG_TYPE_FUNC]); in samsung_pinmux_setup()
398 writel(data, reg + type->reg_offset[PINCFG_TYPE_FUNC]); in samsung_pinmux_setup()
442 cfg_reg = type->reg_offset[cfg_type]; in samsung_pinconf_rw()
540 data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); in samsung_gpio_set()
544 writel(data, reg + type->reg_offset[PINCFG_TYPE_DAT]); in samsung_gpio_set()
559 data = readl(reg + type->reg_offset[PINCFG_TYPE_DAT]); in samsung_gpio_get()
584 type->reg_offset[PINCFG_TYPE_FUNC]; in samsung_gpio_set_direction()
1108 const u8 *offs = bank->type->reg_offset; in samsung_pinctrl_suspend_dev()
1157 const u8 *offs = bank->type->reg_offset; in samsung_pinctrl_resume_dev()
Dpinctrl-samsung.h112 u8 reg_offset[PINCFG_TYPE_NUM]; member
Dpinctrl-exynos.c51 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
184 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_request_resources()
215 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; in exynos_irq_release_resources()
Dpinctrl-s3c24xx.c49 .reg_offset = { 0x00, 0x04, },
54 .reg_offset = { 0x00, 0x04, 0x08, },
/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5_ctl.c57 u32 reg_offset; member
95 (void)ctl->reg_offset; /* TODO use this instead of mdp5_write */ in ctl_write()
104 (void)ctl->reg_offset; /* TODO use this instead of mdp5_write */ in ctl_read()
551 ctl->reg_offset = ctl_cfg->base[c]; in mdp5_ctlm_init()
Dmdp5_plane.c28 uint32_t reg_offset; member
607 enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset) in mdp5_plane_init() argument
629 mdp5_plane->reg_offset = reg_offset; in mdp5_plane_init()
Dmdp5_kms.h232 enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset);
/linux-4.1.27/drivers/net/ethernet/brocade/bna/
Dbna_hw_defs.h82 struct bna_reg_offset reg_offset[] = \
89 reg_offset[(_pcidev)->pci_func].fn_int_status;\
91 reg_offset[(_pcidev)->pci_func].fn_int_mask;\
/linux-4.1.27/include/linux/platform_data/
Dhsmmc-omap.h49 u16 reg_offset; member
Dmmc-omap.h41 u16 reg_offset; member
/linux-4.1.27/sound/soc/sh/rcar/
Dgen.c38 unsigned int reg_offset; member
45 .reg_offset = offset, \
175 regf.reg = conf[i].reg_offset; in _rsnd_gen_regmap_init()
/linux-4.1.27/drivers/clk/bcm/
Dclk-kona.c128 static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset) in __ccu_read() argument
130 return readl(ccu->base + reg_offset); in __ccu_read()
135 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) in __ccu_write() argument
137 writel(reg_val, ccu->base + reg_offset); in __ccu_write()
189 __ccu_wait_bit(struct ccu_data *ccu, u32 reg_offset, u32 bit, bool want) in __ccu_wait_bit() argument
198 val = __ccu_read(ccu, reg_offset); in __ccu_wait_bit()
205 ccu->name, reg_offset, bit, want ? "set" : "clear"); in __ccu_wait_bit()
/linux-4.1.27/drivers/input/touchscreen/
Dedt-ft5x06.c83 int reg_offset; member
590 edt_ft5x06_register_write(tsdata, reg_addr->reg_offset, in edt_ft5x06_work_mode()
873 EDT_GET_PROP(offset, reg_addr->reg_offset); in edt_ft5x06_ts_get_dt_defaults()
888 EDT_ATTR_CHECKSET(offset, reg_addr->reg_offset); in edt_ft5x06_ts_get_defaults()
901 tsdata->offset = edt_ft5x06_register_read(tsdata, reg_addr->reg_offset); in edt_ft5x06_ts_get_parameters()
919 reg_addr->reg_offset = WORK_REGISTER_OFFSET; in edt_ft5x06_ts_set_regs()
927 reg_addr->reg_offset = M09_REGISTER_OFFSET; in edt_ft5x06_ts_set_regs()
/linux-4.1.27/sound/soc/codecs/
Dwm8995.c1801 int reg_offset, ret; in wm8995_set_fll() local
1816 reg_offset = 0; in wm8995_set_fll()
1820 reg_offset = 0x20; in wm8995_set_fll()
1866 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, in wm8995_set_fll()
1871 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset, in wm8995_set_fll()
1875 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); in wm8995_set_fll()
1877 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset, in wm8995_set_fll()
1881 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset, in wm8995_set_fll()
1888 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, in wm8995_set_fll()
Dwm8994.c2134 int reg_offset, ret; in _wm8994_set_fll() local
2142 reg_offset = 0; in _wm8994_set_fll()
2147 reg_offset = 0x20; in _wm8994_set_fll()
2155 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset); in _wm8994_set_fll()
2211 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, in _wm8994_set_fll()
2217 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, in _wm8994_set_fll()
2224 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, in _wm8994_set_fll()
2228 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset, in _wm8994_set_fll()
2231 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, in _wm8994_set_fll()
2236 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset, in _wm8994_set_fll()
[all …]
Drt5677.c4959 .reg_offset = 0,
4963 .reg_offset = 0,
4967 .reg_offset = 0,
/linux-4.1.27/drivers/net/ethernet/broadcom/
Dbcmsysport.h601 .reg_offset = ofs, \
609 .reg_offset = ofs, \
618 u16 reg_offset; member
Dbcmsysport.c358 val = rxchk_readl(priv, s->reg_offset); in bcm_sysport_update_mib_counters()
360 rxchk_writel(priv, 0, s->reg_offset); in bcm_sysport_update_mib_counters()
363 val = rbuf_readl(priv, s->reg_offset); in bcm_sysport_update_mib_counters()
365 rbuf_writel(priv, 0, s->reg_offset); in bcm_sysport_update_mib_counters()
/linux-4.1.27/drivers/net/wireless/mwifiex/
Ddebugfs.c454 u32 reg_type = 0, reg_offset = 0, reg_value = UINT_MAX; in mwifiex_regrdwr_write() local
465 sscanf(buf, "%u %x %x", &reg_type, &reg_offset, &reg_value); in mwifiex_regrdwr_write()
467 if (reg_type == 0 || reg_offset == 0) { in mwifiex_regrdwr_write()
472 saved_reg_offset = reg_offset; in mwifiex_regrdwr_write()
Dsta_ioctl.c1202 u32 reg_offset, u32 reg_value) in mwifiex_reg_write() argument
1207 reg_rw.offset = cpu_to_le32(reg_offset); in mwifiex_reg_write()
1221 u32 reg_offset, u32 *value) in mwifiex_reg_read() argument
1227 reg_rw.offset = cpu_to_le32(reg_offset); in mwifiex_reg_read()
Dmain.h1296 u32 reg_offset, u32 reg_value);
1299 u32 reg_offset, u32 *value);
/linux-4.1.27/drivers/net/ethernet/marvell/
Dmvneta.c1081 unsigned int reg_offset; in mvneta_set_ucast_addr() local
1090 reg_offset = last_nibble % 4; in mvneta_set_ucast_addr()
1096 unicast_reg &= ~(0xff << (8 * reg_offset)); in mvneta_set_ucast_addr()
1098 unicast_reg &= ~(0xff << (8 * reg_offset)); in mvneta_set_ucast_addr()
1099 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); in mvneta_set_ucast_addr()
1902 unsigned int reg_offset; in mvneta_set_special_mcast_addr() local
1907 reg_offset = last_byte % 4; in mvneta_set_special_mcast_addr()
1913 smc_table_reg &= ~(0xff << (8 * reg_offset)); in mvneta_set_special_mcast_addr()
1915 smc_table_reg &= ~(0xff << (8 * reg_offset)); in mvneta_set_special_mcast_addr()
1916 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); in mvneta_set_special_mcast_addr()
[all …]
/linux-4.1.27/drivers/pinctrl/intel/
Dpinctrl-baytrail.c161 u32 reg_offset; in byt_gpio_reg() local
164 reg_offset = (offset / 32) * 4; in byt_gpio_reg()
166 reg_offset = vg->range->pins[offset] * 16; in byt_gpio_reg()
168 return vg->reg_base + reg_offset + reg; in byt_gpio_reg()
/linux-4.1.27/arch/blackfin/kernel/
Dptrace.c105 void *reg_offset = regs; in put_reg() local
106 *(long *)(reg_offset + regno) = data; in put_reg()
/linux-4.1.27/arch/x86/math-emu/
Dget_address.c30 static int reg_offset[] = { variable
41 #define REG_(x) (*(long *)(reg_offset[(x)] + (u_char *)FPU_info->regs))
/linux-4.1.27/arch/powerpc/sysdev/
Dtsi108_pci.c57 extern u32 tsi108_read_reg(u32 reg_offset);
58 extern void tsi108_write_reg(u32 reg_offset, u32 val);
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb/
Despi.c61 int ch_addr, int reg_offset, u32 wr_data) in tricn_write() argument
66 V_REGISTER_OFFSET(reg_offset) | in tricn_write()
/linux-4.1.27/drivers/gpu/ipu-v3/
Dipu-common.c991 int reg_offset; member
1019 .reg_offset = IPU_CM_CSI0_REG_OFS,
1027 .reg_offset = IPU_CM_CSI1_REG_OFS,
1051 if (reg->reg_offset) { in ipu_add_client_devices()
1054 res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset; in ipu_add_client_devices()
/linux-4.1.27/drivers/net/ethernet/apple/
Dbmac.c93 unsigned short reg_offset;
213 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data ) in bmwrite() argument
215 out_le16((void __iomem *)dev->base_addr + reg_offset, data); in bmwrite()
220 unsigned short bmread(struct net_device *dev, unsigned long reg_offset ) in bmread() argument
222 return in_le16((void __iomem *)dev->base_addr + reg_offset); in bmread()
1582 bmread(bmac_devs, reg_entries[i].reg_offset));
/linux-4.1.27/drivers/net/wireless/iwlegacy/
D4965.c352 u32 reg_offset; in il4965_load_bsm() local
380 for (reg_offset = BSM_SRAM_LOWER_BOUND; in il4965_load_bsm()
381 reg_offset < BSM_SRAM_LOWER_BOUND + len; in il4965_load_bsm()
382 reg_offset += sizeof(u32), image++) in il4965_load_bsm()
383 _il_wr_prph(il, reg_offset, le32_to_cpu(*image)); in il4965_load_bsm()
D3945.c2583 u32 reg_offset; in il3945_load_bsm() local
2607 for (reg_offset = BSM_SRAM_LOWER_BOUND; in il3945_load_bsm()
2608 reg_offset < BSM_SRAM_LOWER_BOUND + len; in il3945_load_bsm()
2609 reg_offset += sizeof(u32), image++) in il3945_load_bsm()
2610 _il_wr_prph(il, reg_offset, le32_to_cpu(*image)); in il3945_load_bsm()
/linux-4.1.27/drivers/mmc/host/
Domap_hsmmc.c237 u32 reg_offset; member
1847 .reg_offset = 0x100,
1850 .reg_offset = 0x100,
1936 pdata->reg_offset = data->reg_offset; in omap_hsmmc_probe()
1972 host->mapbase = res->start + pdata->reg_offset; in omap_hsmmc_probe()
1973 host->base = base + pdata->reg_offset; in omap_hsmmc_probe()
/linux-4.1.27/drivers/pinctrl/mediatek/
Dpinctrl-mtk-common.c799 unsigned int reg_offset; in mtk_eint_flip_edge() local
811 reg_offset = eint_offsets->pol_clr; in mtk_eint_flip_edge()
813 reg_offset = eint_offsets->pol_set; in mtk_eint_flip_edge()
814 writel(mask, reg + reg_offset); in mtk_eint_flip_edge()
/linux-4.1.27/drivers/net/ethernet/intel/igb/
De1000_82575.c2031 u32 reg_val, reg_offset; in igb_vmdq_set_anti_spoofing_pf() local
2035 reg_offset = E1000_DTXSWC; in igb_vmdq_set_anti_spoofing_pf()
2039 reg_offset = E1000_TXSWC; in igb_vmdq_set_anti_spoofing_pf()
2045 reg_val = rd32(reg_offset); in igb_vmdq_set_anti_spoofing_pf()
2057 wr32(reg_offset, reg_val); in igb_vmdq_set_anti_spoofing_pf()
Digb_ethtool.c981 u16 reg_offset; member
1308 (i * test->reg_offset), in igb_reg_test()
1314 (i * test->reg_offset), in igb_reg_test()
1321 + (i * test->reg_offset)); in igb_reg_test()
Digb_main.c7903 u32 reg_val, reg_offset; in igb_ndo_set_vf_spoofchk() local
7911 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; in igb_ndo_set_vf_spoofchk()
7912 reg_val = rd32(reg_offset); in igb_ndo_set_vf_spoofchk()
7919 wr32(reg_offset, reg_val); in igb_ndo_set_vf_spoofchk()
/linux-4.1.27/drivers/leds/
Dleds-bd2802.c153 u8 reg_offset) in bd2802_get_reg_addr() argument
155 return reg_offset + bd2802_get_base_offset(id, color); in bd2802_get_reg_addr()
/linux-4.1.27/drivers/net/wireless/brcm80211/brcmfmac/
Dpcie.c286 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset) in brcmf_pcie_read_reg32() argument
288 void __iomem *address = devinfo->regs + reg_offset; in brcmf_pcie_read_reg32()
295 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset, in brcmf_pcie_write_reg32() argument
298 void __iomem *address = devinfo->regs + reg_offset; in brcmf_pcie_write_reg32()
Dsdio.c755 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset) in w_sdreg32() argument
761 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret); in w_sdreg32()
/linux-4.1.27/drivers/staging/slicoss/
Dslic.h328 ushort reg_offset[32]; member
/linux-4.1.27/drivers/pinctrl/
Dpinctrl-st.c1154 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; in st_pctl_dt_setup_retime_dedicated() local
1161 struct reg_field reg = REG_FIELD(reg_offset, 0, 31); in st_pctl_dt_setup_retime_dedicated()
1165 reg_offset += 4; in st_pctl_dt_setup_retime_dedicated()
/linux-4.1.27/drivers/net/wireless/ath/ath5k/
Dbase.c232 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) in ath5k_ioread32() argument
235 return ath5k_hw_reg_read(ah, reg_offset); in ath5k_ioread32()
238 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) in ath5k_iowrite32() argument
241 ath5k_hw_reg_write(ah, val, reg_offset); in ath5k_iowrite32()
/linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_main.c4118 int reg_offset; in bnx2x_attn_int_deasserted0() local
4121 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : in bnx2x_attn_int_deasserted0()
4126 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted0()
4128 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4145 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted0()
4147 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4171 int reg_offset; in bnx2x_attn_int_deasserted1() local
4173 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : in bnx2x_attn_int_deasserted1()
4176 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted1()
4178 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted1()
[all …]
Dbnx2x_sp.c728 u32 reg_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM : in bnx2x_set_mac_in_nig() local
742 reg_offset += 8*index; in bnx2x_set_mac_in_nig()
748 REG_WR_DMAE(bp, reg_offset, wb_data, 2); in bnx2x_set_mac_in_nig()
/linux-4.1.27/drivers/regulator/
Dpalmas-regulator.c321 .reg_offset = _offset, \
357 .reg_offset = _offset, \
/linux-4.1.27/drivers/net/ethernet/broadcom/genet/
Dbcmgenet.c517 u16 reg_offset; member
544 .reg_offset = offset, \
702 val = bcmgenet_umac_readl(priv, s->reg_offset); in bcmgenet_update_mib_counters()
705 bcmgenet_umac_writel(priv, 0, s->reg_offset); in bcmgenet_update_mib_counters()
/linux-4.1.27/drivers/net/ethernet/calxeda/
Dxgmac.c1587 #define XGMAC_HW_STAT(m, reg_offset) \ argument
1588 { #m, reg_offset, true }
/linux-4.1.27/drivers/scsi/
DFlashPoint.c4954 u32 reg_offset; in FPT_busMstrSGDataXferStart() local
4965 reg_offset = hp_aramBase; in FPT_busMstrSGDataXferStart()
4990 WR_HARP32(p_port, reg_offset, addr); in FPT_busMstrSGDataXferStart()
4991 reg_offset += 4; in FPT_busMstrSGDataXferStart()
4993 WR_HARP32(p_port, reg_offset, count); in FPT_busMstrSGDataXferStart()
4994 reg_offset += 4; in FPT_busMstrSGDataXferStart()
/linux-4.1.27/include/linux/mfd/
Dpalmas.h101 int reg_offset; member