426 		u32 reg_offset, vf_shift, vfre;  in ixgbe_set_vf_lpe()  local
459 		reg_offset = vf / 32;  in ixgbe_set_vf_lpe()
462 		vfre = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));  in ixgbe_set_vf_lpe()
467 		IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), vfre);  in ixgbe_set_vf_lpe()
656 	u32 reg, reg_offset, vf_shift;  in ixgbe_vf_reset_msg()  local
672 	reg_offset = vf / 32;  in ixgbe_vf_reset_msg()
675 	reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));  in ixgbe_vf_reset_msg()
677 	IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);  in ixgbe_vf_reset_msg()
683 	reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));  in ixgbe_vf_reset_msg()
702 	IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);  in ixgbe_vf_reset_msg()
708 	reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));  in ixgbe_vf_reset_msg()
710 	IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);  in ixgbe_vf_reset_msg()