1/* Generic NS8390 register definitions. */ 2/* This file is part of Donald Becker's 8390 drivers, and is distributed 3 under the same license. Auto-loading of 8390.o only in v2.2 - Paul G. 4 Some of these names and comments originated from the Crynwr 5 packet drivers, which are distributed under the GPL. */ 6 7#ifndef _8390_h 8#define _8390_h 9 10#include <linux/if_ether.h> 11#include <linux/ioport.h> 12#include <linux/irqreturn.h> 13#include <linux/skbuff.h> 14 15#define TX_PAGES 12 /* Two Tx slots */ 16 17/* The 8390 specific per-packet-header format. */ 18struct e8390_pkt_hdr { 19 unsigned char status; /* status */ 20 unsigned char next; /* pointer to next packet. */ 21 unsigned short count; /* header + packet length in bytes */ 22}; 23 24#ifdef CONFIG_NET_POLL_CONTROLLER 25void ei_poll(struct net_device *dev); 26void eip_poll(struct net_device *dev); 27#endif 28 29 30/* Without I/O delay - non ISA or later chips */ 31void NS8390_init(struct net_device *dev, int startp); 32int ei_open(struct net_device *dev); 33int ei_close(struct net_device *dev); 34irqreturn_t ei_interrupt(int irq, void *dev_id); 35void ei_tx_timeout(struct net_device *dev); 36netdev_tx_t ei_start_xmit(struct sk_buff *skb, struct net_device *dev); 37void ei_set_multicast_list(struct net_device *dev); 38struct net_device_stats *ei_get_stats(struct net_device *dev); 39 40extern const struct net_device_ops ei_netdev_ops; 41 42struct net_device *__alloc_ei_netdev(int size); 43static inline struct net_device *alloc_ei_netdev(void) 44{ 45 return __alloc_ei_netdev(0); 46} 47 48/* With I/O delay form */ 49void NS8390p_init(struct net_device *dev, int startp); 50int eip_open(struct net_device *dev); 51int eip_close(struct net_device *dev); 52irqreturn_t eip_interrupt(int irq, void *dev_id); 53void eip_tx_timeout(struct net_device *dev); 54netdev_tx_t eip_start_xmit(struct sk_buff *skb, struct net_device *dev); 55void eip_set_multicast_list(struct net_device *dev); 56struct net_device_stats *eip_get_stats(struct net_device *dev); 57 58extern const struct net_device_ops eip_netdev_ops; 59 60struct net_device *__alloc_eip_netdev(int size); 61static inline struct net_device *alloc_eip_netdev(void) 62{ 63 return __alloc_eip_netdev(0); 64} 65 66/* You have one of these per-board */ 67struct ei_device { 68 const char *name; 69 void (*reset_8390)(struct net_device *); 70 void (*get_8390_hdr)(struct net_device *, struct e8390_pkt_hdr *, int); 71 void (*block_output)(struct net_device *, int, const unsigned char *, int); 72 void (*block_input)(struct net_device *, int, struct sk_buff *, int); 73 unsigned long rmem_start; 74 unsigned long rmem_end; 75 void __iomem *mem; 76 unsigned char mcfilter[8]; 77 unsigned open:1; 78 unsigned word16:1; /* We have the 16-bit (vs 8-bit) version of the card. */ 79 unsigned bigendian:1; /* 16-bit big endian mode. Do NOT */ 80 /* set this on random 8390 clones! */ 81 unsigned txing:1; /* Transmit Active */ 82 unsigned irqlock:1; /* 8390's intrs disabled when '1'. */ 83 unsigned dmaing:1; /* Remote DMA Active */ 84 unsigned char tx_start_page, rx_start_page, stop_page; 85 unsigned char current_page; /* Read pointer in buffer */ 86 unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */ 87 unsigned char txqueue; /* Tx Packet buffer queue length. */ 88 short tx1, tx2; /* Packet lengths for ping-pong tx. */ 89 short lasttx; /* Alpha version consistency check. */ 90 unsigned char reg0; /* Register '0' in a WD8013 */ 91 unsigned char reg5; /* Register '5' in a WD8013 */ 92 unsigned char saved_irq; /* Original dev->irq value. */ 93 u32 *reg_offset; /* Register mapping table */ 94 spinlock_t page_lock; /* Page register locks */ 95 unsigned long priv; /* Private field to store bus IDs etc. */ 96 u32 msg_enable; /* debug message level */ 97#ifdef AX88796_PLATFORM 98 unsigned char rxcr_base; /* default value for RXCR */ 99#endif 100}; 101 102/* The maximum number of 8390 interrupt service routines called per IRQ. */ 103#define MAX_SERVICE 12 104 105/* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */ 106#define TX_TIMEOUT (20*HZ/100) 107 108#define ei_status (*(struct ei_device *)netdev_priv(dev)) 109 110/* Some generic ethernet register configurations. */ 111#define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */ 112#define E8390_RX_IRQ_MASK 0x5 113 114#ifdef AX88796_PLATFORM 115#define E8390_RXCONFIG (ei_status.rxcr_base | 0x04) 116#define E8390_RXOFF (ei_status.rxcr_base | 0x20) 117#else 118#define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */ 119#define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */ 120#endif 121 122#define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */ 123#define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */ 124 125 126/* Register accessed at EN_CMD, the 8390 base addr. */ 127#define E8390_STOP 0x01 /* Stop and reset the chip */ 128#define E8390_START 0x02 /* Start the chip, clear reset */ 129#define E8390_TRANS 0x04 /* Transmit a frame */ 130#define E8390_RREAD 0x08 /* Remote read */ 131#define E8390_RWRITE 0x10 /* Remote write */ 132#define E8390_NODMA 0x20 /* Remote DMA */ 133#define E8390_PAGE0 0x00 /* Select page chip registers */ 134#define E8390_PAGE1 0x40 /* using the two high-order bits */ 135#define E8390_PAGE2 0x80 /* Page 3 is invalid. */ 136 137/* 138 * Only generate indirect loads given a machine that needs them. 139 * - removed AMIGA_PCMCIA from this list, handled as ISA io now 140 * - the _p for generates no delay by default 8390p.c overrides this. 141 */ 142 143#ifndef ei_inb 144#define ei_inb(_p) inb(_p) 145#define ei_outb(_v,_p) outb(_v,_p) 146#define ei_inb_p(_p) inb(_p) 147#define ei_outb_p(_v,_p) outb(_v,_p) 148#endif 149 150#ifndef EI_SHIFT 151#define EI_SHIFT(x) (x) 152#endif 153 154#define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */ 155/* Page 0 register offsets. */ 156#define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */ 157#define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */ 158#define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */ 159#define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */ 160#define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */ 161#define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */ 162#define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */ 163#define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */ 164#define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */ 165#define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */ 166#define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */ 167#define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */ 168#define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */ 169#define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */ 170#define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */ 171#define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */ 172#define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */ 173#define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */ 174#define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */ 175#define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */ 176#define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */ 177#define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */ 178#define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */ 179#define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */ 180#define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */ 181#define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */ 182 183/* Bits in EN0_ISR - Interrupt status register */ 184#define ENISR_RX 0x01 /* Receiver, no error */ 185#define ENISR_TX 0x02 /* Transmitter, no error */ 186#define ENISR_RX_ERR 0x04 /* Receiver, with error */ 187#define ENISR_TX_ERR 0x08 /* Transmitter, with error */ 188#define ENISR_OVER 0x10 /* Receiver overwrote the ring */ 189#define ENISR_COUNTERS 0x20 /* Counters need emptying */ 190#define ENISR_RDC 0x40 /* remote dma complete */ 191#define ENISR_RESET 0x80 /* Reset completed */ 192#define ENISR_ALL 0x3f /* Interrupts we will enable */ 193 194/* Bits in EN0_DCFG - Data config register */ 195#define ENDCFG_WTS 0x01 /* word transfer mode selection */ 196#define ENDCFG_BOS 0x02 /* byte order selection */ 197 198/* Page 1 register offsets. */ 199#define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */ 200#define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */ 201#define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */ 202#define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */ 203#define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */ 204 205/* Bits in received packet status byte and EN0_RSR*/ 206#define ENRSR_RXOK 0x01 /* Received a good packet */ 207#define ENRSR_CRC 0x02 /* CRC error */ 208#define ENRSR_FAE 0x04 /* frame alignment error */ 209#define ENRSR_FO 0x08 /* FIFO overrun */ 210#define ENRSR_MPA 0x10 /* missed pkt */ 211#define ENRSR_PHY 0x20 /* physical/multicast address */ 212#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ 213#define ENRSR_DEF 0x80 /* deferring */ 214 215/* Transmitted packet status, EN0_TSR. */ 216#define ENTSR_PTX 0x01 /* Packet transmitted without error */ 217#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ 218#define ENTSR_COL 0x04 /* The transmit collided at least once. */ 219#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ 220#define ENTSR_CRS 0x10 /* The carrier sense was lost. */ 221#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ 222#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ 223#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ 224 225#endif /* _8390_h */ 226