213 	int reg_offset = dev_priv->gpio_mmio_base;  in gmbus_wait_hw_status()  local
223 	I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);  in gmbus_wait_hw_status()
229 		gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);  in gmbus_wait_hw_status()
237 	I915_WRITE(GMBUS4 + reg_offset, 0);  in gmbus_wait_hw_status()
250 	int reg_offset = dev_priv->gpio_mmio_base;  in gmbus_wait_idle()  local
252 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)  in gmbus_wait_idle()
258 	I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);  in gmbus_wait_idle()
263 	I915_WRITE(GMBUS4 + reg_offset, 0);  in gmbus_wait_idle()
277 	int reg_offset = dev_priv->gpio_mmio_base;  in gmbus_xfer_read_chunk()  local
279 	I915_WRITE(GMBUS1 + reg_offset,  in gmbus_xfer_read_chunk()
294 		val = I915_READ(GMBUS3 + reg_offset);  in gmbus_xfer_read_chunk()
332 	int reg_offset = dev_priv->gpio_mmio_base;  in gmbus_xfer_write_chunk()  local
342 	I915_WRITE(GMBUS3 + reg_offset, val);  in gmbus_xfer_write_chunk()
343 	I915_WRITE(GMBUS1 + reg_offset,  in gmbus_xfer_write_chunk()
356 		I915_WRITE(GMBUS3 + reg_offset, val);  in gmbus_xfer_write_chunk()
404 	int reg_offset = dev_priv->gpio_mmio_base;  in gmbus_xfer_index_read()  local
418 		I915_WRITE(GMBUS5 + reg_offset, gmbus5);  in gmbus_xfer_index_read()
424 		I915_WRITE(GMBUS5 + reg_offset, 0);  in gmbus_xfer_index_read()
438 	int i = 0, inc, try = 0, reg_offset;  in gmbus_xfer()  local
449 	reg_offset = dev_priv->gpio_mmio_base;  in gmbus_xfer()
452 	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);  in gmbus_xfer()
482 	I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);  in gmbus_xfer()
493 	I915_WRITE(GMBUS0 + reg_offset, 0);  in gmbus_xfer()
522 	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);  in gmbus_xfer()
523 	I915_WRITE(GMBUS1 + reg_offset, 0);  in gmbus_xfer()
524 	I915_WRITE(GMBUS0 + reg_offset, 0);  in gmbus_xfer()
547 	I915_WRITE(GMBUS0 + reg_offset, 0);  in gmbus_xfer()