Lines Matching refs:reg_offset
192 u32 reg_offset, wb_offset; in cayman_dma_resume() local
198 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
202 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
206 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
207 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
215 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
218 WREG32(DMA_RB_RPTR + reg_offset, 0); in cayman_dma_resume()
219 WREG32(DMA_RB_WPTR + reg_offset, 0); in cayman_dma_resume()
222 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, in cayman_dma_resume()
224 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, in cayman_dma_resume()
230 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); in cayman_dma_resume()
237 WREG32(DMA_IB_CNTL + reg_offset, ib_cntl); in cayman_dma_resume()
239 dma_cntl = RREG32(DMA_CNTL + reg_offset); in cayman_dma_resume()
241 WREG32(DMA_CNTL + reg_offset, dma_cntl); in cayman_dma_resume()
244 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2); in cayman_dma_resume()
246 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); in cayman_dma_resume()