217 		unsigned int reg_offset;  in tile_pcie_open()  local
224 		reg_offset =  in tile_pcie_open()
232 			__gxio_mmio_read(context->mmio_base_mac + reg_offset);  in tile_pcie_open()
313 	unsigned int reg_offset;  in trio_handle_level_irq()  local
322 	reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS <<  in trio_handle_level_irq()
330 	__gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask);  in trio_handle_level_irq()
395 	unsigned int reg_offset;  in strapped_for_rc()  local
398 	reg_offset =  in strapped_for_rc()
405 		__gxio_mmio_read(trio_context->mmio_base_mac + reg_offset);  in strapped_for_rc()
562 	unsigned int reg_offset;  in fixup_read_and_payload_sizes()  local
570 	reg_offset =  in fixup_read_and_payload_sizes()
578 					      reg_offset);  in fixup_read_and_payload_sizes()
580 	__gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,  in fixup_read_and_payload_sizes()
589 	reg_offset =  in fixup_read_and_payload_sizes()
597 					     reg_offset);  in fixup_read_and_payload_sizes()
599 	__gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,  in fixup_read_and_payload_sizes()
609 	reg_offset =  in fixup_read_and_payload_sizes()
617 						reg_offset);  in fixup_read_and_payload_sizes()
693 		unsigned int reg_offset;  in pcibios_init()  local
709 		reg_offset =  in pcibios_init()
718 					 reg_offset);  in pcibios_init()
751 					 reg_offset);  in pcibios_init()
768 		reg_offset =  in pcibios_init()
776 					 reg_offset);  in pcibios_init()
778 		__gxio_mmio_write(trio_context->mmio_base_mac + reg_offset,  in pcibios_init()
785 		reg_offset =  in pcibios_init()
792 		__gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,  in pcibios_init()
798 		reg_offset =  in pcibios_init()
807 					   reg_offset);  in pcibios_init()
812 				    reg_offset, class_code_revision);  in pcibios_init()
1232 			unsigned int reg_offset;  in tile_cfg_read()  local
1234 			reg_offset = ((offset & 0xFFF) <<  in tile_cfg_read()
1241 			mmio_addr = trio_context->mmio_base_mac + reg_offset;  in tile_cfg_read()
1358 			unsigned int reg_offset;  in tile_cfg_write()  local
1360 			reg_offset = ((offset & 0xFFF) <<  in tile_cfg_write()
1367 			mmio_addr = trio_context->mmio_base_mac + reg_offset;  in tile_cfg_write()