1/* 2 * Copyright 2012 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15#include <linux/kernel.h> 16#include <linux/mmzone.h> 17#include <linux/pci.h> 18#include <linux/delay.h> 19#include <linux/string.h> 20#include <linux/init.h> 21#include <linux/capability.h> 22#include <linux/sched.h> 23#include <linux/errno.h> 24#include <linux/irq.h> 25#include <linux/msi.h> 26#include <linux/io.h> 27#include <linux/uaccess.h> 28#include <linux/ctype.h> 29 30#include <asm/processor.h> 31#include <asm/sections.h> 32#include <asm/byteorder.h> 33 34#include <gxio/iorpc_globals.h> 35#include <gxio/kiorpc.h> 36#include <gxio/trio.h> 37#include <gxio/iorpc_trio.h> 38#include <hv/drv_trio_intf.h> 39 40#include <arch/sim.h> 41 42/* 43 * This file containes the routines to search for PCI buses, 44 * enumerate the buses, and configure any attached devices. 45 */ 46 47#define DEBUG_PCI_CFG 0 48 49#if DEBUG_PCI_CFG 50#define TRACE_CFG_WR(size, val, bus, dev, func, offset) \ 51 pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \ 52 size, val, bus, dev, func, offset & 0xFFF); 53#define TRACE_CFG_RD(size, val, bus, dev, func, offset) \ 54 pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \ 55 size, val, bus, dev, func, offset & 0xFFF); 56#else 57#define TRACE_CFG_WR(...) 58#define TRACE_CFG_RD(...) 59#endif 60 61static int pci_probe = 1; 62 63/* Information on the PCIe RC ports configuration. */ 64static int pcie_rc[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES]; 65 66/* 67 * On some platforms with one or more Gx endpoint ports, we need to 68 * delay the PCIe RC port probe for a few seconds to work around 69 * a HW PCIe link-training bug. The exact delay is specified with 70 * a kernel boot argument in the form of "pcie_rc_delay=T,P,S", 71 * where T is the TRIO instance number, P is the port number and S is 72 * the delay in seconds. If the argument is specified, but the delay is 73 * not provided, the value will be DEFAULT_RC_DELAY. 74 */ 75static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES]; 76 77/* Default number of seconds that the PCIe RC port probe can be delayed. */ 78#define DEFAULT_RC_DELAY 10 79 80/* The PCI I/O space size in each PCI domain. */ 81#define IO_SPACE_SIZE 0x10000 82 83/* Provide shorter versions of some very long constant names. */ 84#define AUTO_CONFIG_RC \ 85 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC 86#define AUTO_CONFIG_RC_G1 \ 87 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1 88#define AUTO_CONFIG_EP \ 89 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT 90#define AUTO_CONFIG_EP_G1 \ 91 TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1 92 93/* Array of the PCIe ports configuration info obtained from the BIB. */ 94struct pcie_trio_ports_property pcie_ports[TILEGX_NUM_TRIO]; 95 96/* Number of configured TRIO instances. */ 97int num_trio_shims; 98 99/* All drivers share the TRIO contexts defined here. */ 100gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO]; 101 102/* Pointer to an array of PCIe RC controllers. */ 103struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES]; 104int num_rc_controllers; 105 106static struct pci_ops tile_cfg_ops; 107 108/* Mask of CPUs that should receive PCIe interrupts. */ 109static struct cpumask intr_cpus_map; 110 111/* We don't need to worry about the alignment of resources. */ 112resource_size_t pcibios_align_resource(void *data, const struct resource *res, 113 resource_size_t size, 114 resource_size_t align) 115{ 116 return res->start; 117} 118EXPORT_SYMBOL(pcibios_align_resource); 119 120/* 121 * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #. 122 * For now, we simply send interrupts to non-dataplane CPUs. 123 * We may implement methods to allow user to specify the target CPUs, 124 * e.g. via boot arguments. 125 */ 126static int tile_irq_cpu(int irq) 127{ 128 unsigned int count; 129 int i = 0; 130 int cpu; 131 132 count = cpumask_weight(&intr_cpus_map); 133 if (unlikely(count == 0)) { 134 pr_warn("intr_cpus_map empty, interrupts will be delievered to dataplane tiles\n"); 135 return irq % (smp_height * smp_width); 136 } 137 138 count = irq % count; 139 for_each_cpu(cpu, &intr_cpus_map) { 140 if (i++ == count) 141 break; 142 } 143 return cpu; 144} 145 146/* Open a file descriptor to the TRIO shim. */ 147static int tile_pcie_open(int trio_index) 148{ 149 gxio_trio_context_t *context = &trio_contexts[trio_index]; 150 int ret; 151 int mac; 152 153 /* This opens a file descriptor to the TRIO shim. */ 154 ret = gxio_trio_init(context, trio_index); 155 if (ret < 0) 156 goto gxio_trio_init_failure; 157 158 /* Allocate an ASID for the kernel. */ 159 ret = gxio_trio_alloc_asids(context, 1, 0, 0); 160 if (ret < 0) { 161 pr_err("PCI: ASID alloc failure on TRIO %d, give up\n", 162 trio_index); 163 goto asid_alloc_failure; 164 } 165 166 context->asid = ret; 167 168#ifdef USE_SHARED_PCIE_CONFIG_REGION 169 /* 170 * Alloc a PIO region for config access, shared by all MACs per TRIO. 171 * This shouldn't fail since the kernel is supposed to the first 172 * client of the TRIO's PIO regions. 173 */ 174 ret = gxio_trio_alloc_pio_regions(context, 1, 0, 0); 175 if (ret < 0) { 176 pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n", 177 trio_index); 178 goto pio_alloc_failure; 179 } 180 181 context->pio_cfg_index = ret; 182 183 /* 184 * For PIO CFG, the bus_address_hi parameter is 0. The mac parameter 185 * is also 0 because it is specified in PIO_REGION_SETUP_CFG_ADDR. 186 */ 187 ret = gxio_trio_init_pio_region_aux(context, context->pio_cfg_index, 188 0, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE); 189 if (ret < 0) { 190 pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n", 191 trio_index); 192 goto pio_alloc_failure; 193 } 194#endif 195 196 /* Get the properties of the PCIe ports on this TRIO instance. */ 197 ret = gxio_trio_get_port_property(context, &pcie_ports[trio_index]); 198 if (ret < 0) { 199 pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d, on TRIO %d\n", 200 ret, trio_index); 201 goto get_port_property_failure; 202 } 203 204 context->mmio_base_mac = 205 iorpc_ioremap(context->fd, 0, HV_TRIO_CONFIG_IOREMAP_SIZE); 206 if (context->mmio_base_mac == NULL) { 207 pr_err("PCI: TRIO config space mapping failure, error %d, on TRIO %d\n", 208 ret, trio_index); 209 ret = -ENOMEM; 210 211 goto trio_mmio_mapping_failure; 212 } 213 214 /* Check the port strap state which will override the BIB setting. */ 215 for (mac = 0; mac < TILEGX_TRIO_PCIES; mac++) { 216 TRIO_PCIE_INTFC_PORT_CONFIG_t port_config; 217 unsigned int reg_offset; 218 219 /* Ignore ports that are not specified in the BIB. */ 220 if (!pcie_ports[trio_index].ports[mac].allow_rc && 221 !pcie_ports[trio_index].ports[mac].allow_ep) 222 continue; 223 224 reg_offset = 225 (TRIO_PCIE_INTFC_PORT_CONFIG << 226 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 227 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << 228 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) | 229 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 230 231 port_config.word = 232 __gxio_mmio_read(context->mmio_base_mac + reg_offset); 233 234 if (port_config.strap_state != AUTO_CONFIG_RC && 235 port_config.strap_state != AUTO_CONFIG_RC_G1) { 236 /* 237 * If this is really intended to be an EP port, record 238 * it so that the endpoint driver will know about it. 239 */ 240 if (port_config.strap_state == AUTO_CONFIG_EP || 241 port_config.strap_state == AUTO_CONFIG_EP_G1) 242 pcie_ports[trio_index].ports[mac].allow_ep = 1; 243 } 244 } 245 246 return ret; 247 248trio_mmio_mapping_failure: 249get_port_property_failure: 250asid_alloc_failure: 251#ifdef USE_SHARED_PCIE_CONFIG_REGION 252pio_alloc_failure: 253#endif 254 hv_dev_close(context->fd); 255gxio_trio_init_failure: 256 context->fd = -1; 257 258 return ret; 259} 260 261static int __init tile_trio_init(void) 262{ 263 int i; 264 265 /* We loop over all the TRIO shims. */ 266 for (i = 0; i < TILEGX_NUM_TRIO; i++) { 267 if (tile_pcie_open(i) < 0) 268 continue; 269 num_trio_shims++; 270 } 271 272 return 0; 273} 274postcore_initcall(tile_trio_init); 275 276static void tilegx_legacy_irq_ack(struct irq_data *d) 277{ 278 __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq); 279} 280 281static void tilegx_legacy_irq_mask(struct irq_data *d) 282{ 283 __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq); 284} 285 286static void tilegx_legacy_irq_unmask(struct irq_data *d) 287{ 288 __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq); 289} 290 291static struct irq_chip tilegx_legacy_irq_chip = { 292 .name = "tilegx_legacy_irq", 293 .irq_ack = tilegx_legacy_irq_ack, 294 .irq_mask = tilegx_legacy_irq_mask, 295 .irq_unmask = tilegx_legacy_irq_unmask, 296 297 /* TBD: support set_affinity. */ 298}; 299 300/* 301 * This is a wrapper function of the kernel level-trigger interrupt 302 * handler handle_level_irq() for PCI legacy interrupts. The TRIO 303 * is configured such that only INTx Assert interrupts are proxied 304 * to Linux which just calls handle_level_irq() after clearing the 305 * MAC INTx Assert status bit associated with this interrupt. 306 */ 307static void trio_handle_level_irq(unsigned int irq, struct irq_desc *desc) 308{ 309 struct pci_controller *controller = irq_desc_get_handler_data(desc); 310 gxio_trio_context_t *trio_context = controller->trio; 311 uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc); 312 int mac = controller->mac; 313 unsigned int reg_offset; 314 uint64_t level_mask; 315 316 handle_level_irq(irq, desc); 317 318 /* 319 * Clear the INTx Level status, otherwise future interrupts are 320 * not sent. 321 */ 322 reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS << 323 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 324 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << 325 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | 326 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 327 328 level_mask = TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK << intx; 329 330 __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask); 331} 332 333/* 334 * Create kernel irqs and set up the handlers for the legacy interrupts. 335 * Also some minimum initialization for the MSI support. 336 */ 337static int tile_init_irqs(struct pci_controller *controller) 338{ 339 int i; 340 int j; 341 int irq; 342 int result; 343 344 cpumask_copy(&intr_cpus_map, cpu_online_mask); 345 346 347 for (i = 0; i < 4; i++) { 348 gxio_trio_context_t *context = controller->trio; 349 int cpu; 350 351 /* Ask the kernel to allocate an IRQ. */ 352 irq = irq_alloc_hwirq(-1); 353 if (!irq) { 354 pr_err("PCI: no free irq vectors, failed for %d\n", i); 355 goto free_irqs; 356 } 357 controller->irq_intx_table[i] = irq; 358 359 /* Distribute the 4 IRQs to different tiles. */ 360 cpu = tile_irq_cpu(irq); 361 362 /* Configure the TRIO intr binding for this IRQ. */ 363 result = gxio_trio_config_legacy_intr(context, cpu_x(cpu), 364 cpu_y(cpu), KERNEL_PL, 365 irq, controller->mac, i); 366 if (result < 0) { 367 pr_err("PCI: MAC intx config failed for %d\n", i); 368 369 goto free_irqs; 370 } 371 372 /* Register the IRQ handler with the kernel. */ 373 irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip, 374 trio_handle_level_irq); 375 irq_set_chip_data(irq, (void *)(uint64_t)i); 376 irq_set_handler_data(irq, controller); 377 } 378 379 return 0; 380 381free_irqs: 382 for (j = 0; j < i; j++) 383 irq_free_hwirq(controller->irq_intx_table[j]); 384 385 return -1; 386} 387 388/* 389 * Return 1 if the port is strapped to operate in RC mode. 390 */ 391static int 392strapped_for_rc(gxio_trio_context_t *trio_context, int mac) 393{ 394 TRIO_PCIE_INTFC_PORT_CONFIG_t port_config; 395 unsigned int reg_offset; 396 397 /* Check the port configuration. */ 398 reg_offset = 399 (TRIO_PCIE_INTFC_PORT_CONFIG << 400 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 401 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << 402 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) | 403 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 404 port_config.word = 405 __gxio_mmio_read(trio_context->mmio_base_mac + reg_offset); 406 407 if (port_config.strap_state == AUTO_CONFIG_RC || 408 port_config.strap_state == AUTO_CONFIG_RC_G1) 409 return 1; 410 else 411 return 0; 412} 413 414/* 415 * Find valid controllers and fill in pci_controller structs for each 416 * of them. 417 * 418 * Return the number of controllers discovered. 419 */ 420int __init tile_pci_init(void) 421{ 422 int ctl_index = 0; 423 int i, j; 424 425 if (!pci_probe) { 426 pr_info("PCI: disabled by boot argument\n"); 427 return 0; 428 } 429 430 pr_info("PCI: Searching for controllers...\n"); 431 432 if (num_trio_shims == 0 || sim_is_simulator()) 433 return 0; 434 435 /* 436 * Now determine which PCIe ports are configured to operate in RC 437 * mode. There is a differece in the port configuration capability 438 * between the Gx36 and Gx72 devices. 439 * 440 * The Gx36 has configuration capability for each of the 3 PCIe 441 * interfaces (disable, auto endpoint, auto RC, etc.). 442 * On the Gx72, you can only select one of the 3 PCIe interfaces per 443 * TRIO to train automatically. Further, the allowable training modes 444 * are reduced to four options (auto endpoint, auto RC, stream x1, 445 * stream x4). 446 * 447 * For Gx36 ports, it must be allowed to be in RC mode by the 448 * Board Information Block, and the hardware strapping pins must be 449 * set to RC mode. 450 * 451 * For Gx72 ports, the port will operate in RC mode if either of the 452 * following is true: 453 * 1. It is allowed to be in RC mode by the Board Information Block, 454 * and the BIB doesn't allow the EP mode. 455 * 2. It is allowed to be in either the RC or the EP mode by the BIB, 456 * and the hardware strapping pin is set to RC mode. 457 */ 458 for (i = 0; i < TILEGX_NUM_TRIO; i++) { 459 gxio_trio_context_t *context = &trio_contexts[i]; 460 461 if (context->fd < 0) 462 continue; 463 464 for (j = 0; j < TILEGX_TRIO_PCIES; j++) { 465 int is_rc = 0; 466 467 if (pcie_ports[i].is_gx72 && 468 pcie_ports[i].ports[j].allow_rc) { 469 if (!pcie_ports[i].ports[j].allow_ep || 470 strapped_for_rc(context, j)) 471 is_rc = 1; 472 } else if (pcie_ports[i].ports[j].allow_rc && 473 strapped_for_rc(context, j)) { 474 is_rc = 1; 475 } 476 if (is_rc) { 477 pcie_rc[i][j] = 1; 478 num_rc_controllers++; 479 } 480 } 481 } 482 483 /* Return if no PCIe ports are configured to operate in RC mode. */ 484 if (num_rc_controllers == 0) 485 return 0; 486 487 /* Set the TRIO pointer and MAC index for each PCIe RC port. */ 488 for (i = 0; i < TILEGX_NUM_TRIO; i++) { 489 for (j = 0; j < TILEGX_TRIO_PCIES; j++) { 490 if (pcie_rc[i][j]) { 491 pci_controllers[ctl_index].trio = 492 &trio_contexts[i]; 493 pci_controllers[ctl_index].mac = j; 494 pci_controllers[ctl_index].trio_index = i; 495 ctl_index++; 496 if (ctl_index == num_rc_controllers) 497 goto out; 498 } 499 } 500 } 501 502out: 503 /* Configure each PCIe RC port. */ 504 for (i = 0; i < num_rc_controllers; i++) { 505 506 /* Configure the PCIe MAC to run in RC mode. */ 507 struct pci_controller *controller = &pci_controllers[i]; 508 509 controller->index = i; 510 controller->ops = &tile_cfg_ops; 511 512 controller->io_space.start = PCIBIOS_MIN_IO + 513 (i * IO_SPACE_SIZE); 514 controller->io_space.end = controller->io_space.start + 515 IO_SPACE_SIZE - 1; 516 BUG_ON(controller->io_space.end > IO_SPACE_LIMIT); 517 controller->io_space.flags = IORESOURCE_IO; 518 snprintf(controller->io_space_name, 519 sizeof(controller->io_space_name), 520 "PCI I/O domain %d", i); 521 controller->io_space.name = controller->io_space_name; 522 523 /* 524 * The PCI memory resource is located above the PA space. 525 * For every host bridge, the BAR window or the MMIO aperture 526 * is in range [3GB, 4GB - 1] of a 4GB space beyond the 527 * PA space. 528 */ 529 controller->mem_offset = TILE_PCI_MEM_START + 530 (i * TILE_PCI_BAR_WINDOW_TOP); 531 controller->mem_space.start = controller->mem_offset + 532 TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE; 533 controller->mem_space.end = controller->mem_offset + 534 TILE_PCI_BAR_WINDOW_TOP - 1; 535 controller->mem_space.flags = IORESOURCE_MEM; 536 snprintf(controller->mem_space_name, 537 sizeof(controller->mem_space_name), 538 "PCI mem domain %d", i); 539 controller->mem_space.name = controller->mem_space_name; 540 } 541 542 return num_rc_controllers; 543} 544 545/* 546 * (pin - 1) converts from the PCI standard's [1:4] convention to 547 * a normal [0:3] range. 548 */ 549static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin) 550{ 551 struct pci_controller *controller = 552 (struct pci_controller *)dev->sysdata; 553 return controller->irq_intx_table[pin - 1]; 554} 555 556static void fixup_read_and_payload_sizes(struct pci_controller *controller) 557{ 558 gxio_trio_context_t *trio_context = controller->trio; 559 struct pci_bus *root_bus = controller->root_bus; 560 TRIO_PCIE_RC_DEVICE_CONTROL_t dev_control; 561 TRIO_PCIE_RC_DEVICE_CAP_t rc_dev_cap; 562 unsigned int reg_offset; 563 struct pci_bus *child; 564 int mac; 565 int err; 566 567 mac = controller->mac; 568 569 /* Set our max read request size to be 4KB. */ 570 reg_offset = 571 (TRIO_PCIE_RC_DEVICE_CONTROL << 572 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 573 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << 574 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | 575 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 576 577 dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac + 578 reg_offset); 579 dev_control.max_read_req_sz = 5; 580 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset, 581 dev_control.word); 582 583 /* 584 * Set the max payload size supported by this Gx PCIe MAC. 585 * Though Gx PCIe supports Max Payload Size of up to 1024 bytes, 586 * experiments have shown that setting MPS to 256 yields the 587 * best performance. 588 */ 589 reg_offset = 590 (TRIO_PCIE_RC_DEVICE_CAP << 591 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 592 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << 593 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | 594 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 595 596 rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac + 597 reg_offset); 598 rc_dev_cap.mps_sup = 1; 599 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset, 600 rc_dev_cap.word); 601 602 /* Configure PCI Express MPS setting. */ 603 list_for_each_entry(child, &root_bus->children, node) 604 pcie_bus_configure_settings(child); 605 606 /* 607 * Set the mac_config register in trio based on the MPS/MRS of the link. 608 */ 609 reg_offset = 610 (TRIO_PCIE_RC_DEVICE_CONTROL << 611 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 612 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << 613 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | 614 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 615 616 dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac + 617 reg_offset); 618 619 err = gxio_trio_set_mps_mrs(trio_context, 620 dev_control.max_payload_size, 621 dev_control.max_read_req_sz, 622 mac); 623 if (err < 0) { 624 pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, MAC %d on TRIO %d\n", 625 mac, controller->trio_index); 626 } 627} 628 629static int setup_pcie_rc_delay(char *str) 630{ 631 unsigned long delay = 0; 632 unsigned long trio_index; 633 unsigned long mac; 634 635 if (str == NULL || !isdigit(*str)) 636 return -EINVAL; 637 trio_index = simple_strtoul(str, (char **)&str, 10); 638 if (trio_index >= TILEGX_NUM_TRIO) 639 return -EINVAL; 640 641 if (*str != ',') 642 return -EINVAL; 643 644 str++; 645 if (!isdigit(*str)) 646 return -EINVAL; 647 mac = simple_strtoul(str, (char **)&str, 10); 648 if (mac >= TILEGX_TRIO_PCIES) 649 return -EINVAL; 650 651 if (*str != '\0') { 652 if (*str != ',') 653 return -EINVAL; 654 655 str++; 656 if (!isdigit(*str)) 657 return -EINVAL; 658 delay = simple_strtoul(str, (char **)&str, 10); 659 } 660 661 rc_delay[trio_index][mac] = delay ? : DEFAULT_RC_DELAY; 662 return 0; 663} 664early_param("pcie_rc_delay", setup_pcie_rc_delay); 665 666/* PCI initialization entry point, called by subsys_initcall. */ 667int __init pcibios_init(void) 668{ 669 resource_size_t offset; 670 LIST_HEAD(resources); 671 int next_busno; 672 int i; 673 674 tile_pci_init(); 675 676 if (num_rc_controllers == 0) 677 return 0; 678 679 /* 680 * Delay a bit in case devices aren't ready. Some devices are 681 * known to require at least 20ms here, but we use a more 682 * conservative value. 683 */ 684 msleep(250); 685 686 /* Scan all of the recorded PCI controllers. */ 687 for (next_busno = 0, i = 0; i < num_rc_controllers; i++) { 688 struct pci_controller *controller = &pci_controllers[i]; 689 gxio_trio_context_t *trio_context = controller->trio; 690 TRIO_PCIE_INTFC_PORT_STATUS_t port_status; 691 TRIO_PCIE_INTFC_TX_FIFO_CTL_t tx_fifo_ctl; 692 struct pci_bus *bus; 693 unsigned int reg_offset; 694 unsigned int class_code_revision; 695 int trio_index; 696 int mac; 697 int ret; 698 699 if (trio_context->fd < 0) 700 continue; 701 702 trio_index = controller->trio_index; 703 mac = controller->mac; 704 705 /* 706 * Check for PCIe link-up status to decide if we need 707 * to force the link to come up. 708 */ 709 reg_offset = 710 (TRIO_PCIE_INTFC_PORT_STATUS << 711 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 712 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << 713 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) | 714 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 715 716 port_status.word = 717 __gxio_mmio_read(trio_context->mmio_base_mac + 718 reg_offset); 719 if (!port_status.dl_up) { 720 if (rc_delay[trio_index][mac]) { 721 pr_info("Delaying PCIe RC TRIO init %d sec on MAC %d on TRIO %d\n", 722 rc_delay[trio_index][mac], mac, 723 trio_index); 724 msleep(rc_delay[trio_index][mac] * 1000); 725 } 726 ret = gxio_trio_force_rc_link_up(trio_context, mac); 727 if (ret < 0) 728 pr_err("PCI: PCIE_FORCE_LINK_UP failure, MAC %d on TRIO %d\n", 729 mac, trio_index); 730 } 731 732 pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n", 733 i, trio_index, controller->mac); 734 735 /* Delay the bus probe if needed. */ 736 if (rc_delay[trio_index][mac]) { 737 pr_info("Delaying PCIe RC bus enumerating %d sec on MAC %d on TRIO %d\n", 738 rc_delay[trio_index][mac], mac, trio_index); 739 msleep(rc_delay[trio_index][mac] * 1000); 740 } else { 741 /* 742 * Wait a bit here because some EP devices 743 * take longer to come up. 744 */ 745 msleep(1000); 746 } 747 748 /* Check for PCIe link-up status again. */ 749 port_status.word = 750 __gxio_mmio_read(trio_context->mmio_base_mac + 751 reg_offset); 752 if (!port_status.dl_up) { 753 if (pcie_ports[trio_index].ports[mac].removable) { 754 pr_info("PCI: link is down, MAC %d on TRIO %d\n", 755 mac, trio_index); 756 pr_info("This is expected if no PCIe card is connected to this link\n"); 757 } else 758 pr_err("PCI: link is down, MAC %d on TRIO %d\n", 759 mac, trio_index); 760 continue; 761 } 762 763 /* 764 * Ensure that the link can come out of L1 power down state. 765 * Strictly speaking, this is needed only in the case of 766 * heavy RC-initiated DMAs. 767 */ 768 reg_offset = 769 (TRIO_PCIE_INTFC_TX_FIFO_CTL << 770 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 771 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE << 772 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | 773 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 774 tx_fifo_ctl.word = 775 __gxio_mmio_read(trio_context->mmio_base_mac + 776 reg_offset); 777 tx_fifo_ctl.min_p_credits = 0; 778 __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, 779 tx_fifo_ctl.word); 780 781 /* 782 * Change the device ID so that Linux bus crawl doesn't confuse 783 * the internal bridge with any Tilera endpoints. 784 */ 785 reg_offset = 786 (TRIO_PCIE_RC_DEVICE_ID_VEN_ID << 787 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 788 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << 789 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | 790 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 791 792 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset, 793 (TILERA_GX36_RC_DEV_ID << 794 TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) | 795 TILERA_VENDOR_ID); 796 797 /* Set the internal P2P bridge class code. */ 798 reg_offset = 799 (TRIO_PCIE_RC_REVISION_ID << 800 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 801 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD << 802 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | 803 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 804 805 class_code_revision = 806 __gxio_mmio_read32(trio_context->mmio_base_mac + 807 reg_offset); 808 class_code_revision = (class_code_revision & 0xff) | 809 (PCI_CLASS_BRIDGE_PCI << 16); 810 811 __gxio_mmio_write32(trio_context->mmio_base_mac + 812 reg_offset, class_code_revision); 813 814#ifdef USE_SHARED_PCIE_CONFIG_REGION 815 816 /* Map in the MMIO space for the PIO region. */ 817 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) | 818 (((unsigned long long)mac) << 819 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT); 820 821#else 822 823 /* Alloc a PIO region for PCI config access per MAC. */ 824 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0); 825 if (ret < 0) { 826 pr_err("PCI: PCI CFG PIO alloc failure for mac %d on TRIO %d, give up\n", 827 mac, trio_index); 828 829 continue; 830 } 831 832 trio_context->pio_cfg_index[mac] = ret; 833 834 /* For PIO CFG, the bus_address_hi parameter is 0. */ 835 ret = gxio_trio_init_pio_region_aux(trio_context, 836 trio_context->pio_cfg_index[mac], 837 mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE); 838 if (ret < 0) { 839 pr_err("PCI: PCI CFG PIO init failure for mac %d on TRIO %d, give up\n", 840 mac, trio_index); 841 842 continue; 843 } 844 845 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index[mac]) | 846 (((unsigned long long)mac) << 847 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT); 848 849#endif 850 851 /* 852 * To save VMALLOC space, we take advantage of the fact that 853 * bit 29 in the PIO CFG address format is reserved 0. With 854 * TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT being 30, 855 * this cuts VMALLOC space usage from 1GB to 512MB per mac. 856 */ 857 trio_context->mmio_base_pio_cfg[mac] = 858 iorpc_ioremap(trio_context->fd, offset, (1UL << 859 (TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT - 1))); 860 if (trio_context->mmio_base_pio_cfg[mac] == NULL) { 861 pr_err("PCI: PIO map failure for mac %d on TRIO %d\n", 862 mac, trio_index); 863 864 continue; 865 } 866 867 /* Initialize the PCIe interrupts. */ 868 if (tile_init_irqs(controller)) { 869 pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n", 870 mac, trio_index); 871 872 continue; 873 } 874 875 /* 876 * The PCI memory resource is located above the PA space. 877 * The memory range for the PCI root bus should not overlap 878 * with the physical RAM. 879 */ 880 pci_add_resource_offset(&resources, &controller->mem_space, 881 controller->mem_offset); 882 pci_add_resource(&resources, &controller->io_space); 883 controller->first_busno = next_busno; 884 bus = pci_scan_root_bus(NULL, next_busno, controller->ops, 885 controller, &resources); 886 controller->root_bus = bus; 887 next_busno = bus->busn_res.end + 1; 888 } 889 890 /* Do machine dependent PCI interrupt routing */ 891 pci_fixup_irqs(pci_common_swizzle, tile_map_irq); 892 893 /* 894 * This comes from the generic Linux PCI driver. 895 * 896 * It allocates all of the resources (I/O memory, etc) 897 * associated with the devices read in above. 898 */ 899 pci_assign_unassigned_resources(); 900 901 /* Record the I/O resources in the PCI controller structure. */ 902 for (i = 0; i < num_rc_controllers; i++) { 903 struct pci_controller *controller = &pci_controllers[i]; 904 gxio_trio_context_t *trio_context = controller->trio; 905 struct pci_bus *root_bus = pci_controllers[i].root_bus; 906 int ret; 907 int j; 908 909 /* 910 * Skip controllers that are not properly initialized or 911 * have down links. 912 */ 913 if (root_bus == NULL) 914 continue; 915 916 /* Configure the max_payload_size values for this domain. */ 917 fixup_read_and_payload_sizes(controller); 918 919 /* Alloc a PIO region for PCI memory access for each RC port. */ 920 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0); 921 if (ret < 0) { 922 pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, give up\n", 923 controller->trio_index, controller->mac); 924 925 continue; 926 } 927 928 controller->pio_mem_index = ret; 929 930 /* 931 * For PIO MEM, the bus_address_hi parameter is hard-coded 0 932 * because we always assign 32-bit PCI bus BAR ranges. 933 */ 934 ret = gxio_trio_init_pio_region_aux(trio_context, 935 controller->pio_mem_index, 936 controller->mac, 937 0, 938 0); 939 if (ret < 0) { 940 pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, give up\n", 941 controller->trio_index, controller->mac); 942 943 continue; 944 } 945 946#ifdef CONFIG_TILE_PCI_IO 947 /* 948 * Alloc a PIO region for PCI I/O space access for each RC port. 949 */ 950 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0); 951 if (ret < 0) { 952 pr_err("PCI: I/O PIO alloc failure on TRIO %d mac %d, give up\n", 953 controller->trio_index, controller->mac); 954 955 continue; 956 } 957 958 controller->pio_io_index = ret; 959 960 /* 961 * For PIO IO, the bus_address_hi parameter is hard-coded 0 962 * because PCI I/O address space is 32-bit. 963 */ 964 ret = gxio_trio_init_pio_region_aux(trio_context, 965 controller->pio_io_index, 966 controller->mac, 967 0, 968 HV_TRIO_PIO_FLAG_IO_SPACE); 969 if (ret < 0) { 970 pr_err("PCI: I/O PIO init failure on TRIO %d mac %d, give up\n", 971 controller->trio_index, controller->mac); 972 973 continue; 974 } 975#endif 976 977 /* 978 * Configure a Mem-Map region for each memory controller so 979 * that Linux can map all of its PA space to the PCI bus. 980 * Use the IOMMU to handle hash-for-home memory. 981 */ 982 for_each_online_node(j) { 983 unsigned long start_pfn = node_start_pfn[j]; 984 unsigned long end_pfn = node_end_pfn[j]; 985 unsigned long nr_pages = end_pfn - start_pfn; 986 987 ret = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 988 0); 989 if (ret < 0) { 990 pr_err("PCI: Mem-Map alloc failure on TRIO %d mac %d for MC %d, give up\n", 991 controller->trio_index, controller->mac, 992 j); 993 994 goto alloc_mem_map_failed; 995 } 996 997 controller->mem_maps[j] = ret; 998 999 /* 1000 * Initialize the Mem-Map and the I/O MMU so that all 1001 * the physical memory can be accessed by the endpoint 1002 * devices. The base bus address is set to the base CPA 1003 * of this memory controller plus an offset (see pci.h). 1004 * The region's base VA is set to the base CPA. The 1005 * I/O MMU table essentially translates the CPA to 1006 * the real PA. Implicitly, for node 0, we create 1007 * a separate Mem-Map region that serves as the inbound 1008 * window for legacy 32-bit devices. This is a direct 1009 * map of the low 4GB CPA space. 1010 */ 1011 ret = gxio_trio_init_memory_map_mmu_aux(trio_context, 1012 controller->mem_maps[j], 1013 start_pfn << PAGE_SHIFT, 1014 nr_pages << PAGE_SHIFT, 1015 trio_context->asid, 1016 controller->mac, 1017 (start_pfn << PAGE_SHIFT) + 1018 TILE_PCI_MEM_MAP_BASE_OFFSET, 1019 j, 1020 GXIO_TRIO_ORDER_MODE_UNORDERED); 1021 if (ret < 0) { 1022 pr_err("PCI: Mem-Map init failure on TRIO %d mac %d for MC %d, give up\n", 1023 controller->trio_index, controller->mac, 1024 j); 1025 1026 goto alloc_mem_map_failed; 1027 } 1028 continue; 1029 1030alloc_mem_map_failed: 1031 break; 1032 } 1033 1034 pci_bus_add_devices(root_bus); 1035 } 1036 1037 return 0; 1038} 1039subsys_initcall(pcibios_init); 1040 1041/* No bus fixups needed. */ 1042void pcibios_fixup_bus(struct pci_bus *bus) 1043{ 1044} 1045 1046/* Process any "pci=" kernel boot arguments. */ 1047char *__init pcibios_setup(char *str) 1048{ 1049 if (!strcmp(str, "off")) { 1050 pci_probe = 0; 1051 return NULL; 1052 } 1053 return str; 1054} 1055 1056/* 1057 * Called for each device after PCI setup is done. 1058 * We initialize the PCI device capabilities conservatively, assuming that 1059 * all devices can only address the 32-bit DMA space. The exception here is 1060 * that the device dma_offset is set to the value that matches the 64-bit 1061 * capable devices. This is OK because dma_offset is not used by legacy 1062 * dma_ops, nor by the hybrid dma_ops's streaming DMAs, which are 64-bit ops. 1063 * This implementation matches the kernel design of setting PCI devices' 1064 * coherent_dma_mask to 0xffffffffull by default, allowing the device drivers 1065 * to skip calling pci_set_consistent_dma_mask(DMA_BIT_MASK(32)). 1066 */ 1067static void pcibios_fixup_final(struct pci_dev *pdev) 1068{ 1069 set_dma_ops(&pdev->dev, gx_legacy_pci_dma_map_ops); 1070 set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET); 1071 pdev->dev.archdata.max_direct_dma_addr = 1072 TILE_PCI_MAX_DIRECT_DMA_ADDRESS; 1073 pdev->dev.coherent_dma_mask = TILE_PCI_MAX_DIRECT_DMA_ADDRESS; 1074} 1075DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final); 1076 1077/* Map a PCI MMIO bus address into VA space. */ 1078void __iomem *ioremap(resource_size_t phys_addr, unsigned long size) 1079{ 1080 struct pci_controller *controller = NULL; 1081 resource_size_t bar_start; 1082 resource_size_t bar_end; 1083 resource_size_t offset; 1084 resource_size_t start; 1085 resource_size_t end; 1086 int trio_fd; 1087 int i; 1088 1089 start = phys_addr; 1090 end = phys_addr + size - 1; 1091 1092 /* 1093 * By searching phys_addr in each controller's mem_space, we can 1094 * determine the controller that should accept the PCI memory access. 1095 */ 1096 for (i = 0; i < num_rc_controllers; i++) { 1097 /* 1098 * Skip controllers that are not properly initialized or 1099 * have down links. 1100 */ 1101 if (pci_controllers[i].root_bus == NULL) 1102 continue; 1103 1104 bar_start = pci_controllers[i].mem_space.start; 1105 bar_end = pci_controllers[i].mem_space.end; 1106 1107 if ((start >= bar_start) && (end <= bar_end)) { 1108 controller = &pci_controllers[i]; 1109 break; 1110 } 1111 } 1112 1113 if (controller == NULL) 1114 return NULL; 1115 1116 trio_fd = controller->trio->fd; 1117 1118 /* Convert the resource start to the bus address offset. */ 1119 start = phys_addr - controller->mem_offset; 1120 1121 offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start; 1122 1123 /* We need to keep the PCI bus address's in-page offset in the VA. */ 1124 return iorpc_ioremap(trio_fd, offset, size) + 1125 (start & (PAGE_SIZE - 1)); 1126} 1127EXPORT_SYMBOL(ioremap); 1128 1129#ifdef CONFIG_TILE_PCI_IO 1130/* Map a PCI I/O address into VA space. */ 1131void __iomem *ioport_map(unsigned long port, unsigned int size) 1132{ 1133 struct pci_controller *controller = NULL; 1134 resource_size_t bar_start; 1135 resource_size_t bar_end; 1136 resource_size_t offset; 1137 resource_size_t start; 1138 resource_size_t end; 1139 int trio_fd; 1140 int i; 1141 1142 start = port; 1143 end = port + size - 1; 1144 1145 /* 1146 * By searching the port in each controller's io_space, we can 1147 * determine the controller that should accept the PCI I/O access. 1148 */ 1149 for (i = 0; i < num_rc_controllers; i++) { 1150 /* 1151 * Skip controllers that are not properly initialized or 1152 * have down links. 1153 */ 1154 if (pci_controllers[i].root_bus == NULL) 1155 continue; 1156 1157 bar_start = pci_controllers[i].io_space.start; 1158 bar_end = pci_controllers[i].io_space.end; 1159 1160 if ((start >= bar_start) && (end <= bar_end)) { 1161 controller = &pci_controllers[i]; 1162 break; 1163 } 1164 } 1165 1166 if (controller == NULL) 1167 return NULL; 1168 1169 trio_fd = controller->trio->fd; 1170 1171 /* Convert the resource start to the bus address offset. */ 1172 port -= controller->io_space.start; 1173 1174 offset = HV_TRIO_PIO_OFFSET(controller->pio_io_index) + port; 1175 1176 /* We need to keep the PCI bus address's in-page offset in the VA. */ 1177 return iorpc_ioremap(trio_fd, offset, size) + (port & (PAGE_SIZE - 1)); 1178} 1179EXPORT_SYMBOL(ioport_map); 1180 1181void ioport_unmap(void __iomem *addr) 1182{ 1183 iounmap(addr); 1184} 1185EXPORT_SYMBOL(ioport_unmap); 1186#endif 1187 1188void pci_iounmap(struct pci_dev *dev, void __iomem *addr) 1189{ 1190 iounmap(addr); 1191} 1192EXPORT_SYMBOL(pci_iounmap); 1193 1194/**************************************************************** 1195 * 1196 * Tile PCI config space read/write routines 1197 * 1198 ****************************************************************/ 1199 1200/* 1201 * These are the normal read and write ops 1202 * These are expanded with macros from pci_bus_read_config_byte() etc. 1203 * 1204 * devfn is the combined PCI device & function. 1205 * 1206 * offset is in bytes, from the start of config space for the 1207 * specified bus & device. 1208 */ 1209static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset, 1210 int size, u32 *val) 1211{ 1212 struct pci_controller *controller = bus->sysdata; 1213 gxio_trio_context_t *trio_context = controller->trio; 1214 int busnum = bus->number & 0xff; 1215 int device = PCI_SLOT(devfn); 1216 int function = PCI_FUNC(devfn); 1217 int config_type = 1; 1218 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr; 1219 void *mmio_addr; 1220 1221 /* 1222 * Map all accesses to the local device on root bus into the 1223 * MMIO space of the MAC. Accesses to the downstream devices 1224 * go to the PIO space. 1225 */ 1226 if (pci_is_root_bus(bus)) { 1227 if (device == 0) { 1228 /* 1229 * This is the internal downstream P2P bridge, 1230 * access directly. 1231 */ 1232 unsigned int reg_offset; 1233 1234 reg_offset = ((offset & 0xFFF) << 1235 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 1236 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED 1237 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | 1238 (controller->mac << 1239 TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 1240 1241 mmio_addr = trio_context->mmio_base_mac + reg_offset; 1242 1243 goto valid_device; 1244 1245 } else { 1246 /* 1247 * We fake an empty device for (device > 0), 1248 * since there is only one device on bus 0. 1249 */ 1250 goto invalid_device; 1251 } 1252 } 1253 1254 /* 1255 * Accesses to the directly attached device have to be 1256 * sent as type-0 configs. 1257 */ 1258 if (busnum == (controller->first_busno + 1)) { 1259 /* 1260 * There is only one device off of our built-in P2P bridge. 1261 */ 1262 if (device != 0) 1263 goto invalid_device; 1264 1265 config_type = 0; 1266 } 1267 1268 cfg_addr.word = 0; 1269 cfg_addr.reg_addr = (offset & 0xFFF); 1270 cfg_addr.fn = function; 1271 cfg_addr.dev = device; 1272 cfg_addr.bus = busnum; 1273 cfg_addr.type = config_type; 1274 1275 /* 1276 * Note that we don't set the mac field in cfg_addr because the 1277 * mapping is per port. 1278 */ 1279 mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] + 1280 cfg_addr.word; 1281 1282valid_device: 1283 1284 switch (size) { 1285 case 4: 1286 *val = __gxio_mmio_read32(mmio_addr); 1287 break; 1288 1289 case 2: 1290 *val = __gxio_mmio_read16(mmio_addr); 1291 break; 1292 1293 case 1: 1294 *val = __gxio_mmio_read8(mmio_addr); 1295 break; 1296 1297 default: 1298 return PCIBIOS_FUNC_NOT_SUPPORTED; 1299 } 1300 1301 TRACE_CFG_RD(size, *val, busnum, device, function, offset); 1302 1303 return 0; 1304 1305invalid_device: 1306 1307 switch (size) { 1308 case 4: 1309 *val = 0xFFFFFFFF; 1310 break; 1311 1312 case 2: 1313 *val = 0xFFFF; 1314 break; 1315 1316 case 1: 1317 *val = 0xFF; 1318 break; 1319 1320 default: 1321 return PCIBIOS_FUNC_NOT_SUPPORTED; 1322 } 1323 1324 return 0; 1325} 1326 1327 1328/* 1329 * See tile_cfg_read() for relevent comments. 1330 * Note that "val" is the value to write, not a pointer to that value. 1331 */ 1332static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset, 1333 int size, u32 val) 1334{ 1335 struct pci_controller *controller = bus->sysdata; 1336 gxio_trio_context_t *trio_context = controller->trio; 1337 int busnum = bus->number & 0xff; 1338 int device = PCI_SLOT(devfn); 1339 int function = PCI_FUNC(devfn); 1340 int config_type = 1; 1341 TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr; 1342 void *mmio_addr; 1343 u32 val_32 = (u32)val; 1344 u16 val_16 = (u16)val; 1345 u8 val_8 = (u8)val; 1346 1347 /* 1348 * Map all accesses to the local device on root bus into the 1349 * MMIO space of the MAC. Accesses to the downstream devices 1350 * go to the PIO space. 1351 */ 1352 if (pci_is_root_bus(bus)) { 1353 if (device == 0) { 1354 /* 1355 * This is the internal downstream P2P bridge, 1356 * access directly. 1357 */ 1358 unsigned int reg_offset; 1359 1360 reg_offset = ((offset & 0xFFF) << 1361 TRIO_CFG_REGION_ADDR__REG_SHIFT) | 1362 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED 1363 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) | 1364 (controller->mac << 1365 TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT); 1366 1367 mmio_addr = trio_context->mmio_base_mac + reg_offset; 1368 1369 goto valid_device; 1370 1371 } else { 1372 /* 1373 * We fake an empty device for (device > 0), 1374 * since there is only one device on bus 0. 1375 */ 1376 goto invalid_device; 1377 } 1378 } 1379 1380 /* 1381 * Accesses to the directly attached device have to be 1382 * sent as type-0 configs. 1383 */ 1384 if (busnum == (controller->first_busno + 1)) { 1385 /* 1386 * There is only one device off of our built-in P2P bridge. 1387 */ 1388 if (device != 0) 1389 goto invalid_device; 1390 1391 config_type = 0; 1392 } 1393 1394 cfg_addr.word = 0; 1395 cfg_addr.reg_addr = (offset & 0xFFF); 1396 cfg_addr.fn = function; 1397 cfg_addr.dev = device; 1398 cfg_addr.bus = busnum; 1399 cfg_addr.type = config_type; 1400 1401 /* 1402 * Note that we don't set the mac field in cfg_addr because the 1403 * mapping is per port. 1404 */ 1405 mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] + 1406 cfg_addr.word; 1407 1408valid_device: 1409 1410 switch (size) { 1411 case 4: 1412 __gxio_mmio_write32(mmio_addr, val_32); 1413 TRACE_CFG_WR(size, val_32, busnum, device, function, offset); 1414 break; 1415 1416 case 2: 1417 __gxio_mmio_write16(mmio_addr, val_16); 1418 TRACE_CFG_WR(size, val_16, busnum, device, function, offset); 1419 break; 1420 1421 case 1: 1422 __gxio_mmio_write8(mmio_addr, val_8); 1423 TRACE_CFG_WR(size, val_8, busnum, device, function, offset); 1424 break; 1425 1426 default: 1427 return PCIBIOS_FUNC_NOT_SUPPORTED; 1428 } 1429 1430invalid_device: 1431 1432 return 0; 1433} 1434 1435 1436static struct pci_ops tile_cfg_ops = { 1437 .read = tile_cfg_read, 1438 .write = tile_cfg_write, 1439}; 1440 1441 1442/* MSI support starts here. */ 1443static unsigned int tilegx_msi_startup(struct irq_data *d) 1444{ 1445 if (d->msi_desc) 1446 pci_msi_unmask_irq(d); 1447 1448 return 0; 1449} 1450 1451static void tilegx_msi_ack(struct irq_data *d) 1452{ 1453 __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq); 1454} 1455 1456static void tilegx_msi_mask(struct irq_data *d) 1457{ 1458 pci_msi_mask_irq(d); 1459 __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq); 1460} 1461 1462static void tilegx_msi_unmask(struct irq_data *d) 1463{ 1464 __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq); 1465 pci_msi_unmask_irq(d); 1466} 1467 1468static struct irq_chip tilegx_msi_chip = { 1469 .name = "tilegx_msi", 1470 .irq_startup = tilegx_msi_startup, 1471 .irq_ack = tilegx_msi_ack, 1472 .irq_mask = tilegx_msi_mask, 1473 .irq_unmask = tilegx_msi_unmask, 1474 1475 /* TBD: support set_affinity. */ 1476}; 1477 1478int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) 1479{ 1480 struct pci_controller *controller; 1481 gxio_trio_context_t *trio_context; 1482 struct msi_msg msg; 1483 int default_irq; 1484 uint64_t mem_map_base; 1485 uint64_t mem_map_limit; 1486 u64 msi_addr; 1487 int mem_map; 1488 int cpu; 1489 int irq; 1490 int ret; 1491 1492 irq = irq_alloc_hwirq(-1); 1493 if (!irq) 1494 return -ENOSPC; 1495 1496 /* 1497 * Since we use a 64-bit Mem-Map to accept the MSI write, we fail 1498 * devices that are not capable of generating a 64-bit message address. 1499 * These devices will fall back to using the legacy interrupts. 1500 * Most PCIe endpoint devices do support 64-bit message addressing. 1501 */ 1502 if (desc->msi_attrib.is_64 == 0) { 1503 dev_info(&pdev->dev, "64-bit MSI message address not supported, falling back to legacy interrupts\n"); 1504 1505 ret = -ENOMEM; 1506 goto is_64_failure; 1507 } 1508 1509 default_irq = desc->msi_attrib.default_irq; 1510 controller = irq_get_handler_data(default_irq); 1511 1512 BUG_ON(!controller); 1513 1514 trio_context = controller->trio; 1515 1516 /* 1517 * Allocate a scatter-queue that will accept the MSI write and 1518 * trigger the TILE-side interrupts. We use the scatter-queue regions 1519 * before the mem map regions, because the latter are needed by more 1520 * applications. 1521 */ 1522 mem_map = gxio_trio_alloc_scatter_queues(trio_context, 1, 0, 0); 1523 if (mem_map >= 0) { 1524 TRIO_MAP_SQ_DOORBELL_FMT_t doorbell_template = {{ 1525 .pop = 0, 1526 .doorbell = 1, 1527 }}; 1528 1529 mem_map += TRIO_NUM_MAP_MEM_REGIONS; 1530 mem_map_base = MEM_MAP_INTR_REGIONS_BASE + 1531 mem_map * MEM_MAP_INTR_REGION_SIZE; 1532 mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1; 1533 1534 msi_addr = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 8; 1535 msg.data = (unsigned int)doorbell_template.word; 1536 } else { 1537 /* SQ regions are out, allocate from map mem regions. */ 1538 mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0); 1539 if (mem_map < 0) { 1540 dev_info(&pdev->dev, "%s Mem-Map alloc failure - failed to initialize MSI interrupts - falling back to legacy interrupts\n", 1541 desc->msi_attrib.is_msix ? "MSI-X" : "MSI"); 1542 ret = -ENOMEM; 1543 goto msi_mem_map_alloc_failure; 1544 } 1545 1546 mem_map_base = MEM_MAP_INTR_REGIONS_BASE + 1547 mem_map * MEM_MAP_INTR_REGION_SIZE; 1548 mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1; 1549 1550 msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 - 1551 TRIO_MAP_MEM_REG_INT0; 1552 1553 msg.data = mem_map; 1554 } 1555 1556 /* We try to distribute different IRQs to different tiles. */ 1557 cpu = tile_irq_cpu(irq); 1558 1559 /* 1560 * Now call up to the HV to configure the MSI interrupt and 1561 * set up the IPI binding. 1562 */ 1563 ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu), 1564 KERNEL_PL, irq, controller->mac, 1565 mem_map, mem_map_base, mem_map_limit, 1566 trio_context->asid); 1567 if (ret < 0) { 1568 dev_info(&pdev->dev, "HV MSI config failed\n"); 1569 1570 goto hv_msi_config_failure; 1571 } 1572 1573 irq_set_msi_desc(irq, desc); 1574 1575 msg.address_hi = msi_addr >> 32; 1576 msg.address_lo = msi_addr & 0xffffffff; 1577 1578 pci_write_msi_msg(irq, &msg); 1579 irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq); 1580 irq_set_handler_data(irq, controller); 1581 1582 return 0; 1583 1584hv_msi_config_failure: 1585 /* Free mem-map */ 1586msi_mem_map_alloc_failure: 1587is_64_failure: 1588 irq_free_hwirq(irq); 1589 return ret; 1590} 1591 1592void arch_teardown_msi_irq(unsigned int irq) 1593{ 1594 irq_free_hwirq(irq); 1595} 1596