2323 	u32 reg_offset, gb_tile_moden, split_equal_to_row_size;  in cik_tiling_mode_table_init()  local
2346 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2347 			switch (reg_offset) {  in cik_tiling_mode_table_init()
2472 			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2473 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
2475 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2476 			switch (reg_offset) {  in cik_tiling_mode_table_init()
2565 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2566 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
2569 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2570 			switch (reg_offset) {  in cik_tiling_mode_table_init()
2695 			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2696 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
2698 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2699 			switch (reg_offset) {  in cik_tiling_mode_table_init()
2788 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2789 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
2793 			for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2794 				switch (reg_offset) {  in cik_tiling_mode_table_init()
2919 				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2920 				WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
2923 			for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
2924 				switch (reg_offset) {  in cik_tiling_mode_table_init()
3049 				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3050 				WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
3053 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
3054 			switch (reg_offset) {  in cik_tiling_mode_table_init()
3143 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3144 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
3147 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
3148 			switch (reg_offset) {  in cik_tiling_mode_table_init()
3273 			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3274 			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()
3276 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {  in cik_tiling_mode_table_init()
3277 			switch (reg_offset) {  in cik_tiling_mode_table_init()
3366 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3367 			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);  in cik_tiling_mode_table_init()