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Searched refs:membase (Results 1 – 200 of 233) sorted by relevance

12

/linux-4.4.14/drivers/tty/serial/
Dbfin_sport_uart.h34 #define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
35 #define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
36 #define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
37 #define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
38 #define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
39 #define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
51 __ret = bfin_read32((sport)->port.membase + OFFSET_RX); \
56 #define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
57 #define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
58 #define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
[all …]
Dxilinx_uartps.c195 isrstatus = readl(port->membase + CDNS_UART_ISR_OFFSET); in cdns_uart_isr()
203 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & in cdns_uart_isr()
205 if (!readl(port->membase + CDNS_UART_FIFO_OFFSET)) { in cdns_uart_isr()
211 port->membase + CDNS_UART_ISR_OFFSET); in cdns_uart_isr()
224 while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & in cdns_uart_isr()
226 data = readl(port->membase + CDNS_UART_FIFO_OFFSET); in cdns_uart_isr()
277 port->membase + CDNS_UART_IDR_OFFSET); in cdns_uart_isr()
290 port->membase + CDNS_UART_FIFO_OFFSET); in cdns_uart_isr()
308 writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET); in cdns_uart_isr()
398 mreg = readl(port->membase + CDNS_UART_MR_OFFSET); in cdns_uart_set_baud_rate()
[all …]
Dnetx-serial.c121 val = readl(port->membase + UART_CR); in netx_stop_tx()
122 writel(val & ~CR_TIE, port->membase + UART_CR); in netx_stop_tx()
128 val = readl(port->membase + UART_CR); in netx_stop_rx()
129 writel(val & ~CR_RIE, port->membase + UART_CR); in netx_stop_rx()
135 val = readl(port->membase + UART_CR); in netx_enable_ms()
136 writel(val | CR_MSIE, port->membase + UART_CR); in netx_enable_ms()
144 writel(port->x_char, port->membase + UART_DR); in netx_transmit_buffer()
158 writel(xmit->buf[xmit->tail], port->membase + UART_DR); in netx_transmit_buffer()
164 } while (!(readl(port->membase + UART_FR) & FR_TXFF)); in netx_transmit_buffer()
173 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR); in netx_start_tx()
[all …]
Dimx.c296 ucr->ucr1 = readl(port->membase + UCR1); in imx_port_ucrs_save()
297 ucr->ucr2 = readl(port->membase + UCR2); in imx_port_ucrs_save()
298 ucr->ucr3 = readl(port->membase + UCR3); in imx_port_ucrs_save()
305 writel(ucr->ucr1, port->membase + UCR1); in imx_port_ucrs_restore()
306 writel(ucr->ucr2, port->membase + UCR2); in imx_port_ucrs_restore()
307 writel(ucr->ucr3, port->membase + UCR3); in imx_port_ucrs_restore()
371 temp = readl(port->membase + UCR1); in imx_stop_tx()
372 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); in imx_stop_tx()
376 readl(port->membase + USR2) & USR2_TXDC) { in imx_stop_tx()
377 temp = readl(port->membase + UCR2); in imx_stop_tx()
[all …]
Dmcf.c66 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ? in mcf_tx_empty()
77 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ? in mcf_get_mctrl()
95 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_set_mctrl()
97 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0); in mcf_set_mctrl()
108 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR); in mcf_start_tx()
110 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_start_tx()
113 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_start_tx()
123 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_tx()
133 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_rx()
144 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR); in mcf_break_ctl()
[all …]
Dfsl_lpuart.c289 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
291 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
298 temp = lpuart32_read(port->membase + UARTCTRL); in lpuart32_stop_tx()
300 lpuart32_write(temp, port->membase + UARTCTRL); in lpuart32_stop_tx()
307 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
315 temp = lpuart32_read(port->membase + UARTCTRL); in lpuart32_stop_rx()
316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL); in lpuart32_stop_rx()
353 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) { in lpuart_pio_tx()
354 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); in lpuart_pio_tx()
[all …]
Dtimbuart.c54 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
55 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
61 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
62 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
76 u32 isr = ioread32(port->membase + TIMBUART_ISR); in timbuart_tx_empty()
84 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | in timbuart_flush_buffer()
87 iowrite8(ctl, port->membase + TIMBUART_CTRL); in timbuart_flush_buffer()
88 iowrite32(TXBF, port->membase + TIMBUART_ISR); in timbuart_flush_buffer()
96 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) { in timbuart_rx_chars()
97 u8 ch = ioread8(port->membase + TIMBUART_RXFIFO); in timbuart_rx_chars()
[all …]
Dlpc32xx_hs.c111 port->membase))) == 0) in wait_for_xmit_empty()
125 port->membase))) < 32) in wait_for_xmit_ready()
136 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); in lpc32xx_hsuart_console_putchar()
176 if (!port->membase) in lpc32xx_hsuart_console_setup()
253 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && in __serial_uart_flush()
255 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_uart_flush()
264 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
272 LPC32XX_HSUART_IIR(port->membase)); in __serial_lpc32xx_rx()
280 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
294 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_tx()
[all …]
Damba-pl010.c82 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
84 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx()
93 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
95 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx()
104 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
106 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_rx()
114 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms()
116 writel(cr, uap->port.membase + UART010_CR); in pl010_disable_ms()
125 cr = readb(uap->port.membase + UART010_CR); in pl010_enable_ms()
127 writel(cr, uap->port.membase + UART010_CR); in pl010_enable_ms()
[all …]
Dmeson_uart.c102 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
110 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
112 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
119 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
121 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
133 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
136 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
151 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { in meson_uart_start_tx()
153 writel(port->x_char, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
163 writel(ch, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
[all …]
Ddigicolor-usart.c89 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_tx_full()
95 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_rx_empty()
101 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
104 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
109 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
112 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
117 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
120 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
131 writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET); in digicolor_rx_poll()
149 ch = readb_relaxed(port->membase + UA_EMI_REC); in digicolor_uart_rx()
[all …]
Dlantiq.c153 ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()
162 fifocnt = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; in lqasc_rx_chars()
165 ch = ltq_r8(port->membase + LTQ_ASC_RBUF); in lqasc_rx_chars()
166 rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) in lqasc_rx_chars()
179 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
183 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
188 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
226 while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & in lqasc_tx_chars()
229 ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); in lqasc_tx_chars()
239 port->membase + LTQ_ASC_TBUF); in lqasc_tx_chars()
[all …]
Dmxs-auart.c298 while (!(readl(s->port.membase + AUART_STAT) & in mxs_auart_tx_chars()
303 s->port.membase + AUART_DATA); in mxs_auart_tx_chars()
310 s->port.membase + AUART_DATA); in mxs_auart_tx_chars()
320 s->port.membase + AUART_INTR_CLR); in mxs_auart_tx_chars()
323 s->port.membase + AUART_INTR_SET); in mxs_auart_tx_chars()
335 c = readl(s->port.membase + AUART_DATA); in mxs_auart_rx_char()
336 stat = readl(s->port.membase + AUART_STAT); in mxs_auart_rx_char()
371 writel(stat, s->port.membase + AUART_STAT); in mxs_auart_rx_char()
379 stat = readl(s->port.membase + AUART_STAT); in mxs_auart_rx_chars()
385 writel(stat, s->port.membase + AUART_STAT); in mxs_auart_rx_chars()
[all …]
Daltera_jtaguart.c68 return (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & in altera_jtaguart_tx_empty()
87 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_start_tx()
96 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_stop_tx()
105 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_stop_rx()
127 while ((status = readl(port->membase + ALTERA_JTAGUART_DATA_REG)) & in altera_jtaguart_rx_chars()
151 writel(port->x_char, port->membase + ALTERA_JTAGUART_DATA_REG); in altera_jtaguart_tx_chars()
159 count = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & in altera_jtaguart_tx_chars()
168 port->membase + ALTERA_JTAGUART_DATA_REG); in altera_jtaguart_tx_chars()
179 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_tx_chars()
190 isr = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) >> in altera_jtaguart_interrupt()
[all …]
Damba-pl011.c199 status = readw(uap->port.membase + UART01x_FR); in pl011_fifo_to_tty()
204 ch = readw(uap->port.membase + UART01x_DR) | in pl011_fifo_to_tty()
441 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_callback()
555 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_refill()
591 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_irq()
593 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_tx_irq()
603 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_tx_irq()
617 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_stop()
643 writew(uap->im, uap->port.membase + in pl011_dma_tx_start()
650 uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
[all …]
Dmen_z135_uart.c148 reg = ioread32(port->membase + addr); in men_z135_reg_set()
150 iowrite32(reg, port->membase + addr); in men_z135_reg_set()
170 reg = ioread32(port->membase + addr); in men_z135_reg_clr()
172 iowrite32(reg, port->membase + addr); in men_z135_reg_clr()
231 stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); in get_rx_fifo_content()
274 memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room); in men_z135_handle_rx()
277 iowrite32(room, port->membase + MEN_Z135_RX_CTRL); in men_z135_handle_rx()
323 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); in men_z135_handle_tx()
357 memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n); in men_z135_handle_tx()
361 iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL); in men_z135_handle_tx()
[all …]
Dstm32-usart.c137 val = readl_relaxed(port->membase + reg); in stm32_set_bits()
139 writel_relaxed(val, port->membase + reg); in stm32_set_bits()
146 val = readl_relaxed(port->membase + reg); in stm32_clr_bits()
148 writel_relaxed(val, port->membase + reg); in stm32_clr_bits()
161 while ((sr = readl_relaxed(port->membase + USART_SR)) & USART_SR_RXNE) { in stm32_receive_chars()
163 c = readl_relaxed(port->membase + USART_DR); in stm32_receive_chars()
205 writel_relaxed(port->x_char, port->membase + USART_DR); in stm32_transmit_chars()
221 writel_relaxed(xmit->buf[xmit->tail], port->membase + USART_DR); in stm32_transmit_chars()
239 sr = readl_relaxed(port->membase + USART_SR); in stm32_interrupt()
254 return readl_relaxed(port->membase + USART_SR) & USART_SR_TXE; in stm32_tx_empty()
[all …]
Dpch_uart.c230 void __iomem *membase; member
339 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); in port_show_regs()
341 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); in port_show_regs()
343 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); in port_show_regs()
345 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); in port_show_regs()
347 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); in port_show_regs()
349 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); in port_show_regs()
352 ioread8(priv->membase + PCH_UART_BRCSR)); in port_show_regs()
354 lcr = ioread8(priv->membase + UART_LCR); in port_show_regs()
355 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in port_show_regs()
[all …]
Dclps711x.c113 ch = readw(port->membase + UARTDR_OFFSET); in uart_clps711x_int_rx()
159 writew(port->x_char, port->membase + UARTDR_OFFSET); in uart_clps711x_int_tx()
176 writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET); in uart_clps711x_int_tx()
220 ubrlcr = readl(port->membase + UBRLCR_OFFSET); in uart_clps711x_break_ctl()
225 writel(ubrlcr, port->membase + UBRLCR_OFFSET); in uart_clps711x_break_ctl()
244 writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK, in uart_clps711x_startup()
245 port->membase + UBRLCR_OFFSET); in uart_clps711x_startup()
317 writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET); in uart_clps711x_set_termios()
369 writew(ch, port->membase + UARTDR_OFFSET); in uart_clps711x_console_putchar()
410 ubrlcr = readl(port->membase + UBRLCR_OFFSET); in uart_clps711x_console_setup()
[all …]
Dserial_ks8695.c47 #define UART_GET_CHAR(p) (__raw_readl((p)->membase + KS8695_URRB) & 0xFF)
48 #define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + KS8695_URTH)
49 #define UART_GET_FCR(p) __raw_readl((p)->membase + KS8695_URFC)
50 #define UART_PUT_FCR(p, c) __raw_writel((c), (p)->membase + KS8695_URFC)
51 #define UART_GET_MSR(p) __raw_readl((p)->membase + KS8695_URMS)
52 #define UART_GET_LSR(p) __raw_readl((p)->membase + KS8695_URLS)
53 #define UART_GET_LCR(p) __raw_readl((p)->membase + KS8695_URLC)
54 #define UART_PUT_LCR(p, c) __raw_writel((c), (p)->membase + KS8695_URLC)
55 #define UART_GET_MCR(p) __raw_readl((p)->membase + KS8695_URMC)
56 #define UART_PUT_MCR(p, c) __raw_writel((c), (p)->membase + KS8695_URMC)
[all …]
Dsa1100.c60 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
61 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
62 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
63 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
64 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
65 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
66 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
68 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
69 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
70 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
[all …]
Dmux.c71 #define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + IO_DATA_REG_OFFSET)
72 #define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET)
240 data = __raw_readl(port->membase + IO_DATA_REG_OFFSET); in mux_read()
366 if(port->membase == NULL) in mux_verify_port()
481 port->membase = ioremap_nocache(port->mapbase, MUX_LINE_OFFSET); in mux_probe()
523 if(port->membase) in mux_remove()
524 iounmap(port->membase); in mux_remove()
Dbcm63xx_uart.c83 return __raw_readl(port->membase + offset); in bcm_uart_readl()
89 __raw_writel(value, port->membase + offset); in bcm_uart_writel()
743 if (!port->membase) in bcm_console_setup()
782 if (!device->port.membase) in bcm_early_console_setup()
823 if (port->membase) in bcm_uart_probe()
832 port->membase = devm_ioremap_resource(&pdev->dev, res_mem); in bcm_uart_probe()
833 if (IS_ERR(port->membase)) in bcm_uart_probe()
834 return PTR_ERR(port->membase); in bcm_uart_probe()
857 ports[pdev->id].membase = NULL; in bcm_uart_probe()
871 ports[pdev->id].membase = NULL; in bcm_uart_remove()
Dvt8500_serial.c127 writel(val, port->membase + off); in vt8500_write()
132 return readl(port->membase + off); in vt8500_read()
182 c = readw(port->membase + VT8500_RXFIFO) & 0x3ff; in handle_rx()
210 writeb(port->x_char, port->membase + VT8500_TXFIFO); in handle_tx()
223 writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO); in handle_tx()
505 writeb(c, port->membase + VT8500_TXFIFO); in vt8500_console_putchar()
685 vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres); in vt8500_serial_probe()
686 if (IS_ERR(vt8500_port->uart.membase)) in vt8500_serial_probe()
687 return PTR_ERR(vt8500_port->uart.membase); in vt8500_serial_probe()
Duartlite.c99 return reg_ops->in(port->membase + offset); in uart_in32()
106 reg_ops->out(val, port->membase + offset); in uart_out32()
321 iounmap(port->membase); in ulite_release_port()
322 port->membase = NULL; in ulite_release_port()
337 port->membase = ioremap(port->mapbase, ULITE_REGION); in ulite_request_port()
338 if (!port->membase) { in ulite_request_port()
491 if (!port->membase) { in ulite_console_setup()
579 port->membase = NULL; in ulite_assign()
Daltera_uart.c90 return readl(port->membase + (reg << port->regshift)); in altera_uart_readl()
95 writel(dat, port->membase + (reg << port->regshift)); in altera_uart_writel()
334 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG); in altera_uart_startup()
350 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG); in altera_uart_shutdown()
439 writel(c, port->membase + ALTERA_UART_TXDATA_REG); in altera_uart_console_putc()
461 if (!port->membase) in altera_uart_console_setup()
556 port->membase = ioremap(port->mapbase, ALTERA_UART_SIZE); in altera_uart_probe()
557 if (!port->membase) in altera_uart_probe()
Dsprd_serial.c126 return readl_relaxed(port->membase + offset); in serial_in()
131 writel_relaxed(value, port->membase + offset); in serial_out()
603 !(readl(port->membase + SPRD_LSR) & SPRD_LSR_TX_OVER)) in sprd_putc()
606 writeb(c, port->membase + SPRD_TXD); in sprd_putc()
621 if (!device->port.membase) in sprd_early_console_setup()
728 up->membase = devm_ioremap_resource(&pdev->dev, res); in sprd_probe()
729 if (IS_ERR(up->membase)) in sprd_probe()
730 return PTR_ERR(up->membase); in sprd_probe()
Dsamsung.h116 #define portaddr(port, reg) ((port)->membase + (reg))
118 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
Dst-asc.c155 return readl_relaxed(port->membase + offset); in asc_in()
157 return readl(port->membase + offset); in asc_in()
164 writel_relaxed(value, port->membase + offset); in asc_out()
166 writel(value, port->membase + offset); in asc_out()
679 port->membase = devm_ioremap_resource(&pdev->dev, res); in asc_init_port()
680 if (IS_ERR(port->membase)) in asc_init_port()
681 return PTR_ERR(port->membase); in asc_init_port()
853 if (ascport->port.mapbase == 0 || ascport->port.membase == NULL) in asc_console_setup()
Dvr41xx_siu.c72 #define siu_read(port, offset) readb((port)->membase + (offset))
73 #define siu_write(port, offset, value) writeb((value), (port)->membase + (offset))
451 if (port->membase == NULL) in siu_startup()
633 iounmap(port->membase); in siu_release_port()
634 port->membase = NULL; in siu_release_port()
652 port->membase = ioremap(port->mapbase, size); in siu_request_port()
653 if (port->membase == NULL) { in siu_request_port()
797 if (port->membase == NULL) { in siu_console_setup()
800 port->membase = ioremap(port->mapbase, siu_port_size(port)); in siu_console_setup()
Dsb1250-duart.c127 void __iomem *csr = sport->port.membase + reg; in __read_sbdchn()
141 void __iomem *csr = sport->port.membase + reg; in __write_sbdchn()
661 iounmap(uport->membase); in sbd_release_port()
662 uport->membase = NULL; in sbd_release_port()
676 if (!uport->membase) in sbd_map_port()
677 uport->membase = ioremap_nocache(uport->mapbase, in sbd_map_port()
679 if (!uport->membase) { in sbd_map_port()
689 iounmap(uport->membase); in sbd_map_port()
690 uport->membase = NULL; in sbd_map_port()
Dserial_txx9.c177 return __raw_readl(up->port.membase + offset); in sio_in()
188 __raw_writel(value, up->port.membase + offset); in sio_out()
769 up->port.membase = ioremap(up->port.mapbase, size); in serial_txx9_request_resource()
770 if (!up->port.membase) { in serial_txx9_request_resource()
795 iounmap(up->port.membase); in serial_txx9_release_resource()
796 up->port.membase = NULL; in serial_txx9_release_resource()
1044 uart->port.membase = port->membase; in serial_txx9_register_port()
1078 uart->port.membase = NULL; in serial_txx9_unregister_port()
1095 port.membase = p->membase; in serial_txx9_probe()
Dmsm_serial.h140 writel_relaxed(val, port->membase + off); in msm_write()
146 return readl_relaxed(port->membase + off); in msm_read()
Ddz.c104 void __iomem *addr = dport->port.membase + offset; in dz_in()
111 void __iomem *addr = dport->port.membase + offset; in dz_out()
668 iounmap(uport->membase); in dz_release_port()
669 uport->membase = NULL; in dz_release_port()
678 if (!uport->membase) in dz_map_port()
679 uport->membase = ioremap_nocache(uport->mapbase, in dz_map_port()
681 if (!uport->membase) { in dz_map_port()
Darc_uart.c75 #define RBASE(port, reg) (port->membase + reg)
507 if (!port->membase) in arc_serial_console_setup()
566 if (!dev->port.membase) in arc_early_console_setup()
615 port->membase = of_iomap(np, 0); in arc_serial_probe()
616 if (!port->membase) in arc_serial_probe()
Dmsm_serial.c561 ioread32_rep(port->membase + UARTDM_RF, buf, 1); in msm_handle_rx_dm()
662 tf = port->membase + UARTDM_TF; in msm_handle_tx_pio()
664 tf = port->membase + UART_TF; in msm_handle_tx_pio()
711 tf = port->membase + UARTDM_TF; in msm_handle_tx()
713 tf = port->membase + UART_TF; in msm_handle_tx()
1129 iounmap(port->membase); in msm_release_port()
1130 port->membase = NULL; in msm_release_port()
1149 port->membase = ioremap(port->mapbase, size); in msm_request_port()
1150 if (!port->membase) { in msm_request_port()
1375 tf = port->membase + UARTDM_TF; in __msm_console_write()
[all …]
Defm32-uart.c93 writel_relaxed(value, efm_port->port.membase + offset); in efm32_uart_write32()
99 return readl_relaxed(efm_port->port.membase + offset); in efm32_uart_read32()
438 iounmap(port->membase); in efm32_uart_release_port()
446 port->membase = ioremap(port->mapbase, 60); in efm32_uart_request_port()
447 if (!efm_port->port.membase) { in efm32_uart_request_port()
465 iounmap(port->membase); in efm32_uart_request_port()
Dearlycon.c121 port->membase = earlycon_map(port->mapbase, 64); in register_earlycon()
210 port->membase = earlycon_map(addr, SZ_4K); in of_setup_earlycon()
Dar933x_uart.c63 return readl(up->port.membase + offset); in ar933x_uart_read()
69 writel(value, up->port.membase + offset); in ar933x_uart_write()
675 port->membase = devm_ioremap_resource(&pdev->dev, mem_res); in ar933x_uart_probe()
676 if (IS_ERR(port->membase)) in ar933x_uart_probe()
677 return PTR_ERR(port->membase); in ar933x_uart_probe()
Dsccnxp.c217 return readb(port->membase + (reg << port->regshift)); in sccnxp_read()
222 writeb(v, port->membase + (reg << port->regshift)); in sccnxp_write()
856 void __iomem *membase; in sccnxp_probe() local
859 membase = devm_ioremap_resource(&pdev->dev, res); in sccnxp_probe()
860 if (IS_ERR(membase)) in sccnxp_probe()
861 return PTR_ERR(membase); in sccnxp_probe()
951 s->port[i].membase = membase; in sccnxp_probe()
Dzs.c143 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; in read_zsreg()
158 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; in write_zsreg()
172 void __iomem *data = zport->port.membase + in read_zsdata()
183 void __iomem *data = zport->port.membase + in write_zsdata()
986 iounmap(uport->membase); in zs_release_port()
987 uport->membase = 0; in zs_release_port()
993 if (!uport->membase) in zs_map_port()
994 uport->membase = ioremap_nocache(uport->mapbase, in zs_map_port()
996 if (!uport->membase) { in zs_map_port()
Dmpc52xx_uart.c80 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
768 #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
1282 iounmap(port->membase); in mpc52xx_uart_release_port()
1283 port->membase = NULL; in mpc52xx_uart_release_port()
1295 port->membase = ioremap(port->mapbase, in mpc52xx_uart_request_port()
1298 if (!port->membase) in mpc52xx_uart_request_port()
1319 iounmap(port->membase); in mpc52xx_uart_request_port()
1320 port->membase = NULL; in mpc52xx_uart_request_port()
1659 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); in mpc52xx_console_setup()
1662 if (port->membase == NULL) in mpc52xx_console_setup()
[all …]
Dsunsab.c976 up->port.membase = of_ioremap(&op->resource[0], offset, in sunsab_init_one()
979 if (!up->port.membase) in sunsab_init_one()
981 up->regs = (union sab82532_async_regs __iomem *) up->port.membase; in sunsab_init_one()
1066 up[1].port.membase, in sab_probe()
1070 up[0].port.membase, in sab_probe()
1083 up[1].port.membase, in sab_remove()
1086 up[0].port.membase, in sab_remove()
Dapbuart.h45 #define APBBASE(port) ((struct grlib_apbuart_regs_map *)((port)->membase))
Dsunsu.c117 return readb(up->port.membase + offset); in serial_in()
147 writeb(value, up->port.membase + offset); in serial_out()
1443 up->port.membase = of_ioremap(rp, 0, up->reg_size, "su"); in su_probe()
1444 if (!up->port.membase) { in su_probe()
1462 up->port.membase, up->reg_size); in su_probe()
1502 of_iounmap(&op->resource[0], up->port.membase, up->reg_size); in su_probe()
1522 if (up->port.membase) in su_remove()
1523 of_iounmap(&op->resource[0], up->port.membase, up->reg_size); in su_remove()
Dbfin_uart.c1237 if (!(bfin_earlyprintk_port.port.membase in bfin_serial_probe()
1271 uart->port.membase = ioremap(res->start, resource_size(res)); in bfin_serial_probe()
1272 if (!uart->port.membase) { in bfin_serial_probe()
1357 iounmap(uart->port.membase); in bfin_serial_probe()
1376 iounmap(uart->port.membase); in bfin_serial_remove()
1445 bfin_earlyprintk_port.port.membase = ioremap(res->start, in bfin_earlyprintk_probe()
1447 if (!bfin_earlyprintk_port.port.membase) { in bfin_earlyprintk_probe()
1498 if (!bfin_earlyprintk_port.port.membase) in bfin_earlyserial_init()
Datmel_serial.c205 return __raw_readl(port->membase + reg); in atmel_uart_readl()
210 __raw_writel(value, port->membase + reg); in atmel_uart_writel()
218 return __raw_readl(port->membase + ATMEL_US_RHR); in atmel_uart_read_char()
223 __raw_writel(value, port->membase + ATMEL_US_THR); in atmel_uart_write_char()
230 return __raw_readb(port->membase + ATMEL_US_RHR); in atmel_uart_read_char()
235 __raw_writeb(value, port->membase + ATMEL_US_THR); in atmel_uart_write_char()
2264 iounmap(port->membase); in atmel_release_port()
2265 port->membase = NULL; in atmel_release_port()
2281 port->membase = ioremap(port->mapbase, size); in atmel_request_port()
2282 if (port->membase == NULL) { in atmel_request_port()
[all …]
Dm32r_sio.c850 iounmap(up->port.membase); in m32r_sio_release_port()
851 up->port.membase = NULL; in m32r_sio_release_port()
889 up->port.membase = ioremap(up->port.mapbase, size); in m32r_sio_request_port()
890 if (!up->port.membase) in m32r_sio_request_port()
960 up->port.membase = old_serial_port[i].iomem_base; in m32r_sio_init_ports()
Dbfin_sport_uart.c794 sport->port.membase = ioremap(res->start, resource_size(res)); in sport_uart_probe()
795 if (!sport->port.membase) { in sport_uart_probe()
845 iounmap(sport->port.membase); in sport_uart_probe()
865 iounmap(sport->port.membase); in sport_uart_remove()
Dsamsung.c979 port, (unsigned long long)port->mapbase, port->membase); in s3c24xx_serial_startup()
1027 port, (unsigned long long)port->mapbase, port->membase); in s3c64xx_serial_startup()
1705 port->membase = devm_ioremap(port->dev, res->start, resource_size(res)); in s3c24xx_serial_init_port()
1706 if (!port->membase) { in s3c24xx_serial_init_port()
1759 &port->mapbase, port->membase, port->irq, in s3c24xx_serial_init_port()
2402 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE)) in samsung_early_busyuart()
2410 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask) in samsung_early_busyuart_fifo()
2416 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) in samsung_early_putc()
2421 writeb(c, port->membase + S3C2410_UTXH); in samsung_early_putc()
2434 if (!device->port.membase) in samsung_early_console_setup()
Dsh-sci.c394 return ioread8(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
396 return ioread16(p->membase + (reg->offset << p->regshift)); in sci_serial_in()
408 iowrite8(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
410 iowrite16(value, p->membase + (reg->offset << p->regshift)); in sci_serial_out()
2121 if (port->membase) in sci_remap_port()
2125 port->membase = ioremap_nocache(port->mapbase, sport->reg_size); in sci_remap_port()
2126 if (unlikely(!port->membase)) { in sci_remap_port()
2136 port->membase = (void __iomem *)(uintptr_t)port->mapbase; in sci_remap_port()
2147 iounmap(port->membase); in sci_release_port()
2148 port->membase = NULL; in sci_release_port()
Dpxa.c63 return readl(up->port.membase + offset); in serial_in()
69 writel(value, up->port.membase + offset); in serial_out()
896 sport->port.membase = ioremap(mmres->start, resource_size(mmres)); in serial_pxa_probe()
897 if (!sport->port.membase) { in serial_pxa_probe()
Dserial-tegra.c144 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
150 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
1305 u->membase = devm_ioremap_resource(&pdev->dev, resource); in tegra_uart_probe()
1306 if (IS_ERR(u->membase)) in tegra_uart_probe()
1307 return PTR_ERR(u->membase); in tegra_uart_probe()
Dnwpserial.c379 up->port.membase = port->membase; in nwpserial_register_port()
Dip22zilog.c90 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
1102 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB; in ip22zilog_prepare()
1103 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA; in ip22zilog_prepare()
Dpnx8xxx_uart.c71 return (__raw_readl(sport->port.membase + offset)); in serial_in()
76 __raw_writel(value, sport->port.membase + offset); in serial_out()
Dpmac_zilog.c1429 uap->port.membase = ioremap(uap->port.mapbase, 0x1000); in pmz_init_port()
1431 uap->control_reg = uap->port.membase; in pmz_init_port()
1727 uap->port.membase = (unsigned char __iomem *) r_ports->start; in pmz_init_port()
1736 uap->control_reg = uap->port.membase; in pmz_init_port()
Domap-serial.c185 return readw(up->port.membase + offset); in serial_in()
191 writew(value, up->port.membase + offset); in serial_out()
1485 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift)); in omap_serial_fill_features_erratas()
1670 up->port.membase = base; in serial_omap_probe()
Dsirfsoc_uart.h440 #define portaddr(port, reg) ((port)->membase + (reg))
Dsunhv.c555 port->membase = (unsigned char __iomem *) __pa(port); in hv_probe()
/linux-4.4.14/drivers/atm/
Didt77252.h352 void __iomem *membase; /* SAR's memory base address */ member
438 #define SAR_REG_DR0 (card->membase + 0x00)
439 #define SAR_REG_DR1 (card->membase + 0x04)
440 #define SAR_REG_DR2 (card->membase + 0x08)
441 #define SAR_REG_DR3 (card->membase + 0x0C)
442 #define SAR_REG_CMD (card->membase + 0x10)
443 #define SAR_REG_CFG (card->membase + 0x14)
444 #define SAR_REG_STAT (card->membase + 0x18)
445 #define SAR_REG_RSQB (card->membase + 0x1C)
446 #define SAR_REG_RSQT (card->membase + 0x20)
[all …]
Dnicstar.c104 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
213 writel(0x00000000, card->membase + CFG); in nicstar_remove_one()
252 iounmap(card->membase); in nicstar_remove_one()
317 writel(sram_address, card->membase + CMD); in ns_read_sram()
319 data = readl(card->membase + DR0); in ns_read_sram()
335 writel(*(value++), card->membase + i); in ns_write_sram()
341 writel(sram_address, card->membase + CMD); in ns_write_sram()
355 unsigned long membase; in ns_init_card() local
390 membase = pci_resource_start(pcidev, 1); in ns_init_card()
391 card->membase = ioremap(membase, NS_IOREMAP_SIZE); in ns_init_card()
[all …]
Dhe.c176 #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
177 #define he_readl(dev, reg) readl((dev)->membase + (reg))
976 unsigned long membase; in he_start() local
989 membase = pci_resource_start(pci_dev, 0); in he_start()
990 HPRINTK("membase = 0x%lx irq = %d.\n", membase, pci_dev->irq); in he_start()
1050 if (!(he_dev->membase = ioremap(membase, HE_REGMAP_SIZE))) { in he_start()
1537 if (he_dev->membase) { in he_stop()
1603 if (he_dev->membase) in he_stop()
1604 iounmap(he_dev->membase); in he_stop()
2793 val = readl(he_dev->membase + HOST_CNTL); in read_prom_byte()
Dhorizon.h409 u32 * membase; member
Didt77252.c3102 if (card->membase) in deinit_card()
3103 iounmap(card->membase); in deinit_card()
3605 unsigned long membase, srambase; in idt77252_init_one() local
3634 membase = pci_resource_start(pcidev, 1); in idt77252_init_one()
3646 card->membase = ioremap(membase, 1024); in idt77252_init_one()
3647 if (!card->membase) { in idt77252_init_one()
3691 'A' + card->revision - 1 : '?', membase, srambase, in idt77252_init_one()
3727 iounmap(card->membase); in idt77252_init_one()
Dambassador.c314 dev->membase[addr / sizeof(u32)] = data; in wr_plain()
322 u32 data = dev->membase[addr / sizeof(u32)]; in rd_plain()
334 dev->membase[addr / sizeof(u32)] = be; in wr_mem()
342 __be32 be = dev->membase[addr / sizeof(u32)]; in rd_mem()
2149 dev->membase = bus_to_virt(pci_resource_start(pci_dev, 0)); in setup_dev()
Dambassador.h631 u32 * membase; member
Dhorizon.c2669 u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1)); in hrz_probe() local
2707 iobase, irq, membase); in hrz_probe()
2739 dev->membase = membase; in hrz_probe()
/linux-4.4.14/drivers/net/ethernet/allwinner/
Dsun4i-emac.c72 void __iomem *membase; member
95 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
99 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
108 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
112 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
193 writel(0, db->membase + EMAC_CTL_REG); in emac_reset()
195 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); in emac_reset()
267 reg_val = readl(db->membase + EMAC_TX_MODE_REG); in emac_setup()
270 db->membase + EMAC_TX_MODE_REG); in emac_setup()
274 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); in emac_setup()
[all …]
/linux-4.4.14/drivers/isdn/hisax/
Dtelespci.c183 return (readisac(cs->hw.teles0.membase, offset)); in ReadISAC()
189 writeisac(cs->hw.teles0.membase, offset, value); in WriteISAC()
195 read_fifo_isac(cs->hw.teles0.membase, data, size); in ReadISACfifo()
201 write_fifo_isac(cs->hw.teles0.membase, data, size); in WriteISACfifo()
207 return (readhscx(cs->hw.teles0.membase, hscx, offset)); in ReadHSCX()
213 writehscx(cs->hw.teles0.membase, hscx, offset, value); in WriteHSCX()
220 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
221 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
222 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
223 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
[all …]
Dteles0.c100 return (readisac(cs->hw.teles0.membase, offset)); in ReadISAC()
106 writeisac(cs->hw.teles0.membase, offset, value); in WriteISAC()
112 read_fifo_isac(cs->hw.teles0.membase, data, size); in ReadISACfifo()
118 write_fifo_isac(cs->hw.teles0.membase, data, size); in WriteISACfifo()
124 return (readhscx(cs->hw.teles0.membase, hscx, offset)); in ReadHSCX()
130 writehscx(cs->hw.teles0.membase, hscx, offset, value); in WriteHSCX()
137 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
138 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
139 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
140 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
[all …]
/linux-4.4.14/drivers/net/phy/
Dmdio-sun4i.c35 void __iomem *membase; member
46 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_read()
48 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
52 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { in sun4i_mdio_read()
59 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
61 value = readl(data->membase + EMAC_MAC_MRDD_REG); in sun4i_mdio_read()
73 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_write()
75 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
79 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { in sun4i_mdio_write()
86 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
[all …]
/linux-4.4.14/drivers/gpio/
Dgpio-timberdale.c46 void __iomem *membase; member
60 reg = ioread32(tgpio->membase + offset); in timbgpio_update_bit()
67 iowrite32(reg, tgpio->membase + offset); in timbgpio_update_bit()
83 value = ioread32(tgpio->membase + TGPIOVAL); in timbgpio_gpio_get()
120 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_disable()
132 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_enable()
148 ver = ioread32(tgpio->membase + TGPIO_VER); in timbgpio_irq_type()
152 lvr = ioread32(tgpio->membase + TGPIO_LVR); in timbgpio_irq_type()
153 flr = ioread32(tgpio->membase + TGPIO_FLR); in timbgpio_irq_type()
155 bflr = ioread32(tgpio->membase + TGPIO_BFLR); in timbgpio_irq_type()
[all …]
Dgpio-mvebu.c81 void __iomem *membase; member
102 return mvchip->membase + GPIO_OUT_OFF; in mvebu_gpioreg_out()
107 return mvchip->membase + GPIO_BLINK_EN_OFF; in mvebu_gpioreg_blink()
113 return mvchip->membase + GPIO_IO_CONF_OFF; in mvebu_gpioreg_io_conf()
118 return mvchip->membase + GPIO_IN_POL_OFF; in mvebu_gpioreg_in_pol()
124 return mvchip->membase + GPIO_DATA_IN_OFF; in mvebu_gpioreg_data_in()
135 return mvchip->membase + GPIO_EDGE_CAUSE_OFF; in mvebu_gpioreg_edge_cause()
152 return mvchip->membase + GPIO_EDGE_MASK_OFF; in mvebu_gpioreg_edge_mask()
155 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); in mvebu_gpioreg_edge_mask()
171 return mvchip->membase + GPIO_LEVEL_MASK_OFF; in mvebu_gpioreg_level_mask()
[all …]
/linux-4.4.14/drivers/i2c/busses/
Di2c-uniphier-f.c91 void __iomem *membase; member
118 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo()
132 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); in uniphier_fi2c_drain_rxfifo()
140 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); in uniphier_fi2c_set_irqs()
145 writel(-1, priv->membase + UNIPHIER_FI2C_IC); in uniphier_fi2c_clear_irqs()
155 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_stop()
163 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); in uniphier_fi2c_interrupt()
224 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_interrupt()
254 writel(0, priv->membase + UNIPHIER_FI2C_TBC); in uniphier_fi2c_tx_init()
257 priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_tx_init()
[all …]
Di2c-uniphier.c53 void __iomem *membase; member
83 writel(txdata, priv->membase + UNIPHIER_I2C_DTRM); in uniphier_i2c_xfer_byte()
91 rxdata = readl(priv->membase + UNIPHIER_I2C_DREC); in uniphier_i2c_xfer_byte()
221 if (!(readl(priv->membase + UNIPHIER_I2C_DREC) & in uniphier_i2c_check_bus_busy()
279 writel(val, priv->membase + UNIPHIER_I2C_BRST); in uniphier_i2c_reset()
286 return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) & in uniphier_i2c_get_scl()
295 priv->membase + UNIPHIER_I2C_BRST); in uniphier_i2c_set_scl()
302 return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) & in uniphier_i2c_get_sda()
349 priv->membase + UNIPHIER_I2C_CLK); in uniphier_i2c_clk_init()
369 priv->membase = devm_ioremap_resource(dev, regs); in uniphier_i2c_probe()
[all …]
Di2c-cadence.c119 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
120 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
144 void __iomem *membase; member
893 id->membase = devm_ioremap_resource(&pdev->dev, r_mem); in cdns_i2c_probe()
894 if (IS_ERR(id->membase)) in cdns_i2c_probe()
895 return PTR_ERR(id->membase); in cdns_i2c_probe()
/linux-4.4.14/drivers/input/keyboard/
Dlocomokbd.c87 static inline void locomokbd_charge_all(unsigned long membase) in locomokbd_charge_all() argument
89 locomo_writel(0x00FF, membase + LOCOMO_KSC); in locomokbd_charge_all()
92 static inline void locomokbd_activate_all(unsigned long membase) in locomokbd_activate_all() argument
96 locomo_writel(0, membase + LOCOMO_KSC); in locomokbd_activate_all()
97 r = locomo_readl(membase + LOCOMO_KIC); in locomokbd_activate_all()
99 locomo_writel(r, membase + LOCOMO_KIC); in locomokbd_activate_all()
102 static inline void locomokbd_activate_col(unsigned long membase, int col) in locomokbd_activate_col() argument
109 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_activate_col()
112 static inline void locomokbd_reset_col(unsigned long membase, int col) in locomokbd_reset_col() argument
117 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_reset_col()
[all …]
/linux-4.4.14/drivers/reset/
Dreset-sunxi.c27 void __iomem *membase; member
44 reg = readl(data->membase + (bank * 4)); in sunxi_reset_assert()
45 writel(reg & ~BIT(offset), data->membase + (bank * 4)); in sunxi_reset_assert()
65 reg = readl(data->membase + (bank * 4)); in sunxi_reset_deassert()
66 writel(reg | BIT(offset), data->membase + (bank * 4)); in sunxi_reset_deassert()
99 data->membase = ioremap(res.start, size); in sunxi_reset_init()
100 if (!data->membase) { in sunxi_reset_init()
158 data->membase = devm_ioremap_resource(&pdev->dev, res); in sunxi_reset_probe()
159 if (IS_ERR(data->membase)) in sunxi_reset_probe()
160 return PTR_ERR(data->membase); in sunxi_reset_probe()
Dreset-socfpga.c30 void __iomem *membase; member
48 reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS)); in socfpga_reset_assert()
49 writel(reg | BIT(offset), data->membase + data->modrst_offset + in socfpga_reset_assert()
70 reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS)); in socfpga_reset_deassert()
71 writel(reg & ~BIT(offset), data->membase + data->modrst_offset + in socfpga_reset_deassert()
88 reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS)); in socfpga_reset_status()
121 data->membase = devm_ioremap_resource(&pdev->dev, res); in socfpga_reset_probe()
122 if (IS_ERR(data->membase)) in socfpga_reset_probe()
123 return PTR_ERR(data->membase); in socfpga_reset_probe()
/linux-4.4.14/drivers/dma/
Dtimb_dma.c80 void __iomem *membase; member
97 void __iomem *membase; member
126 ier = ioread32(td->membase + TIMBDMA_IER); in __td_enable_chan_irq()
130 iowrite32(ier, td->membase + TIMBDMA_IER); in __td_enable_chan_irq()
144 isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id); in __td_dma_done_ack()
146 iowrite32(isr, td->membase + TIMBDMA_ISR); in __td_dma_done_ack()
201 td_chan, td_chan->chan.chan_id, td_chan->membase); in __td_start_dma()
206 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR); in __td_start_dma()
207 iowrite32(td_desc->txd.phys, td_chan->membase + in __td_start_dma()
210 iowrite32(td_chan->bytes_per_line, td_chan->membase + in __td_start_dma()
[all …]
Dfsl-edma.c166 void __iomem *membase; member
230 void __iomem *addr = fsl_chan->edma->membase; in fsl_edma_enable_request()
239 void __iomem *addr = fsl_chan->edma->membase; in fsl_edma_disable_request()
361 void __iomem *addr = fsl_chan->edma->membase; in fsl_edma_desc_residue()
433 void __iomem *addr = fsl_chan->edma->membase; in fsl_edma_set_tcd_regs()
660 base_addr = fsl_edma->membase; in fsl_edma_tx_handler()
697 err = edma_readl(fsl_edma, fsl_edma->membase + EDMA_ERR); in fsl_edma_err_handler()
705 fsl_edma->membase + EDMA_CERR); in fsl_edma_err_handler()
857 fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res); in fsl_edma_probe()
858 if (IS_ERR(fsl_edma->membase)) in fsl_edma_probe()
[all …]
Dpch_dma.c100 void __iomem *membase; member
119 readl((pdc)->membase + PDC_##name)
121 writel((val), (pdc)->membase + PDC_##name)
125 void __iomem *membase; member
141 readl((pd)->membase + PCH_DMA_##name)
143 writel((val), (pd)->membase + PCH_DMA_##name)
872 regs = pd->membase = pci_iomap(pdev, 1, 0); in pch_dma_probe()
873 if (!pd->membase) { in pch_dma_probe()
905 pd_chan->membase = &regs->desc[i]; in pch_dma_probe()
942 pci_iounmap(pdev, pd->membase); in pch_dma_probe()
[all …]
/linux-4.4.14/drivers/tty/serial/8250/
D8250_uniphier.c63 return (readl(p->membase + offset) >> valshift) & 0xff; in uniphier_serial_in()
91 writel(value, p->membase + offset); in uniphier_serial_out()
103 tmp = readl(p->membase + offset); in uniphier_serial_out()
106 writel(tmp, p->membase + offset); in uniphier_serial_out()
120 return readl(up->port.membase + offset); in uniphier_serial_dl_read()
127 writel(value, up->port.membase + offset); in uniphier_serial_dl_write()
172 void __iomem *membase; in uniphier_uart_probe() local
182 membase = devm_ioremap(dev, regs->start, resource_size(regs)); in uniphier_uart_probe()
183 if (!membase) in uniphier_uart_probe()
208 up.port.membase = membase; in uniphier_uart_probe()
D8250_early.c44 return readb(port->membase + offset); in serial8250_early_in()
46 return readl(port->membase + (offset << 2)); in serial8250_early_in()
48 return ioread32be(port->membase + (offset << 2)); in serial8250_early_in()
60 writeb(value, port->membase + offset); in serial8250_early_out()
63 writel(value, port->membase + (offset << 2)); in serial8250_early_out()
66 iowrite32be(value, port->membase + (offset << 2)); in serial8250_early_out()
139 if (!(device->port.membase || device->port.iobase)) in early_serial8250_setup()
D8250_em.c43 writeb(value, p->membase); in serial8250_em_serial_out()
49 writel(value, p->membase + ((offset + 1) << 2)); in serial8250_em_serial_out()
56 writel(value, p->membase + (offset << 2)); in serial8250_em_serial_out()
64 return readb(p->membase); in serial8250_em_serial_in()
69 return readl(p->membase + ((offset + 1) << 2)); in serial8250_em_serial_in()
74 return readl(p->membase + (offset << 2)); in serial8250_em_serial_in()
D8250_dw.c100 writeb(value, p->membase + (offset << p->regshift)); in dw8250_serial_out()
110 writeb(value, p->membase + (UART_LCR << p->regshift)); in dw8250_serial_out()
121 unsigned int value = readb(p->membase + (offset << p->regshift)); in dw8250_serial_in()
131 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); in dw8250_serial_inq()
139 __raw_writeq(value, p->membase + (offset << p->regshift)); in dw8250_serial_outq()
141 __raw_readq(p->membase + (UART_LCR << p->regshift)); in dw8250_serial_outq()
152 p->membase + (UART_LCR << p->regshift)); in dw8250_serial_outq()
164 writel(value, p->membase + (offset << p->regshift)); in dw8250_serial_out32()
174 writel(value, p->membase + (UART_LCR << p->regshift)); in dw8250_serial_out32()
185 unsigned int value = readl(p->membase + (offset << p->regshift)); in dw8250_serial_in32()
[all …]
D8250_ingenic.c55 return readl(port->membase + (offset << 2)); in early_in()
60 writel(value, port->membase + (offset << 2)); in early_out()
104 if (!dev->port.membase) in ingenic_early_console_setup()
175 writeb(value, p->membase + (offset << p->regshift)); in ingenic_uart_serial_out()
182 value = readb(p->membase + (offset << p->regshift)); in ingenic_uart_serial_in()
245 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, in ingenic_uart_probe()
247 if (!uart.port.membase) in ingenic_uart_probe()
D8250_mid.c117 chip->regs = p->membase; in dnv_setup()
167 writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */ in mid8250_set_termios()
168 writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */ in mid8250_set_termios()
169 writel(div, p->membase + INTEL_MID_UART_DIV); in mid8250_set_termios()
252 uart.port.membase = pcim_iomap(pdev, bar, 0); in mid8250_probe()
253 if (!uart.port.membase) in mid8250_probe()
D8250_hp300.c118 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE); in hp300_setup_serial_console()
135 port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE); in hp300_setup_serial_console()
177 uart.port.membase = (char *)(uart.port.mapbase + DIO_VIRADDRBASE); in hpdca_init_one()
258 uart.port.membase = (char *)(base + DIO_VIRADDRBASE); in hp300_8250_init()
D8250_mtk.c199 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, in mtk8250_probe()
201 if (!uart.port.membase) in mtk8250_probe()
229 writel(0x0, uart.port.membase + in mtk8250_probe()
312 if (!device->port.membase) in early_mtk8250_setup()
D8250_gsc.c62 uart.port.membase = ioremap_nocache(address, 16); in serial_init_chip()
71 iounmap(uart.port.membase); in serial_init_chip()
D8250_lpc18xx.c102 writel(value, p->membase + offset); in lpc18xx_uart_serial_out()
126 uart.port.membase = devm_ioremap(&pdev->dev, res->start, in lpc18xx_serial_probe()
128 if (!uart.port.membase) in lpc18xx_serial_probe()
D8250_port.c319 return __raw_readl(p->membase + (offset << p->regshift)); in au_serial_in()
329 __raw_writel(value, p->membase + (offset << p->regshift)); in au_serial_out()
335 return __raw_readl(up->port.membase + 0x28); in au_serial_dl_read()
340 __raw_writel(value, up->port.membase + 0x28); in au_serial_dl_write()
362 return readb(p->membase + offset); in mem_serial_in()
368 writeb(value, p->membase + offset); in mem_serial_out()
374 writel(value, p->membase + offset); in mem32_serial_out()
380 return readl(p->membase + offset); in mem32_serial_in()
386 iowrite32be(value, p->membase + offset); in mem32be_serial_out()
392 return ioread32be(p->membase + offset); in mem32be_serial_in()
[all …]
D8250_core.c553 port->membase = old_serial_port[i].iomem_base; in serial8250_isa_init_ports()
719 p->membase = port->membase; in early_serial_setup()
810 uart.port.membase = p->membase; in serial8250_probe()
973 uart->port.membase = up->port.membase; in serial8250_register_8250_port()
D8250_omap.c120 return readl(up->port.membase + (reg << up->port.regshift)); in uart_read()
1094 void __iomem *membase; in omap8250_probe() local
1105 membase = devm_ioremap_nocache(&pdev->dev, regs->start, in omap8250_probe()
1107 if (!membase) in omap8250_probe()
1113 up.port.membase = membase; in omap8250_probe()
D8250_acorn.c74 uart.port.membase = info->vaddr + type->offset[i]; in serial_card_probe()
/linux-4.4.14/arch/mips/ralink/
Dcevt-rt3352.c33 void __iomem *membase; member
49 count = ioread32(sdev->membase + SYSTICK_COUNT); in systick_next_event()
51 iowrite32(count, sdev->membase + SYSTICK_COMPARE); in systick_next_event()
100 iowrite32(0, systick.membase + SYSTICK_CONFIG); in systick_shutdown()
115 systick.membase + SYSTICK_CONFIG); in systick_set_oneshot()
122 systick.membase = of_iomap(np, 0); in ralink_systick_init()
123 if (!systick.membase) in ralink_systick_init()
137 clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name, in ralink_systick_init()
Dtimer.c32 void __iomem *membase; member
40 __raw_writel(val, rt->membase + reg); in rt_timer_w32()
45 return __raw_readl(rt->membase + reg); in rt_timer_r32()
129 rt->membase = devm_ioremap_resource(&pdev->dev, res); in rt_timer_probe()
130 if (IS_ERR(rt->membase)) in rt_timer_probe()
131 return PTR_ERR(rt->membase); in rt_timer_probe()
Dbootrom.c15 static void __iomem *membase = (void __iomem *) KSEG1ADDR(BOOTROM_OFFSET);
19 seq_write(s, membase, BOOTROM_SIZE); in bootrom_show()
/linux-4.4.14/arch/arm/mach-davinci/
Dserial.c39 WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset); in serial_write_reg()
41 __raw_writel(value, p->membase + offset); in serial_write_reg()
93 if (!p->membase && p->mapbase) { in davinci_serial_init()
94 p->membase = ioremap(p->mapbase, SZ_4K); in davinci_serial_init()
96 if (p->membase) in davinci_serial_init()
102 if (p->membase && p->type != PORT_AR7) in davinci_serial_init()
/linux-4.4.14/arch/mips/pmcs-msp71xx/
Dmsp_serial.c54 writeb(value, p->membase + offset); in msp_serial_out()
61 return readb(p->membase + offset); in msp_serial_in()
67 unsigned int iir = readb(p->membase + (UART_IIR << p->regshift)); in msp_serial_handle_irq()
82 (void)readb(p->membase + 0xc0); in msp_serial_handle_irq()
83 writeb(d->last_lcr, p->membase + (UART_LCR << p->regshift)); in msp_serial_handle_irq()
108 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN); in msp_serial_setup()
146 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN); in msp_serial_setup()
/linux-4.4.14/drivers/net/ethernet/sfc/
Dio.h85 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq()
89 return (__force __le64)__raw_readq(efx->membase + reg); in _efx_readq()
96 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed()
100 return (__force __le32)__raw_readl(efx->membase + reg); in _efx_readd()
128 static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase, in efx_sram_writeq() argument
140 __raw_writeq((__force u64)value->u64[0], membase + addr); in efx_sram_writeq()
142 __raw_writel((__force u32)value->u32[0], membase + addr); in efx_sram_writeq()
143 __raw_writel((__force u32)value->u32[1], membase + addr + 4); in efx_sram_writeq()
180 static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase, in efx_sram_readq() argument
188 value->u64[0] = (__force __le64)__raw_readq(membase + addr); in efx_sram_readq()
[all …]
Defx.c1271 efx->membase = ioremap_nocache(efx->membase_phys, mem_map_size); in efx_init_io()
1272 if (!efx->membase) { in efx_init_io()
1282 efx->membase); in efx_init_io()
1302 if (efx->membase) { in efx_fini_io()
1303 iounmap(efx->membase); in efx_fini_io()
1304 efx->membase = NULL; in efx_fini_io()
/linux-4.4.14/arch/x86/platform/ce4100/
Dce4100.c50 return readl(p->membase + offset); in mem_serial_in()
69 ret = readl(p->membase + offset); in ce4100_mem_serial_in()
90 writel(value, p->membase + offset); in ce4100_mem_serial_out()
107 up->membase = in ce4100_serial_fixup()
109 up->membase += up->mapbase & ~PAGE_MASK; in ce4100_serial_fixup()
111 up->membase += port * 0x100; in ce4100_serial_fixup()
/linux-4.4.14/drivers/tty/serial/jsm/
Djsm_driver.c147 brd->membase = pci_resource_start(pdev, 4); in jsm_probe_one()
150 if (brd->membase & 0x1) in jsm_probe_one()
151 brd->membase &= ~0x3; in jsm_probe_one()
153 brd->membase &= ~0xF; in jsm_probe_one()
165 brd->re_map_membase = ioremap(brd->membase, in jsm_probe_one()
199 brd->membase = pci_resource_start(pdev, 0); in jsm_probe_one()
202 if (brd->membase & 1) in jsm_probe_one()
203 brd->membase &= ~0x3; in jsm_probe_one()
205 brd->membase &= ~0xF; in jsm_probe_one()
213 brd->re_map_membase = ioremap(brd->membase, in jsm_probe_one()
Djsm.h152 u64 membase; /* Start of base memory of the card */ member
/linux-4.4.14/drivers/isdn/hardware/avm/
Dt1pci.c73 card->membase = p->membase; in t1pci_add_card()
83 card->mbase = ioremap(card->membase, 64); in t1pci_add_card()
86 card->membase); in t1pci_add_card()
134 card->port, card->irq, card->membase); in t1pci_add_card()
183 cinfo->card ? cinfo->card->membase : 0 in t1pci_procinfo()
203 param.membase = pci_resource_start(dev, 0); in t1pci_probe()
206 param.port, param.irq, param.membase); in t1pci_probe()
211 param.port, param.irq, param.membase); in t1pci_probe()
Db1pci.c175 cinfo->card ? cinfo->card->membase : 0, in b1pciv4_procinfo()
207 card->membase = p->membase; in b1pciv4_probe()
217 card->mbase = ioremap(card->membase, 64); in b1pciv4_probe()
220 card->membase); in b1pciv4_probe()
265 card->port, card->irq, card->membase, card->revision); in b1pciv4_probe()
318 param.membase = pci_resource_start(pdev, 0); in b1pci_pci_probe()
322 param.port, param.irq, param.membase); in b1pci_pci_probe()
330 param.port, param.irq, param.membase); in b1pci_pci_probe()
333 param.membase = 0; in b1pci_pci_probe()
Dc4.c1063 cinfo->card ? cinfo->card->membase : 0 in c4_procinfo()
1079 seq_printf(m, "%-16s 0x%lx\n", "membase", card->membase); in c4_proc_show()
1169 card->membase = p->membase; in c4_add_card()
1179 card->mbase = ioremap(card->membase, 128); in c4_add_card()
1182 card->membase); in c4_add_card()
1232 card->membase); in c4_add_card()
1266 param.membase = pci_resource_start(dev, 0); in c4_probe()
1269 nr, param.port, param.irq, param.membase); in c4_probe()
1274 nr, param.port, param.irq, param.membase); in c4_probe()
Davmcard.h83 unsigned long membase; member
/linux-4.4.14/drivers/clk/sunxi/
Dclk-sun9i-mmc.c35 void __iomem *membase; member
49 void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id; in sun9i_mmc_reset_assert()
71 void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id; in sun9i_mmc_reset_deassert()
110 data->membase = devm_ioremap_resource(&pdev->dev, r); in sun9i_a80_mmc_config_clk_probe()
111 if (IS_ERR(data->membase)) in sun9i_a80_mmc_config_clk_probe()
112 return PTR_ERR(data->membase); in sun9i_a80_mmc_config_clk_probe()
146 data->membase + SUN9I_MMC_WIDTH * i, in sun9i_a80_mmc_config_clk_probe()
/linux-4.4.14/drivers/pinctrl/
Dpinctrl-xway.c465 !gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); in xway_pinconf_get()
473 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) { in xway_pinconf_get()
482 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) in xway_pinconf_get()
491 gpio_getbit(info->membase[0], reg, PORT_PIN(pin))); in xway_pinconf_get()
523 gpio_setbit(info->membase[0], in xway_pinconf_set()
527 gpio_clearbit(info->membase[0], in xway_pinconf_set()
538 gpio_clearbit(info->membase[0], in xway_pinconf_set()
543 gpio_setbit(info->membase[0], reg, PORT_PIN(pin)); in xway_pinconf_set()
550 gpio_clearbit(info->membase[0], in xway_pinconf_set()
554 gpio_setbit(info->membase[0], in xway_pinconf_set()
[all …]
Dpinctrl-falcon.c253 void __iomem *mem = info->membase[PORT(pin)]; in falcon_pinconf_get()
290 void __iomem *mem = info->membase[PORT(pin)]; in falcon_pinconf_set()
338 pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset)))); in falcon_pinconf_dbg_show()
390 if ((port >= PORTS) || (!info->membase[port])) in falcon_mux_apply()
393 pad_w32(info->membase[port], mux, in falcon_mux_apply()
420 if ((id >= PORTS) || (!falcon_info.membase[id])) in pinctrl_falcon_get_range_size()
423 avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL); in pinctrl_falcon_get_range_size()
463 falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev, in pinctrl_falcon_probe()
465 if (IS_ERR(falcon_info.membase[*bank])) in pinctrl_falcon_probe()
466 return PTR_ERR(falcon_info.membase[*bank]); in pinctrl_falcon_probe()
[all …]
Dpinctrl-lantiq.h70 void __iomem *membase[5]; member
/linux-4.4.14/drivers/pinctrl/sunxi/
Dpinctrl-sunxi.c315 val = readl(pctl->membase + sunxi_dlevel_reg(pin)); in sunxi_pconf_group_set()
319 pctl->membase + sunxi_dlevel_reg(pin)); in sunxi_pconf_group_set()
322 val = readl(pctl->membase + sunxi_pull_reg(pin)); in sunxi_pconf_group_set()
325 pctl->membase + sunxi_pull_reg(pin)); in sunxi_pconf_group_set()
328 val = readl(pctl->membase + sunxi_pull_reg(pin)); in sunxi_pconf_group_set()
331 pctl->membase + sunxi_pull_reg(pin)); in sunxi_pconf_group_set()
389 val = readl(pctl->membase + sunxi_mux_reg(pin)); in sunxi_pmx_set()
392 pctl->membase + sunxi_mux_reg(pin)); in sunxi_pmx_set()
467 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; in sunxi_pinctrl_gpio_get()
486 regval = readl(pctl->membase + reg); in sunxi_pinctrl_gpio_set()
[all …]
Dpinctrl-sunxi.h117 void __iomem *membase; member
/linux-4.4.14/drivers/spi/
Dspi-sh-sci.c31 void __iomem *membase; member
37 #define SCSPTR(sp) (sp->membase + 0x1c)
154 sp->membase = ioremap(r->start, resource_size(r)); in sh_sci_spi_probe()
155 if (!sp->membase) { in sh_sci_spi_probe()
167 iounmap(sp->membase); in sh_sci_spi_probe()
180 iounmap(sp->membase); in sh_sci_spi_remove()
Dspi-txx9.c80 void __iomem *membase; member
89 return __raw_readl(c->membase + reg); in txx9spi_rd()
93 __raw_writel(val, c->membase + reg); in txx9spi_wr()
360 c->membase = devm_ioremap_resource(&dev->dev, res); in txx9spi_probe()
361 if (IS_ERR(c->membase)) in txx9spi_probe()
/linux-4.4.14/arch/arm/plat-orion/include/plat/
Dcommon.h18 void __init orion_uart0_init(void __iomem *membase,
23 void __init orion_uart1_init(void __iomem *membase,
28 void __init orion_uart2_init(void __iomem *membase,
33 void __init orion_uart3_init(void __iomem *membase,
/linux-4.4.14/arch/arm/mach-omap1/
Dserial.c38 return (unsigned int)__raw_readb(up->membase + offset); in omap_serial_in()
45 __raw_writeb(value, p->membase + offset); in omap_serial_outp()
129 serial_platform_data[i].membase = NULL; in omap_serial_init()
135 serial_platform_data[i].membase = in omap_serial_init()
137 if (!serial_platform_data[i].membase) { in omap_serial_init()
Dboard-ams-delta.c528 .membase = IOMEM(MODEM_VIRT),
/linux-4.4.14/drivers/staging/dgnc/
Ddgnc_driver.c438 brd->membase = pci_resource_start(pdev, 4); in dgnc_found_board()
440 if (!brd->membase) { in dgnc_found_board()
448 if (brd->membase & 1) in dgnc_found_board()
449 brd->membase &= ~3; in dgnc_found_board()
451 brd->membase &= ~15; in dgnc_found_board()
501 brd->membase = pci_resource_start(pdev, 0); in dgnc_found_board()
504 if (brd->membase & 1) in dgnc_found_board()
505 brd->membase &= ~3; in dgnc_found_board()
507 brd->membase &= ~15; in dgnc_found_board()
613 brd->re_map_membase = ioremap(brd->membase, 0x1000); in dgnc_do_remap()
Ddgnc_mgmt.c146 di.info_physaddr = (ulong)dgnc_Board[brd]->membase; in dgnc_mgmt_ioctl()
147 di.info_physsize = (ulong)dgnc_Board[brd]->membase in dgnc_mgmt_ioctl()
Ddgnc_driver.h194 ulong membase; /* Start of base memory of the card */ member
/linux-4.4.14/drivers/net/can/
Dbfin_can.c144 void __iomem *membase; member
174 struct bfin_can_regs __iomem *reg = priv->membase; in bfin_can_set_bittiming()
200 struct bfin_can_regs __iomem *reg = priv->membase; in bfin_can_set_reset_mode()
259 struct bfin_can_regs __iomem *reg = priv->membase; in bfin_can_set_normal_mode()
331 struct bfin_can_regs __iomem *reg = priv->membase; in bfin_can_get_berr_counter()
344 struct bfin_can_regs __iomem *reg = priv->membase; in bfin_can_start_xmit()
389 struct bfin_can_regs __iomem *reg = priv->membase; in bfin_can_rx()
435 struct bfin_can_regs __iomem *reg = priv->membase; in bfin_can_err()
519 struct bfin_can_regs __iomem *reg = priv->membase; in bfin_can_interrupt()
672 priv->membase = devm_ioremap_resource(&pdev->dev, res_mem); in bfin_can_probe()
[all …]
/linux-4.4.14/arch/arm/plat-orion/
Dcommon.c86 void __iomem *membase, in uart_complete() argument
92 data->membase = membase; in uart_complete()
120 void __init orion_uart0_init(void __iomem *membase, in orion_uart0_init() argument
126 membase, mapbase, irq, clk); in orion_uart0_init()
148 void __init orion_uart1_init(void __iomem *membase, in orion_uart1_init() argument
154 membase, mapbase, irq, clk); in orion_uart1_init()
176 void __init orion_uart2_init(void __iomem *membase, in orion_uart2_init() argument
182 membase, mapbase, irq, clk); in orion_uart2_init()
204 void __init orion_uart3_init(void __iomem *membase, in orion_uart3_init() argument
210 membase, mapbase, irq, clk); in orion_uart3_init()
/linux-4.4.14/drivers/staging/comedi/drivers/
Dii_pci20kc.c418 unsigned int membase; in ii20k_attach() local
423 membase = it->options[0]; in ii20k_attach()
424 if (!membase || (membase & ~(0x100000 - II20K_SIZE))) { in ii20k_attach()
431 if (!request_mem_region(membase, II20K_SIZE, dev->board_name)) { in ii20k_attach()
433 dev->board_name, membase, II20K_SIZE); in ii20k_attach()
436 dev->iobase = membase; /* actually, a memory address */ in ii20k_attach()
438 dev->mmio = ioremap(membase, II20K_SIZE); in ii20k_attach()
/linux-4.4.14/arch/mips/netlogic/xlr/
Dplatform.c32 uartbase = (uint64_t)(long)p->membase; in nlm_xlr_uart_in()
49 uartbase = (uint64_t)(long)p->membase; in nlm_xlr_uart_out()
92 xlr_uart_data[0].membase = (void __iomem *)uartbase; in nlm_uart_init()
96 xlr_uart_data[1].membase = (void __iomem *)uartbase; in nlm_uart_init()
/linux-4.4.14/drivers/net/irda/
Dsh_irda.c143 void __iomem *membase; member
173 iowrite16(data, self->membase + offset); in sh_irda_write()
183 ret = ioread16(self->membase + offset); in sh_irda_read()
196 old = ioread16(self->membase + offset); in sh_irda_update_bits()
199 iowrite16(data, self->membase + offset); in sh_irda_update_bits()
610 self->tx_buff.head = self->membase + IRDARAM; in sh_irda_init_iobuf()
776 self->membase = ioremap_nocache(res->start, resource_size(res)); in sh_irda_probe()
777 if (!self->membase) { in sh_irda_probe()
821 iounmap(self->membase); in sh_irda_probe()
839 iounmap(self->membase); in sh_irda_remove()
Dbfin_sir.h40 unsigned char __iomem *membase; member
85 #define port_membase(port) (((struct bfin_sir_port *)(port))->membase)
Dsh_sir.c107 void __iomem *membase; member
129 iowrite16(data, self->membase + offset); in sh_sir_write()
134 return ioread16(self->membase + offset); in sh_sir_read()
725 self->membase = ioremap_nocache(res->start, resource_size(res)); in sh_sir_probe()
726 if (!self->membase) { in sh_sir_probe()
775 iounmap(self->membase); in sh_sir_probe()
793 iounmap(self->membase); in sh_sir_remove()
/linux-4.4.14/arch/arm/kernel/
Disa.c64 register_isa_ports(unsigned int membase, unsigned int portbase, unsigned int portshift) in register_isa_ports() argument
66 isa_membase = membase; in register_isa_ports()
/linux-4.4.14/arch/mips/loongson64/common/
Dserial.c36 .membase = (void __iomem *)NULL, \
69 uart8250_data[mips_machtype][0].membase = in serial_init()
90 uart8250_data[mips_machtype][i].membase = in serial_init()
/linux-4.4.14/arch/mips/emma/markeins/
Dplatform.c109 .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
117 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
125 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
/linux-4.4.14/arch/arm/mach-iop33x/
Duart.c34 .membase = (char *)IOP33X_UART0_VIRT,
84 .membase = (char *)IOP33X_UART1_VIRT,
/linux-4.4.14/drivers/net/ethernet/8390/
Dmac8390.c238 static enum mac8390_access __init mac8390_testio(volatile unsigned long membase) in mac8390_testio() argument
243 memcpy_toio(membase, &outdata, 4); in mac8390_testio()
245 if (memcmp_withio(&outdata, membase, 4) == 0) in mac8390_testio()
248 word_memcpy_tocard(membase, &outdata, 4); in mac8390_testio()
250 word_memcpy_fromcard(&indata, membase, 4); in mac8390_testio()
256 static int __init mac8390_memsize(unsigned long membase) in mac8390_memsize() argument
264 volatile unsigned short *m = (unsigned short *)(membase + (i * 0x1000)); in mac8390_memsize()
279 volatile unsigned short *p = (unsigned short *)(membase + (j * 0x1000)); in mac8390_memsize()
/linux-4.4.14/arch/arm/mach-ixp4xx/
Dcoyote-setup.c64 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
100 coyote_uart_data[0].membase = in coyote_init()
Davila-setup.c81 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
90 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Ddsmg600-setup.c130 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
139 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Dvulcan-setup.c80 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
89 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Dnslu2-setup.c144 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
153 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Domixp-setup.c128 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
136 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
Dnas100d-setup.c132 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
141 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Dfsg-setup.c92 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
101 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Dixdp425-setup.c154 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
163 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Dgateway7001-setup.c58 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Dwg302v2-setup.c59 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Dgtwx5715-setup.c110 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
Dgoramo_mlr.c250 .membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT +
260 .membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT +
/linux-4.4.14/arch/mips/bcm47xx/
Dserial.c40 p->membase = (void *)ssb_port->regs; in uart8250_init_ssb()
66 p->membase = (void *)bcma_port->regs; in uart8250_init_bcma()
/linux-4.4.14/arch/powerpc/boot/
Dwrapper355 membase=`${CROSS}objdump -p "$kernel" | grep -m 1 LOAD | awk '{print $7}'`
360 ${MKIMAGE} -A ppc -O linux -T kernel -C gzip -a $membase -e $membase \
377 ${MKIMAGE} -A ppc -O linux -T multi -C gzip -a $membase -e $membase \
/linux-4.4.14/drivers/firmware/efi/libstub/
Defi-stub-helper.c117 unsigned long membase = EFI_ERROR; in get_dram_base() local
124 return membase; in get_dram_base()
130 if (membase > md->phys_addr) in get_dram_base()
131 membase = md->phys_addr; in get_dram_base()
135 return membase; in get_dram_base()
/linux-4.4.14/arch/mips/pnx833x/common/
Dplatform.c70 .membase = (void __iomem *)PNX833X_UART0_PORTS_START,
83 .membase = (void __iomem *)PNX833X_UART1_PORTS_START,
/linux-4.4.14/include/uapi/linux/
Dkernelcapi.h27 unsigned int membase; member
/linux-4.4.14/arch/mips/rb532/
Dserial.c44 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
Ddevices.c228 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
/linux-4.4.14/arch/arm/mach-w90x900/
Dcpu.h29 .membase = name##_BA, \
/linux-4.4.14/drivers/misc/ibmasm/
Duart.c55 uart.port.membase = iomem_base; in ibmasm_register_uart()
/linux-4.4.14/arch/powerpc/kernel/
Dlegacy_serial.c59 tmp = readl(p->membase + (UART_IIR & ~3)); in tsi_serial_in()
62 return readb(p->membase + offset); in tsi_serial_in()
69 writeb(value, p->membase + offset); in tsi_serial_out()
513 port->membase = ioremap(port->mapbase, 0x100); in fixup_port_mmio()
/linux-4.4.14/arch/m68k/include/asm/
Dmcfuart.h20 void __iomem *membase; /* Virtual address if mapped */ member
/linux-4.4.14/arch/xtensa/platforms/xt2000/
Dsetup.c121 .membase = (void*)(_base), \
/linux-4.4.14/arch/blackfin/mach-bf533/boards/
DH8606.c325 .membase = (void *)0x20200000,
334 .membase = (void *)0x20200010,
/linux-4.4.14/drivers/video/
Dvgastate.c407 if (!state->membase) in save_vga()
408 state->membase = 0xA0000; in save_vga()
410 fbbase = ioremap(state->membase, state->memsize); in save_vga()
467 void __iomem *fbbase = ioremap(state->membase, state->memsize); in restore_vga()
/linux-4.4.14/arch/arm/mach-gemini/
Ddevices.c23 .membase = (void *)IO_ADDRESS(GEMINI_UART_BASE),
/linux-4.4.14/include/linux/isdn/
Dcapilli.h36 unsigned int membase; member
/linux-4.4.14/arch/mips/vr41xx/common/
Dsiu.c152 port.membase = (unsigned char __iomem *)KSEG1ADDR(res[i].start); in vr41xx_siu_setup()
/linux-4.4.14/arch/arm/mach-pxa/
Dviper.c527 .membase = (void *)&FFUART,
536 .membase = (void *)&BTUART,
545 .membase = (void *)&STUART,
Dzeus.c276 .membase = (void *)&FFUART,
285 .membase = (void *)&BTUART,
294 .membase = (void *)&STUART,
/linux-4.4.14/include/linux/
Dserial_8250.h23 void __iomem *membase; /* ioremap cookie or NULL */ member
Dserial_core.h120 unsigned char __iomem *membase; /* read/write[bwl] */ member
/linux-4.4.14/arch/mips/jazz/
Dsetup.c100 .membase = (void *)(_base), \
/linux-4.4.14/arch/arm/mach-iop32x/
Diq80321.c146 .membase = (char *)IQ80321_UART,
Dglantank.c140 .membase = (char *)GLANTANK_UART,
Dem7210.c154 .membase = (char *)IQ31244_UART,
Diq31244.c220 .membase = (char *)IQ31244_UART,
Dn2100.c174 .membase = (char *)N2100_UART,
/linux-4.4.14/drivers/isdn/hysdn/
Dboardergo.c421 card->memend = card->membase + ERG_DPRAM_PAGE_SIZE - 1; in ergo_inithardware()
422 if (!(card->dpram = ioremap(card->membase, ERG_DPRAM_PAGE_SIZE))) { in ergo_inithardware()
Dhysdn_defs.h151 unsigned long membase; /* DPRAM memory base */ member
Dhysdn_init.c81 card->membase = pci_resource_start(akt_pcidev, PCI_REG_MEMORY_BASE); in hysdn_pci_init_one()
Dhysdn_procconf.c281 card->membase, in hysdn_conf_open()
/linux-4.4.14/drivers/net/ethernet/
Dethoc.c201 void __iomem *membase; member
318 vma = dev->membase; in ethoc_init_ring()
1094 priv->membase = devm_ioremap_nocache(&pdev->dev, in ethoc_probe()
1096 if (!priv->membase) { in ethoc_probe()
1103 priv->membase = dmam_alloc_coherent(&pdev->dev, in ethoc_probe()
1106 if (!priv->membase) { in ethoc_probe()
/linux-4.4.14/arch/arm/mach-ks8695/
Dboard-og.c103 .membase = (char *) S8250_VIRT,
/linux-4.4.14/arch/arm/mach-imx/
Dmach-mx31ads.c84 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
91 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
Dmach-kzm_arm11_01.c72 .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
/linux-4.4.14/arch/mips/alchemy/common/
Dplatform.c37 alchemy_uart_enable(CPHYSADDR(port->membase)); in alchemy_8250_pm()
42 alchemy_uart_disable(CPHYSADDR(port->membase)); in alchemy_8250_pm()
/linux-4.4.14/arch/arm/mach-iop13xx/
Dsetup.c76 .membase = IOP13XX_UART0_VIRT,
89 .membase = IOP13XX_UART1_VIRT,
/linux-4.4.14/arch/arm/mach-cns3xxx/
Dcns3420vb.c96 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT, in cns3420_early_serial_setup()
/linux-4.4.14/drivers/pci/host/
Dpci-mvebu.c105 u16 membase; member
428 if (port->bridge.memlimit < port->bridge.membase || in mvebu_pcie_handle_membase_change()
448 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); in mvebu_pcie_handle_membase_change()
532 *value = (bridge->memlimit << 16 | bridge->membase); in mvebu_sw_pci_bridge_read()
682 bridge->membase = value & 0xffff; in mvebu_sw_pci_bridge_write()
Dpcie-designware.c711 u32 membase; in dw_pcie_setup_rc() local
772 membase = ((u32)pp->mem_base & 0xfff00000) >> 16; in dw_pcie_setup_rc()
774 val = memlimit | membase; in dw_pcie_setup_rc()
/linux-4.4.14/drivers/staging/wlan-ng/
Dp80211netdev.h176 unsigned int membase; member
/linux-4.4.14/arch/mips/ar7/
Dplatform.c584 uart_port.membase = ioremap(uart_port.mapbase, 256); in ar7_register_uarts()
595 uart_port.membase = ioremap(uart_port.mapbase, 256); in ar7_register_uarts()
/linux-4.4.14/drivers/scsi/pm8001/
Dpm8001_init.c419 pm8001_ha->io_mem[logicalBar].membase = in pm8001_ioremap()
421 pm8001_ha->io_mem[logicalBar].membase &= in pm8001_ioremap()
426 ioremap(pm8001_ha->io_mem[logicalBar].membase, in pm8001_ioremap()
433 (u64)pm8001_ha->io_mem[logicalBar].membase, in pm8001_ioremap()
438 pm8001_ha->io_mem[logicalBar].membase = 0; in pm8001_ioremap()
/linux-4.4.14/drivers/isdn/icn/
Dicn.c19 static unsigned long membase = ICN_MEMADDR; variable
28 module_param(membase, ulong, 0);
29 MODULE_PARM_DESC(membase, "Shared memory address of all cards");
1610 membase = (unsigned long)ints[2]; in icn_setup()
1631 dev.memaddr = (membase & 0x0ffc000); in icn_init()
/linux-4.4.14/drivers/staging/dgap/
Ddgap.c1351 if (!request_mem_region(brd->membase, 0x200000, "dgap")) in dgap_remap()
1354 if (!request_mem_region(brd->membase + PCI_IO_OFFSET, 0x200000, "dgap")) in dgap_remap()
1357 brd->re_map_membase = ioremap(brd->membase, 0x200000); in dgap_remap()
1361 brd->re_map_port = ioremap((brd->membase + PCI_IO_OFFSET), 0x200000); in dgap_remap()
1370 release_mem_region(brd->membase + PCI_IO_OFFSET, 0x200000); in dgap_remap()
1372 release_mem_region(brd->membase, 0x200000); in dgap_remap()
1381 release_mem_region(brd->membase + PCI_IO_OFFSET, 0x200000); in dgap_unmap()
1382 release_mem_region(brd->membase, 0x200000); in dgap_unmap()
2112 brd->membase = pci_resource_start(pdev, 2); in dgap_found_board()
2117 brd->membase = pci_resource_start(pdev, 0); in dgap_found_board()
[all …]
/linux-4.4.14/include/video/
Dvga.h184 unsigned long membase; /* VGA window base, 0 for default - 0xA000 */ member
/linux-4.4.14/arch/frv/kernel/
Dsetup.c192 .membase = (char *) UART0_BASE,
201 .membase = (char *) UART1_BASE,
/linux-4.4.14/arch/mn10300/kernel/
Dmn10300-serial.c158 .uart.membase = (void __iomem *) &SC0CTR,
220 .uart.membase = (void __iomem *) &SC1CTR,
282 .uart.membase = (void __iomem *) &SC2CTR,
/linux-4.4.14/drivers/isdn/capi/
Dkcapi.c1235 cparams.membase = cdef.membase; in capi20_manufacturer()
/linux-4.4.14/Documentation/isdn/
DREADME.icn103 portbase=p membase=m icn_id=idstring [icn_id2=idstring2]

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