315 			val = readl(pctl->membase + sunxi_dlevel_reg(pin));  in sunxi_pconf_group_set()
319 				pctl->membase + sunxi_dlevel_reg(pin));  in sunxi_pconf_group_set()
322 			val = readl(pctl->membase + sunxi_pull_reg(pin));  in sunxi_pconf_group_set()
325 				pctl->membase + sunxi_pull_reg(pin));  in sunxi_pconf_group_set()
328 			val = readl(pctl->membase + sunxi_pull_reg(pin));  in sunxi_pconf_group_set()
331 				pctl->membase + sunxi_pull_reg(pin));  in sunxi_pconf_group_set()
389 	val = readl(pctl->membase + sunxi_mux_reg(pin));  in sunxi_pmx_set()
392 		pctl->membase + sunxi_mux_reg(pin));  in sunxi_pmx_set()
467 	val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;  in sunxi_pinctrl_gpio_get()
486 	regval = readl(pctl->membase + reg);  in sunxi_pinctrl_gpio_set()
493 	writel(regval, pctl->membase + reg);  in sunxi_pinctrl_gpio_set()
616 	regval = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_set_type()
618 	writel(regval | (mode << index), pctl->membase + reg);  in sunxi_pinctrl_irq_set_type()
633 	writel(1 << status_idx, pctl->membase + status_reg);  in sunxi_pinctrl_irq_ack()
647 	val = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_mask()
648 	writel(val & ~(1 << idx), pctl->membase + reg);  in sunxi_pinctrl_irq_mask()
664 	val = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_unmask()
665 	writel(val | (1 << idx), pctl->membase + reg);  in sunxi_pinctrl_irq_unmask()
749 	val = readl(pctl->membase + reg);  in sunxi_pinctrl_irq_handler()
892 	pctl->membase = devm_ioremap_resource(&pdev->dev, res);  in sunxi_pinctrl_init()
893 	if (IS_ERR(pctl->membase))  in sunxi_pinctrl_init()
894 		return PTR_ERR(pctl->membase);  in sunxi_pinctrl_init()
1027 		writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i,  in sunxi_pinctrl_init()
1030 		       pctl->membase + sunxi_irq_status_reg_from_bank(i,  in sunxi_pinctrl_init()