Lines Matching refs:membase
199 status = readw(uap->port.membase + UART01x_FR); in pl011_fifo_to_tty()
204 ch = readw(uap->port.membase + UART01x_DR) | in pl011_fifo_to_tty()
441 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_callback()
555 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_refill()
591 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_irq()
593 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_tx_irq()
603 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_tx_irq()
617 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_stop()
643 writew(uap->im, uap->port.membase + in pl011_dma_tx_start()
650 uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
661 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
663 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { in pl011_dma_tx_start()
672 writew(uap->port.x_char, uap->port.membase + UART01x_DR); in pl011_dma_tx_start()
678 writew(dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_tx_start()
706 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_flush_buffer()
746 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_trigger_dma()
750 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_trigger_dma()
809 uap->port.membase + UART011_ICR); in pl011_dma_rx_chars()
857 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_irq()
877 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_irq()
925 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_callback()
938 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_rx_stop()
982 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_dma_rx_poll()
1044 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_startup()
1053 uap->port.membase + ST_UART011_DMAWM); in pl011_dma_startup()
1078 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_dma_shutdown()
1083 writew(uap->dmacr, uap->port.membase + UART011_DMACR); in pl011_dma_shutdown()
1184 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_stop_tx()
1194 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_start_tx_pio()
1214 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_stop_rx()
1225 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_enable_ms()
1245 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_rx_chars()
1266 readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_tx_char()
1269 writew(c, uap->port.membase + UART01x_DR); in pl011_tx_char()
1316 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; in pl011_modem_status()
1344 writew(0x00, uap->port.membase + UART011_ICR); in check_apply_cts_event_workaround()
1351 dummy_read = readw(uap->port.membase + UART011_ICR); in check_apply_cts_event_workaround()
1352 dummy_read = readw(uap->port.membase + UART011_ICR); in check_apply_cts_event_workaround()
1364 imsc = readw(uap->port.membase + UART011_IMSC); in pl011_int()
1365 status = readw(uap->port.membase + UART011_RIS) & imsc; in pl011_int()
1372 uap->port.membase + UART011_ICR); in pl011_int()
1389 status = readw(uap->port.membase + UART011_RIS) & imsc; in pl011_int()
1403 unsigned int status = readw(uap->port.membase + UART01x_FR); in pl011_tx_empty()
1412 unsigned int status = readw(uap->port.membase + UART01x_FR); in pl011_get_mctrl()
1432 cr = readw(uap->port.membase + UART011_CR); in pl011_set_mctrl()
1452 writew(cr, uap->port.membase + UART011_CR); in pl011_set_mctrl()
1463 lcr_h = readw(uap->port.membase + uap->lcrh_tx); in pl011_break_ctl()
1468 writew(lcr_h, uap->port.membase + uap->lcrh_tx); in pl011_break_ctl()
1478 unsigned char __iomem *regs = uap->port.membase; in pl011_quiesce_irqs()
1509 status = readw(uap->port.membase + UART01x_FR); in pl011_get_poll_char()
1513 return readw(uap->port.membase + UART01x_DR); in pl011_get_poll_char()
1522 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_put_poll_char()
1525 writew(ch, uap->port.membase + UART01x_DR); in pl011_put_poll_char()
1550 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); in pl011_hwinit()
1556 uap->im = readw(uap->port.membase + UART011_IMSC); in pl011_hwinit()
1557 writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC); in pl011_hwinit()
1571 writew(lcr_h, uap->port.membase + uap->lcrh_rx); in pl011_write_lcr_h()
1579 writew(0xff, uap->port.membase + UART011_MIS); in pl011_write_lcr_h()
1580 writew(lcr_h, uap->port.membase + uap->lcrh_tx); in pl011_write_lcr_h()
1586 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_allocate_irq()
1602 uap->port.membase + UART011_ICR); in pl011_enable_interrupts()
1606 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_enable_interrupts()
1625 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); in pl011_startup()
1632 writew(cr, uap->port.membase + UART011_CR); in pl011_startup()
1639 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; in pl011_startup()
1680 val = readw(uap->port.membase + lcrh); in pl011_shutdown_channel()
1682 writew(val, uap->port.membase + lcrh); in pl011_shutdown_channel()
1696 cr = readw(uap->port.membase + UART011_CR); in pl011_disable_uart()
1700 writew(cr, uap->port.membase + UART011_CR); in pl011_disable_uart()
1717 writew(uap->im, uap->port.membase + UART011_IMSC); in pl011_disable_interrupts()
1718 writew(0xffff, uap->port.membase + UART011_ICR); in pl011_disable_interrupts()
1870 old_cr = readw(port->membase + UART011_CR); in pl011_set_termios()
1871 writew(0, port->membase + UART011_CR); in pl011_set_termios()
1904 writew(quot & 0x3f, port->membase + UART011_FBRD); in pl011_set_termios()
1905 writew(quot >> 6, port->membase + UART011_IBRD); in pl011_set_termios()
1914 writew(old_cr, port->membase + UART011_CR); in pl011_set_termios()
2055 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_console_putchar()
2057 writew(ch, uap->port.membase + UART01x_DR); in pl011_console_putchar()
2082 old_cr = readw(uap->port.membase + UART011_CR); in pl011_console_write()
2085 writew(new_cr, uap->port.membase + UART011_CR); in pl011_console_write()
2095 status = readw(uap->port.membase + UART01x_FR); in pl011_console_write()
2098 writew(old_cr, uap->port.membase + UART011_CR); in pl011_console_write()
2111 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { in pl011_console_get_options()
2114 lcr_h = readw(uap->port.membase + uap->lcrh_tx); in pl011_console_get_options()
2129 ibrd = readw(uap->port.membase + UART011_IBRD); in pl011_console_get_options()
2130 fbrd = readw(uap->port.membase + UART011_FBRD); in pl011_console_get_options()
2135 if (readw(uap->port.membase + UART011_CR) in pl011_console_get_options()
2207 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) in pl011_putc()
2209 writeb(c, port->membase + UART01x_DR); in pl011_putc()
2210 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) in pl011_putc()
2224 if (!device->port.membase) in pl011_early_console_setup()
2321 uap->port.membase = base; in pl011_setup_port()
2337 writew(0, uap->port.membase + UART011_IMSC); in pl011_register_port()
2338 writew(0xffff, uap->port.membase + UART011_ICR); in pl011_register_port()