1/*
2 * iop13xx platform Initialization
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19
20#include <linux/dma-mapping.h>
21#include <linux/serial_8250.h>
22#include <linux/io.h>
23#include <linux/reboot.h>
24#ifdef CONFIG_MTD_PHYSMAP
25#include <linux/mtd/physmap.h>
26#endif
27#include <asm/mach/map.h>
28#include <mach/hardware.h>
29#include <asm/irq.h>
30#include <asm/hardware/iop_adma.h>
31#include <mach/irqs.h>
32
33#define IOP13XX_UART_XTAL 33334000
34#define IOP13XX_SETUP_DEBUG 0
35#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
36
37/* Standard IO mapping for all IOP13XX based systems
38 */
39static struct map_desc iop13xx_std_desc[] __initdata = {
40	{    /* mem mapped registers */
41		.virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
42		.pfn 	 = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
43		.length  = IOP13XX_PMMR_SIZE,
44		.type	 = MT_DEVICE,
45	},
46};
47
48static struct resource iop13xx_uart0_resources[] = {
49	[0] = {
50		.start = IOP13XX_UART0_PHYS,
51		.end = IOP13XX_UART0_PHYS + 0x3f,
52		.flags = IORESOURCE_MEM,
53	},
54	[1] = {
55		.start = IRQ_IOP13XX_UART0,
56		.end = IRQ_IOP13XX_UART0,
57		.flags = IORESOURCE_IRQ
58	}
59};
60
61static struct resource iop13xx_uart1_resources[] = {
62	[0] = {
63		.start = IOP13XX_UART1_PHYS,
64		.end = IOP13XX_UART1_PHYS + 0x3f,
65		.flags = IORESOURCE_MEM,
66	},
67	[1] = {
68		.start = IRQ_IOP13XX_UART1,
69		.end = IRQ_IOP13XX_UART1,
70		.flags = IORESOURCE_IRQ
71	}
72};
73
74static struct plat_serial8250_port iop13xx_uart0_data[] = {
75	{
76       .membase     = IOP13XX_UART0_VIRT,
77       .mapbase     = IOP13XX_UART0_PHYS,
78       .irq         = IRQ_IOP13XX_UART0,
79       .uartclk     = IOP13XX_UART_XTAL,
80       .regshift    = 2,
81       .iotype      = UPIO_MEM,
82       .flags       = UPF_SKIP_TEST,
83	},
84	{  },
85};
86
87static struct plat_serial8250_port iop13xx_uart1_data[] = {
88	{
89       .membase     = IOP13XX_UART1_VIRT,
90       .mapbase     = IOP13XX_UART1_PHYS,
91       .irq         = IRQ_IOP13XX_UART1,
92       .uartclk     = IOP13XX_UART_XTAL,
93       .regshift    = 2,
94       .iotype      = UPIO_MEM,
95       .flags       = UPF_SKIP_TEST,
96	},
97	{  },
98};
99
100/* The ids are fixed up later in iop13xx_platform_init */
101static struct platform_device iop13xx_uart0 = {
102       .name = "serial8250",
103       .id = 0,
104       .dev.platform_data = iop13xx_uart0_data,
105       .num_resources = 2,
106       .resource = iop13xx_uart0_resources,
107};
108
109static struct platform_device iop13xx_uart1 = {
110       .name = "serial8250",
111       .id = 0,
112       .dev.platform_data = iop13xx_uart1_data,
113       .num_resources = 2,
114       .resource = iop13xx_uart1_resources
115};
116
117static struct resource iop13xx_i2c_0_resources[] = {
118	[0] = {
119		.start = IOP13XX_I2C0_PHYS,
120		.end = IOP13XX_I2C0_PHYS + 0x18,
121		.flags = IORESOURCE_MEM,
122	},
123	[1] = {
124		.start = IRQ_IOP13XX_I2C_0,
125		.end = IRQ_IOP13XX_I2C_0,
126		.flags = IORESOURCE_IRQ
127	}
128};
129
130static struct resource iop13xx_i2c_1_resources[] = {
131	[0] = {
132		.start = IOP13XX_I2C1_PHYS,
133		.end = IOP13XX_I2C1_PHYS + 0x18,
134		.flags = IORESOURCE_MEM,
135	},
136	[1] = {
137		.start = IRQ_IOP13XX_I2C_1,
138		.end = IRQ_IOP13XX_I2C_1,
139		.flags = IORESOURCE_IRQ
140	}
141};
142
143static struct resource iop13xx_i2c_2_resources[] = {
144	[0] = {
145		.start = IOP13XX_I2C2_PHYS,
146		.end = IOP13XX_I2C2_PHYS + 0x18,
147		.flags = IORESOURCE_MEM,
148	},
149	[1] = {
150		.start = IRQ_IOP13XX_I2C_2,
151		.end = IRQ_IOP13XX_I2C_2,
152		.flags = IORESOURCE_IRQ
153	}
154};
155
156/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
157 * we just use the same device name.
158 */
159
160/* The ids are fixed up later in iop13xx_platform_init */
161static struct platform_device iop13xx_i2c_0_controller = {
162	.name = "IOP3xx-I2C",
163	.id = 0,
164	.num_resources = 2,
165	.resource = iop13xx_i2c_0_resources
166};
167
168static struct platform_device iop13xx_i2c_1_controller = {
169	.name = "IOP3xx-I2C",
170	.id = 0,
171	.num_resources = 2,
172	.resource = iop13xx_i2c_1_resources
173};
174
175static struct platform_device iop13xx_i2c_2_controller = {
176	.name = "IOP3xx-I2C",
177	.id = 0,
178	.num_resources = 2,
179	.resource = iop13xx_i2c_2_resources
180};
181
182#ifdef CONFIG_MTD_PHYSMAP
183/* PBI Flash Device
184 */
185static struct physmap_flash_data iq8134x_flash_data = {
186	.width = 2,
187};
188
189static struct resource iq8134x_flash_resource = {
190	.start = IQ81340_FLASHBASE,
191	.end   = 0,
192	.flags = IORESOURCE_MEM,
193};
194
195static struct platform_device iq8134x_flash = {
196	.name           = "physmap-flash",
197	.id             = 0,
198	.dev            = { .platform_data  = &iq8134x_flash_data, },
199	.num_resources  = 1,
200	.resource       = &iq8134x_flash_resource,
201};
202
203static unsigned long iq8134x_probe_flash_size(void)
204{
205	uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
206	int i;
207	char query[3];
208	unsigned long size = 0;
209	int width = iq8134x_flash_data.width;
210
211	if (flash_addr) {
212		/* send CFI 'query' command */
213		writew(0x98, flash_addr);
214
215		/* check for CFI compliance */
216		for (i = 0; i < 3 * width; i += width)
217			query[i / width] = readb(flash_addr + (0x10 * width) + i);
218
219		/* read the size */
220		if (memcmp(query, "QRY", 3) == 0)
221			size = 1 << readb(flash_addr + (0x27 * width));
222
223		/* send CFI 'read array' command */
224		writew(0xff, flash_addr);
225
226		iounmap(flash_addr);
227	}
228
229	return size;
230}
231#endif
232
233/* ADMA Channels */
234static struct resource iop13xx_adma_0_resources[] = {
235	[0] = {
236		.start = IOP13XX_ADMA_PHYS_BASE(0),
237		.end = IOP13XX_ADMA_UPPER_PA(0),
238		.flags = IORESOURCE_MEM,
239	},
240	[1] = {
241		.start = IRQ_IOP13XX_ADMA0_EOT,
242		.end = IRQ_IOP13XX_ADMA0_EOT,
243		.flags = IORESOURCE_IRQ
244	},
245	[2] = {
246		.start = IRQ_IOP13XX_ADMA0_EOC,
247		.end = IRQ_IOP13XX_ADMA0_EOC,
248		.flags = IORESOURCE_IRQ
249	},
250	[3] = {
251		.start = IRQ_IOP13XX_ADMA0_ERR,
252		.end = IRQ_IOP13XX_ADMA0_ERR,
253		.flags = IORESOURCE_IRQ
254	}
255};
256
257static struct resource iop13xx_adma_1_resources[] = {
258	[0] = {
259		.start = IOP13XX_ADMA_PHYS_BASE(1),
260		.end = IOP13XX_ADMA_UPPER_PA(1),
261		.flags = IORESOURCE_MEM,
262	},
263	[1] = {
264		.start = IRQ_IOP13XX_ADMA1_EOT,
265		.end = IRQ_IOP13XX_ADMA1_EOT,
266		.flags = IORESOURCE_IRQ
267	},
268	[2] = {
269		.start = IRQ_IOP13XX_ADMA1_EOC,
270		.end = IRQ_IOP13XX_ADMA1_EOC,
271		.flags = IORESOURCE_IRQ
272	},
273	[3] = {
274		.start = IRQ_IOP13XX_ADMA1_ERR,
275		.end = IRQ_IOP13XX_ADMA1_ERR,
276		.flags = IORESOURCE_IRQ
277	}
278};
279
280static struct resource iop13xx_adma_2_resources[] = {
281	[0] = {
282		.start = IOP13XX_ADMA_PHYS_BASE(2),
283		.end = IOP13XX_ADMA_UPPER_PA(2),
284		.flags = IORESOURCE_MEM,
285	},
286	[1] = {
287		.start = IRQ_IOP13XX_ADMA2_EOT,
288		.end = IRQ_IOP13XX_ADMA2_EOT,
289		.flags = IORESOURCE_IRQ
290	},
291	[2] = {
292		.start = IRQ_IOP13XX_ADMA2_EOC,
293		.end = IRQ_IOP13XX_ADMA2_EOC,
294		.flags = IORESOURCE_IRQ
295	},
296	[3] = {
297		.start = IRQ_IOP13XX_ADMA2_ERR,
298		.end = IRQ_IOP13XX_ADMA2_ERR,
299		.flags = IORESOURCE_IRQ
300	}
301};
302
303static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(64);
304static struct iop_adma_platform_data iop13xx_adma_0_data = {
305	.hw_id = 0,
306	.pool_size = PAGE_SIZE,
307};
308
309static struct iop_adma_platform_data iop13xx_adma_1_data = {
310	.hw_id = 1,
311	.pool_size = PAGE_SIZE,
312};
313
314static struct iop_adma_platform_data iop13xx_adma_2_data = {
315	.hw_id = 2,
316	.pool_size = PAGE_SIZE,
317};
318
319/* The ids are fixed up later in iop13xx_platform_init */
320static struct platform_device iop13xx_adma_0_channel = {
321	.name = "iop-adma",
322	.id = 0,
323	.num_resources = 4,
324	.resource = iop13xx_adma_0_resources,
325	.dev = {
326		.dma_mask = &iop13xx_adma_dmamask,
327		.coherent_dma_mask = DMA_BIT_MASK(64),
328		.platform_data = (void *) &iop13xx_adma_0_data,
329	},
330};
331
332static struct platform_device iop13xx_adma_1_channel = {
333	.name = "iop-adma",
334	.id = 0,
335	.num_resources = 4,
336	.resource = iop13xx_adma_1_resources,
337	.dev = {
338		.dma_mask = &iop13xx_adma_dmamask,
339		.coherent_dma_mask = DMA_BIT_MASK(64),
340		.platform_data = (void *) &iop13xx_adma_1_data,
341	},
342};
343
344static struct platform_device iop13xx_adma_2_channel = {
345	.name = "iop-adma",
346	.id = 0,
347	.num_resources = 4,
348	.resource = iop13xx_adma_2_resources,
349	.dev = {
350		.dma_mask = &iop13xx_adma_dmamask,
351		.coherent_dma_mask = DMA_BIT_MASK(64),
352		.platform_data = (void *) &iop13xx_adma_2_data,
353	},
354};
355
356void __init iop13xx_map_io(void)
357{
358	/* Initialize the Static Page Table maps */
359	iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
360}
361
362static int init_uart;
363static int init_i2c;
364static int init_adma;
365
366void __init iop13xx_platform_init(void)
367{
368	int i;
369	u32 uart_idx, i2c_idx, adma_idx, plat_idx;
370	struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
371
372	/* set the bases so we can read the device id */
373	iop13xx_set_atu_mmr_bases();
374
375	memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
376
377	if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
378		switch (iop13xx_dev_id()) {
379		/* enable both uarts on iop341 */
380		case 0x3380:
381		case 0x3384:
382		case 0x3388:
383		case 0x338c:
384			init_uart |= IOP13XX_INIT_UART_0;
385			init_uart |= IOP13XX_INIT_UART_1;
386			break;
387		/* only enable uart 1 */
388		default:
389			init_uart |= IOP13XX_INIT_UART_1;
390		}
391	}
392
393	if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
394		switch (iop13xx_dev_id()) {
395		/* enable all i2c units on iop341 and iop342 */
396		case 0x3380:
397		case 0x3384:
398		case 0x3388:
399		case 0x338c:
400		case 0x3382:
401		case 0x3386:
402		case 0x338a:
403		case 0x338e:
404			init_i2c |= IOP13XX_INIT_I2C_0;
405			init_i2c |= IOP13XX_INIT_I2C_1;
406			init_i2c |= IOP13XX_INIT_I2C_2;
407			break;
408		/* only enable i2c 1 and 2 */
409		default:
410			init_i2c |= IOP13XX_INIT_I2C_1;
411			init_i2c |= IOP13XX_INIT_I2C_2;
412		}
413	}
414
415	if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) {
416		init_adma |= IOP13XX_INIT_ADMA_0;
417		init_adma |= IOP13XX_INIT_ADMA_1;
418		init_adma |= IOP13XX_INIT_ADMA_2;
419	}
420
421	plat_idx = 0;
422	uart_idx = 0;
423	i2c_idx = 0;
424
425	/* uart 1 (if enabled) is ttyS0 */
426	if (init_uart & IOP13XX_INIT_UART_1) {
427		PRINTK("Adding uart1 to platform device list\n");
428		iop13xx_uart1.id = uart_idx++;
429		iop13xx_devices[plat_idx++] = &iop13xx_uart1;
430	}
431	if (init_uart & IOP13XX_INIT_UART_0) {
432		PRINTK("Adding uart0 to platform device list\n");
433		iop13xx_uart0.id = uart_idx++;
434		iop13xx_devices[plat_idx++] = &iop13xx_uart0;
435	}
436
437	for(i = 0; i < IQ81340_NUM_I2C; i++) {
438		if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
439			printk("Adding i2c%d to platform device list\n", i);
440		switch(init_i2c & (1 << i)) {
441		case IOP13XX_INIT_I2C_0:
442			iop13xx_i2c_0_controller.id = i2c_idx++;
443			iop13xx_devices[plat_idx++] =
444				&iop13xx_i2c_0_controller;
445			break;
446		case IOP13XX_INIT_I2C_1:
447			iop13xx_i2c_1_controller.id = i2c_idx++;
448			iop13xx_devices[plat_idx++] =
449				&iop13xx_i2c_1_controller;
450			break;
451		case IOP13XX_INIT_I2C_2:
452			iop13xx_i2c_2_controller.id = i2c_idx++;
453			iop13xx_devices[plat_idx++] =
454				&iop13xx_i2c_2_controller;
455			break;
456		}
457	}
458
459	/* initialize adma channel ids and capabilities */
460	adma_idx = 0;
461	for (i = 0; i < IQ81340_NUM_ADMA; i++) {
462		struct iop_adma_platform_data *plat_data;
463		if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG)
464			printk(KERN_INFO
465				"Adding adma%d to platform device list\n", i);
466		switch (init_adma & (1 << i)) {
467		case IOP13XX_INIT_ADMA_0:
468			iop13xx_adma_0_channel.id = adma_idx++;
469			iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel;
470			plat_data = &iop13xx_adma_0_data;
471			dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
472			dma_cap_set(DMA_XOR, plat_data->cap_mask);
473			dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
474			dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
475			break;
476		case IOP13XX_INIT_ADMA_1:
477			iop13xx_adma_1_channel.id = adma_idx++;
478			iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel;
479			plat_data = &iop13xx_adma_1_data;
480			dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
481			dma_cap_set(DMA_XOR, plat_data->cap_mask);
482			dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
483			dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
484			break;
485		case IOP13XX_INIT_ADMA_2:
486			iop13xx_adma_2_channel.id = adma_idx++;
487			iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel;
488			plat_data = &iop13xx_adma_2_data;
489			dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
490			dma_cap_set(DMA_XOR, plat_data->cap_mask);
491			dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
492			dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
493			dma_cap_set(DMA_PQ, plat_data->cap_mask);
494			dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask);
495			break;
496		}
497	}
498
499#ifdef CONFIG_MTD_PHYSMAP
500	iq8134x_flash_resource.end = iq8134x_flash_resource.start +
501				iq8134x_probe_flash_size() - 1;
502	if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
503		iop13xx_devices[plat_idx++] = &iq8134x_flash;
504	else
505		printk(KERN_ERR "%s: Failed to probe flash size\n", __func__);
506#endif
507
508	platform_add_devices(iop13xx_devices, plat_idx);
509}
510
511static int __init iop13xx_init_uart_setup(char *str)
512{
513	if (str) {
514		while (*str != '\0') {
515			switch(*str) {
516			case '0':
517				init_uart |= IOP13XX_INIT_UART_0;
518				break;
519			case '1':
520				init_uart |= IOP13XX_INIT_UART_1;
521				break;
522			case ',':
523			case '=':
524				break;
525			default:
526				PRINTK("\"iop13xx_init_uart\" malformed"
527					    " at character: \'%c\'", *str);
528				*(str + 1) = '\0';
529				init_uart = IOP13XX_INIT_UART_DEFAULT;
530			}
531			str++;
532		}
533	}
534	return 1;
535}
536
537static int __init iop13xx_init_i2c_setup(char *str)
538{
539	if (str) {
540		while (*str != '\0') {
541			switch(*str) {
542			case '0':
543				init_i2c |= IOP13XX_INIT_I2C_0;
544				break;
545			case '1':
546				init_i2c |= IOP13XX_INIT_I2C_1;
547				break;
548			case '2':
549				init_i2c |= IOP13XX_INIT_I2C_2;
550				break;
551			case ',':
552			case '=':
553				break;
554			default:
555				PRINTK("\"iop13xx_init_i2c\" malformed"
556					    " at character: \'%c\'", *str);
557				*(str + 1) = '\0';
558				init_i2c = IOP13XX_INIT_I2C_DEFAULT;
559			}
560			str++;
561		}
562	}
563	return 1;
564}
565
566static int __init iop13xx_init_adma_setup(char *str)
567{
568	if (str)	{
569		while (*str != '\0') {
570			switch (*str) {
571			case '0':
572				init_adma |= IOP13XX_INIT_ADMA_0;
573				break;
574			case '1':
575				init_adma |= IOP13XX_INIT_ADMA_1;
576				break;
577			case '2':
578				init_adma |= IOP13XX_INIT_ADMA_2;
579				break;
580			case ',':
581			case '=':
582				break;
583			default:
584				PRINTK("\"iop13xx_init_adma\" malformed"
585					    " at character: \'%c\'", *str);
586				*(str + 1) = '\0';
587				init_adma = IOP13XX_INIT_ADMA_DEFAULT;
588			}
589			str++;
590		}
591	}
592	return 1;
593}
594
595__setup("iop13xx_init_adma", iop13xx_init_adma_setup);
596__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
597__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
598
599void iop13xx_restart(enum reboot_mode mode, const char *cmd)
600{
601	/*
602	 * Reset the internal bus (warning both cores are reset)
603	 */
604	write_wdtcr(IOP_WDTCR_EN_ARM);
605	write_wdtcr(IOP_WDTCR_EN);
606	write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
607	write_wdtcr(0x1000);
608}
609