102 	val = readl(port->membase + AML_UART_STATUS);  in meson_uart_tx_empty()
110 	val = readl(port->membase + AML_UART_CONTROL);  in meson_uart_stop_tx()
112 	writel(val, port->membase + AML_UART_CONTROL);  in meson_uart_stop_tx()
119 	val = readl(port->membase + AML_UART_CONTROL);  in meson_uart_stop_rx()
121 	writel(val, port->membase + AML_UART_CONTROL);  in meson_uart_stop_rx()
133 	val = readl(port->membase + AML_UART_CONTROL);  in meson_uart_shutdown()
136 	writel(val, port->membase + AML_UART_CONTROL);  in meson_uart_shutdown()
151 	while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) {  in meson_uart_start_tx()
153 			writel(port->x_char, port->membase + AML_UART_WFIFO);  in meson_uart_start_tx()
163 		writel(ch, port->membase + AML_UART_WFIFO);  in meson_uart_start_tx()
181 		status = readl(port->membase + AML_UART_STATUS);  in meson_receive_chars()
191 			mode = readl(port->membase + AML_UART_CONTROL);  in meson_receive_chars()
193 			writel(mode, port->membase + AML_UART_CONTROL);  in meson_receive_chars()
197 			writel(mode, port->membase + AML_UART_CONTROL);  in meson_receive_chars()
206 		ch = readl(port->membase + AML_UART_RFIFO);  in meson_receive_chars()
215 	} while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY));  in meson_receive_chars()
228 	if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY))  in meson_uart_interrupt()
231 	if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL))  in meson_uart_interrupt()
249 	val = readl(port->membase + AML_UART_CONTROL);  in meson_uart_startup()
251 	writel(val, port->membase + AML_UART_CONTROL);  in meson_uart_startup()
254 	writel(val, port->membase + AML_UART_CONTROL);  in meson_uart_startup()
257 	writel(val, port->membase + AML_UART_CONTROL);  in meson_uart_startup()
260 	writel(val, port->membase + AML_UART_CONTROL);  in meson_uart_startup()
263 	writel(val, port->membase + AML_UART_MISC);  in meson_uart_startup()
275 	while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_EMPTY))  in meson_uart_change_speed()
278 	val = readl(port->membase + AML_UART_REG5);  in meson_uart_change_speed()
282 	writel(val, port->membase + AML_UART_REG5);  in meson_uart_change_speed()
298 	val = readl(port->membase + AML_UART_CONTROL);  in meson_uart_set_termios()
337 	writel(val, port->membase + AML_UART_CONTROL);  in meson_uart_set_termios()
373 		devm_iounmap(port->dev, port->membase);  in meson_uart_release_port()
374 		port->membase = NULL;  in meson_uart_release_port()
398 		port->membase = devm_ioremap_nocache(port->dev,  in meson_uart_request_port()
401 		if (port->membase == NULL)  in meson_uart_request_port()
437 	if (!port->membase)  in meson_console_putchar()
440 	while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)  in meson_console_putchar()
442 	writel(ch, port->membase + AML_UART_WFIFO);  in meson_console_putchar()
485 	if (!port || !port->membase)  in meson_serial_console_setup()