Lines Matching refs:membase
230 void __iomem *membase; member
339 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); in port_show_regs()
341 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); in port_show_regs()
343 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); in port_show_regs()
345 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); in port_show_regs()
347 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); in port_show_regs()
349 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); in port_show_regs()
352 ioread8(priv->membase + PCH_UART_BRCSR)); in port_show_regs()
354 lcr = ioread8(priv->membase + UART_LCR); in port_show_regs()
355 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in port_show_regs()
357 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); in port_show_regs()
359 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); in port_show_regs()
360 iowrite8(lcr, priv->membase + UART_LCR); in port_show_regs()
441 u8 ier = ioread8(priv->membase + UART_IER); in pch_uart_hal_enable_interrupt()
443 iowrite8(ier, priv->membase + UART_IER); in pch_uart_hal_enable_interrupt()
449 u8 ier = ioread8(priv->membase + UART_IER); in pch_uart_hal_disable_interrupt()
451 iowrite8(ier, priv->membase + UART_IER); in pch_uart_hal_disable_interrupt()
491 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in pch_uart_hal_set_line()
492 iowrite8(dll, priv->membase + PCH_UART_DLL); in pch_uart_hal_set_line()
493 iowrite8(dlm, priv->membase + PCH_UART_DLM); in pch_uart_hal_set_line()
494 iowrite8(lcr, priv->membase + UART_LCR); in pch_uart_hal_set_line()
508 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
510 priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
511 iowrite8(priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
560 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
562 priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
563 iowrite8(fcr, priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
571 unsigned int msr = ioread8(priv->membase + UART_MSR); in pch_uart_hal_get_modem()
584 iowrite8(thr, priv->membase + PCH_UART_THR); in pch_uart_hal_write()
595 lsr = ioread8(priv->membase + UART_LSR); in pch_uart_hal_read()
596 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); in pch_uart_hal_read()
598 lsr = ioread8(priv->membase + UART_LSR)) { in pch_uart_hal_read()
599 rbr = ioread8(priv->membase + PCH_UART_RBR); in pch_uart_hal_read()
620 return ioread8(priv->membase + UART_IIR) &\ in pch_uart_hal_get_iid()
626 return ioread8(priv->membase + UART_LSR); in pch_uart_hal_get_line_status()
633 lcr = ioread8(priv->membase + UART_LCR); in pch_uart_hal_set_break()
639 iowrite8(lcr, priv->membase + UART_LCR); in pch_uart_hal_set_break()
1229 iowrite8(mcr, priv->membase + UART_MCR); in pch_uart_set_mctrl()
1461 pci_iounmap(priv->pdev, priv->membase); in pch_uart_release_port()
1469 void __iomem *membase; in pch_uart_request_port() local
1476 membase = pci_iomap(priv->pdev, 1, 0); in pch_uart_request_port()
1477 if (!membase) { in pch_uart_request_port()
1481 priv->membase = port->membase = membase; in pch_uart_request_port()
1537 status = ioread8(up->membase + UART_LSR); in wait_for_xmitr()
1550 unsigned int msr = ioread8(up->membase + UART_MSR); in wait_for_xmitr()
1569 u8 lsr = ioread8(priv->membase + UART_LSR); in pch_uart_get_poll_char()
1574 return ioread8(priv->membase + PCH_UART_RBR); in pch_uart_get_poll_char()
1588 ier = ioread8(priv->membase + UART_IER); in pch_uart_put_poll_char()
1595 iowrite8(c, priv->membase + PCH_UART_THR); in pch_uart_put_poll_char()
1602 iowrite8(ier, priv->membase + UART_IER); in pch_uart_put_poll_char()
1638 iowrite8(ch, priv->membase + PCH_UART_THR); in pch_console_putchar()
1677 ier = ioread8(priv->membase + UART_IER); in pch_console_write()
1688 iowrite8(ier, priv->membase + UART_IER); in pch_console_write()
1714 if (!port || (!port->iobase && !port->membase)) in pch_console_setup()
1809 priv->port.membase = NULL; in pch_uart_init_port()