1/* 2 * ARC On-Chip(fpga) UART Driver 3 * 4 * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * vineetg: July 10th 2012 11 * -Decoupled the driver from arch/arc 12 * +Using platform_get_resource() for irq/membase (thx to bfin_uart.c) 13 * +Using early_platform_xxx() for early console (thx to mach-shmobile/xxx) 14 * 15 * Vineetg: Aug 21st 2010 16 * -Is uart_tx_stopped() not done in tty write path as it has already been 17 * taken care of, in serial core 18 * 19 * Vineetg: Aug 18th 2010 20 * -New Serial Core based ARC UART driver 21 * -Derived largely from blackfin driver albiet with some major tweaks 22 * 23 * TODO: 24 * -check if sysreq works 25 */ 26 27#if defined(CONFIG_SERIAL_ARC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 28#define SUPPORT_SYSRQ 29#endif 30 31#include <linux/module.h> 32#include <linux/serial.h> 33#include <linux/console.h> 34#include <linux/sysrq.h> 35#include <linux/platform_device.h> 36#include <linux/tty.h> 37#include <linux/tty_flip.h> 38#include <linux/serial_core.h> 39#include <linux/io.h> 40#include <linux/of_irq.h> 41#include <linux/of_address.h> 42 43/************************************* 44 * ARC UART Hardware Specs 45 ************************************/ 46#define ARC_UART_TX_FIFO_SIZE 1 47 48/* 49 * UART Register set (this is not a Standards Compliant IP) 50 * Also each reg is Word aligned, but only 8 bits wide 51 */ 52#define R_ID0 0 53#define R_ID1 4 54#define R_ID2 8 55#define R_ID3 12 56#define R_DATA 16 57#define R_STS 20 58#define R_BAUDL 24 59#define R_BAUDH 28 60 61/* Bits for UART Status Reg (R/W) */ 62#define RXIENB 0x04 /* Receive Interrupt Enable */ 63#define TXIENB 0x40 /* Transmit Interrupt Enable */ 64 65#define RXEMPTY 0x20 /* Receive FIFO Empty: No char receivede */ 66#define TXEMPTY 0x80 /* Transmit FIFO Empty, thus char can be written into */ 67 68#define RXFULL 0x08 /* Receive FIFO full */ 69#define RXFULL1 0x10 /* Receive FIFO has space for 1 char (tot space=4) */ 70 71#define RXFERR 0x01 /* Frame Error: Stop Bit not detected */ 72#define RXOERR 0x02 /* OverFlow Err: Char recv but RXFULL still set */ 73 74/* Uart bit fiddling helpers: lowest level */ 75#define RBASE(port, reg) (port->membase + reg) 76#define UART_REG_SET(u, r, v) writeb((v), RBASE(u, r)) 77#define UART_REG_GET(u, r) readb(RBASE(u, r)) 78 79#define UART_REG_OR(u, r, v) UART_REG_SET(u, r, UART_REG_GET(u, r) | (v)) 80#define UART_REG_CLR(u, r, v) UART_REG_SET(u, r, UART_REG_GET(u, r) & ~(v)) 81 82/* Uart bit fiddling helpers: API level */ 83#define UART_SET_DATA(uart, val) UART_REG_SET(uart, R_DATA, val) 84#define UART_GET_DATA(uart) UART_REG_GET(uart, R_DATA) 85 86#define UART_SET_BAUDH(uart, val) UART_REG_SET(uart, R_BAUDH, val) 87#define UART_SET_BAUDL(uart, val) UART_REG_SET(uart, R_BAUDL, val) 88 89#define UART_CLR_STATUS(uart, val) UART_REG_CLR(uart, R_STS, val) 90#define UART_GET_STATUS(uart) UART_REG_GET(uart, R_STS) 91 92#define UART_ALL_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB|TXIENB) 93#define UART_RX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB) 94#define UART_TX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, TXIENB) 95 96#define UART_ALL_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB|TXIENB) 97#define UART_RX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB) 98#define UART_TX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, TXIENB) 99 100#define ARC_SERIAL_DEV_NAME "ttyARC" 101 102struct arc_uart_port { 103 struct uart_port port; 104 unsigned long baud; 105}; 106 107#define to_arc_port(uport) container_of(uport, struct arc_uart_port, port) 108 109static struct arc_uart_port arc_uart_ports[CONFIG_SERIAL_ARC_NR_PORTS]; 110 111#ifdef CONFIG_SERIAL_ARC_CONSOLE 112static struct console arc_console; 113#endif 114 115#define DRIVER_NAME "arc-uart" 116 117static struct uart_driver arc_uart_driver = { 118 .owner = THIS_MODULE, 119 .driver_name = DRIVER_NAME, 120 .dev_name = ARC_SERIAL_DEV_NAME, 121 .major = 0, 122 .minor = 0, 123 .nr = CONFIG_SERIAL_ARC_NR_PORTS, 124#ifdef CONFIG_SERIAL_ARC_CONSOLE 125 .cons = &arc_console, 126#endif 127}; 128 129static void arc_serial_stop_rx(struct uart_port *port) 130{ 131 UART_RX_IRQ_DISABLE(port); 132} 133 134static void arc_serial_stop_tx(struct uart_port *port) 135{ 136 while (!(UART_GET_STATUS(port) & TXEMPTY)) 137 cpu_relax(); 138 139 UART_TX_IRQ_DISABLE(port); 140} 141 142/* 143 * Return TIOCSER_TEMT when transmitter is not busy. 144 */ 145static unsigned int arc_serial_tx_empty(struct uart_port *port) 146{ 147 unsigned int stat; 148 149 stat = UART_GET_STATUS(port); 150 if (stat & TXEMPTY) 151 return TIOCSER_TEMT; 152 153 return 0; 154} 155 156/* 157 * Driver internal routine, used by both tty(serial core) as well as tx-isr 158 * -Called under spinlock in either cases 159 * -also tty->stopped has already been checked 160 * = by uart_start( ) before calling us 161 * = tx_ist checks that too before calling 162 */ 163static void arc_serial_tx_chars(struct uart_port *port) 164{ 165 struct circ_buf *xmit = &port->state->xmit; 166 int sent = 0; 167 unsigned char ch; 168 169 if (unlikely(port->x_char)) { 170 UART_SET_DATA(port, port->x_char); 171 port->icount.tx++; 172 port->x_char = 0; 173 sent = 1; 174 } else if (!uart_circ_empty(xmit)) { 175 ch = xmit->buf[xmit->tail]; 176 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 177 port->icount.tx++; 178 while (!(UART_GET_STATUS(port) & TXEMPTY)) 179 cpu_relax(); 180 UART_SET_DATA(port, ch); 181 sent = 1; 182 } 183 184 /* 185 * If num chars in xmit buffer are too few, ask tty layer for more. 186 * By Hard ISR to schedule processing in software interrupt part 187 */ 188 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 189 uart_write_wakeup(port); 190 191 if (sent) 192 UART_TX_IRQ_ENABLE(port); 193} 194 195/* 196 * port is locked and interrupts are disabled 197 * uart_start( ) calls us under the port spinlock irqsave 198 */ 199static void arc_serial_start_tx(struct uart_port *port) 200{ 201 arc_serial_tx_chars(port); 202} 203 204static void arc_serial_rx_chars(struct uart_port *port, unsigned int status) 205{ 206 unsigned int ch, flg = 0; 207 208 /* 209 * UART has 4 deep RX-FIFO. Driver's recongnition of this fact 210 * is very subtle. Here's how ... 211 * Upon getting a RX-Intr, such that RX-EMPTY=0, meaning data available, 212 * driver reads the DATA Reg and keeps doing that in a loop, until 213 * RX-EMPTY=1. Multiple chars being avail, with a single Interrupt, 214 * before RX-EMPTY=0, implies some sort of buffering going on in the 215 * controller, which is indeed the Rx-FIFO. 216 */ 217 do { 218 /* 219 * This could be an Rx Intr for err (no data), 220 * so check err and clear that Intr first 221 */ 222 if (unlikely(status & (RXOERR | RXFERR))) { 223 if (status & RXOERR) { 224 port->icount.overrun++; 225 flg = TTY_OVERRUN; 226 UART_CLR_STATUS(port, RXOERR); 227 } 228 229 if (status & RXFERR) { 230 port->icount.frame++; 231 flg = TTY_FRAME; 232 UART_CLR_STATUS(port, RXFERR); 233 } 234 } else 235 flg = TTY_NORMAL; 236 237 if (status & RXEMPTY) 238 continue; 239 240 ch = UART_GET_DATA(port); 241 port->icount.rx++; 242 243 if (!(uart_handle_sysrq_char(port, ch))) 244 uart_insert_char(port, status, RXOERR, ch, flg); 245 246 spin_unlock(&port->lock); 247 tty_flip_buffer_push(&port->state->port); 248 spin_lock(&port->lock); 249 } while (!((status = UART_GET_STATUS(port)) & RXEMPTY)); 250} 251 252/* 253 * A note on the Interrupt handling state machine of this driver 254 * 255 * kernel printk writes funnel thru the console driver framework and in order 256 * to keep things simple as well as efficient, it writes to UART in polled 257 * mode, in one shot, and exits. 258 * 259 * OTOH, Userland output (via tty layer), uses interrupt based writes as there 260 * can be undeterministic delay between char writes. 261 * 262 * Thus Rx-interrupts are always enabled, while tx-interrupts are by default 263 * disabled. 264 * 265 * When tty has some data to send out, serial core calls driver's start_tx 266 * which 267 * -checks-if-tty-buffer-has-char-to-send 268 * -writes-data-to-uart 269 * -enable-tx-intr 270 * 271 * Once data bits are pushed out, controller raises the Tx-room-avail-Interrupt. 272 * The first thing Tx ISR does is disable further Tx interrupts (as this could 273 * be the last char to send, before settling down into the quiet polled mode). 274 * It then calls the exact routine used by tty layer write to send out any 275 * more char in tty buffer. In case of sending, it re-enables Tx-intr. In case 276 * of no data, it remains disabled. 277 * This is how the transmit state machine is dynamically switched on/off 278 */ 279 280static irqreturn_t arc_serial_isr(int irq, void *dev_id) 281{ 282 struct uart_port *port = dev_id; 283 unsigned int status; 284 285 status = UART_GET_STATUS(port); 286 287 /* 288 * Single IRQ for both Rx (data available) Tx (room available) Interrupt 289 * notifications from the UART Controller. 290 * To demultiplex between the two, we check the relevant bits 291 */ 292 if (status & RXIENB) { 293 294 /* already in ISR, no need of xx_irqsave */ 295 spin_lock(&port->lock); 296 arc_serial_rx_chars(port, status); 297 spin_unlock(&port->lock); 298 } 299 300 if ((status & TXIENB) && (status & TXEMPTY)) { 301 302 /* Unconditionally disable further Tx-Interrupts. 303 * will be enabled by tx_chars() if needed. 304 */ 305 UART_TX_IRQ_DISABLE(port); 306 307 spin_lock(&port->lock); 308 309 if (!uart_tx_stopped(port)) 310 arc_serial_tx_chars(port); 311 312 spin_unlock(&port->lock); 313 } 314 315 return IRQ_HANDLED; 316} 317 318static unsigned int arc_serial_get_mctrl(struct uart_port *port) 319{ 320 /* 321 * Pretend we have a Modem status reg and following bits are 322 * always set, to satify the serial core state machine 323 * (DSR) Data Set Ready 324 * (CTS) Clear To Send 325 * (CAR) Carrier Detect 326 */ 327 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 328} 329 330static void arc_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) 331{ 332 /* MCR not present */ 333} 334 335static void arc_serial_break_ctl(struct uart_port *port, int break_state) 336{ 337 /* ARC UART doesn't support sending Break signal */ 338} 339 340static int arc_serial_startup(struct uart_port *port) 341{ 342 /* Before we hook up the ISR, Disable all UART Interrupts */ 343 UART_ALL_IRQ_DISABLE(port); 344 345 if (request_irq(port->irq, arc_serial_isr, 0, "arc uart rx-tx", port)) { 346 dev_warn(port->dev, "Unable to attach ARC UART intr\n"); 347 return -EBUSY; 348 } 349 350 UART_RX_IRQ_ENABLE(port); /* Only Rx IRQ enabled to begin with */ 351 352 return 0; 353} 354 355/* This is not really needed */ 356static void arc_serial_shutdown(struct uart_port *port) 357{ 358 free_irq(port->irq, port); 359} 360 361static void 362arc_serial_set_termios(struct uart_port *port, struct ktermios *new, 363 struct ktermios *old) 364{ 365 struct arc_uart_port *uart = to_arc_port(port); 366 unsigned int baud, uartl, uarth, hw_val; 367 unsigned long flags; 368 369 /* 370 * Use the generic handler so that any specially encoded baud rates 371 * such as SPD_xx flags or "%B0" can be handled 372 * Max Baud I suppose will not be more than current 115K * 4 373 * Formula for ARC UART is: hw-val = ((CLK/(BAUD*4)) -1) 374 * spread over two 8-bit registers 375 */ 376 baud = uart_get_baud_rate(port, new, old, 0, 460800); 377 378 hw_val = port->uartclk / (uart->baud * 4) - 1; 379 uartl = hw_val & 0xFF; 380 uarth = (hw_val >> 8) & 0xFF; 381 382 spin_lock_irqsave(&port->lock, flags); 383 384 UART_ALL_IRQ_DISABLE(port); 385 386 UART_SET_BAUDL(port, uartl); 387 UART_SET_BAUDH(port, uarth); 388 389 UART_RX_IRQ_ENABLE(port); 390 391 /* 392 * UART doesn't support Parity/Hardware Flow Control; 393 * Only supports 8N1 character size 394 */ 395 new->c_cflag &= ~(CMSPAR|CRTSCTS|CSIZE); 396 new->c_cflag |= CS8; 397 398 if (old) 399 tty_termios_copy_hw(new, old); 400 401 /* Don't rewrite B0 */ 402 if (tty_termios_baud_rate(new)) 403 tty_termios_encode_baud_rate(new, baud, baud); 404 405 uart_update_timeout(port, new->c_cflag, baud); 406 407 spin_unlock_irqrestore(&port->lock, flags); 408} 409 410static const char *arc_serial_type(struct uart_port *port) 411{ 412 return port->type == PORT_ARC ? DRIVER_NAME : NULL; 413} 414 415static void arc_serial_release_port(struct uart_port *port) 416{ 417} 418 419static int arc_serial_request_port(struct uart_port *port) 420{ 421 return 0; 422} 423 424/* 425 * Verify the new serial_struct (for TIOCSSERIAL). 426 */ 427static int 428arc_serial_verify_port(struct uart_port *port, struct serial_struct *ser) 429{ 430 if (port->type != PORT_UNKNOWN && ser->type != PORT_ARC) 431 return -EINVAL; 432 433 return 0; 434} 435 436/* 437 * Configure/autoconfigure the port. 438 */ 439static void arc_serial_config_port(struct uart_port *port, int flags) 440{ 441 if (flags & UART_CONFIG_TYPE) 442 port->type = PORT_ARC; 443} 444 445#ifdef CONFIG_CONSOLE_POLL 446 447static void arc_serial_poll_putchar(struct uart_port *port, unsigned char chr) 448{ 449 while (!(UART_GET_STATUS(port) & TXEMPTY)) 450 cpu_relax(); 451 452 UART_SET_DATA(port, chr); 453} 454 455static int arc_serial_poll_getchar(struct uart_port *port) 456{ 457 unsigned char chr; 458 459 while (!(UART_GET_STATUS(port) & RXEMPTY)) 460 cpu_relax(); 461 462 chr = UART_GET_DATA(port); 463 return chr; 464} 465#endif 466 467static struct uart_ops arc_serial_pops = { 468 .tx_empty = arc_serial_tx_empty, 469 .set_mctrl = arc_serial_set_mctrl, 470 .get_mctrl = arc_serial_get_mctrl, 471 .stop_tx = arc_serial_stop_tx, 472 .start_tx = arc_serial_start_tx, 473 .stop_rx = arc_serial_stop_rx, 474 .break_ctl = arc_serial_break_ctl, 475 .startup = arc_serial_startup, 476 .shutdown = arc_serial_shutdown, 477 .set_termios = arc_serial_set_termios, 478 .type = arc_serial_type, 479 .release_port = arc_serial_release_port, 480 .request_port = arc_serial_request_port, 481 .config_port = arc_serial_config_port, 482 .verify_port = arc_serial_verify_port, 483#ifdef CONFIG_CONSOLE_POLL 484 .poll_put_char = arc_serial_poll_putchar, 485 .poll_get_char = arc_serial_poll_getchar, 486#endif 487}; 488 489#ifdef CONFIG_SERIAL_ARC_CONSOLE 490 491static int arc_serial_console_setup(struct console *co, char *options) 492{ 493 struct uart_port *port; 494 int baud = 115200; 495 int bits = 8; 496 int parity = 'n'; 497 int flow = 'n'; 498 499 if (co->index < 0 || co->index >= CONFIG_SERIAL_ARC_NR_PORTS) 500 return -ENODEV; 501 502 /* 503 * The uart port backing the console (e.g. ttyARC1) might not have been 504 * init yet. If so, defer the console setup to after the port. 505 */ 506 port = &arc_uart_ports[co->index].port; 507 if (!port->membase) 508 return -ENODEV; 509 510 if (options) 511 uart_parse_options(options, &baud, &parity, &bits, &flow); 512 513 /* 514 * Serial core will call port->ops->set_termios( ) 515 * which will set the baud reg 516 */ 517 return uart_set_options(port, co, baud, parity, bits, flow); 518} 519 520static void arc_serial_console_putchar(struct uart_port *port, int ch) 521{ 522 while (!(UART_GET_STATUS(port) & TXEMPTY)) 523 cpu_relax(); 524 525 UART_SET_DATA(port, (unsigned char)ch); 526} 527 528/* 529 * Interrupts are disabled on entering 530 */ 531static void arc_serial_console_write(struct console *co, const char *s, 532 unsigned int count) 533{ 534 struct uart_port *port = &arc_uart_ports[co->index].port; 535 unsigned long flags; 536 537 spin_lock_irqsave(&port->lock, flags); 538 uart_console_write(port, s, count, arc_serial_console_putchar); 539 spin_unlock_irqrestore(&port->lock, flags); 540} 541 542static struct console arc_console = { 543 .name = ARC_SERIAL_DEV_NAME, 544 .write = arc_serial_console_write, 545 .device = uart_console_device, 546 .setup = arc_serial_console_setup, 547 .flags = CON_PRINTBUFFER, 548 .index = -1, 549 .data = &arc_uart_driver 550}; 551 552static __init void arc_early_serial_write(struct console *con, const char *s, 553 unsigned int n) 554{ 555 struct earlycon_device *dev = con->data; 556 557 uart_console_write(&dev->port, s, n, arc_serial_console_putchar); 558} 559 560static int __init arc_early_console_setup(struct earlycon_device *dev, 561 const char *opt) 562{ 563 struct uart_port *port = &dev->port; 564 unsigned int l, h, hw_val; 565 566 if (!dev->port.membase) 567 return -ENODEV; 568 569 hw_val = port->uartclk / (dev->baud * 4) - 1; 570 l = hw_val & 0xFF; 571 h = (hw_val >> 8) & 0xFF; 572 573 UART_SET_BAUDL(port, l); 574 UART_SET_BAUDH(port, h); 575 576 dev->con->write = arc_early_serial_write; 577 return 0; 578} 579EARLYCON_DECLARE(arc_uart, arc_early_console_setup); 580OF_EARLYCON_DECLARE(arc_uart, "snps,arc-uart", arc_early_console_setup); 581 582#endif /* CONFIG_SERIAL_ARC_CONSOLE */ 583 584static int arc_serial_probe(struct platform_device *pdev) 585{ 586 struct device_node *np = pdev->dev.of_node; 587 struct arc_uart_port *uart; 588 struct uart_port *port; 589 int dev_id; 590 u32 val; 591 592 /* no device tree device */ 593 if (!np) 594 return -ENODEV; 595 596 dev_id = of_alias_get_id(np, "serial"); 597 if (dev_id < 0) 598 dev_id = 0; 599 600 uart = &arc_uart_ports[dev_id]; 601 port = &uart->port; 602 603 if (of_property_read_u32(np, "clock-frequency", &val)) { 604 dev_err(&pdev->dev, "clock-frequency property NOTset\n"); 605 return -EINVAL; 606 } 607 port->uartclk = val; 608 609 if (of_property_read_u32(np, "current-speed", &val)) { 610 dev_err(&pdev->dev, "current-speed property NOT set\n"); 611 return -EINVAL; 612 } 613 uart->baud = val; 614 615 port->membase = of_iomap(np, 0); 616 if (!port->membase) 617 /* No point of dev_err since UART itself is hosed here */ 618 return -ENXIO; 619 620 port->irq = irq_of_parse_and_map(np, 0); 621 622 port->dev = &pdev->dev; 623 port->iotype = UPIO_MEM; 624 port->flags = UPF_BOOT_AUTOCONF; 625 port->line = dev_id; 626 port->ops = &arc_serial_pops; 627 628 port->fifosize = ARC_UART_TX_FIFO_SIZE; 629 630 /* 631 * uart_insert_char( ) uses it in decideding whether to ignore a 632 * char or not. Explicitly setting it here, removes the subtelty 633 */ 634 port->ignore_status_mask = 0; 635 636 return uart_add_one_port(&arc_uart_driver, &arc_uart_ports[dev_id].port); 637} 638 639static int arc_serial_remove(struct platform_device *pdev) 640{ 641 /* This will never be called */ 642 return 0; 643} 644 645static const struct of_device_id arc_uart_dt_ids[] = { 646 { .compatible = "snps,arc-uart" }, 647 { /* Sentinel */ } 648}; 649MODULE_DEVICE_TABLE(of, arc_uart_dt_ids); 650 651static struct platform_driver arc_platform_driver = { 652 .probe = arc_serial_probe, 653 .remove = arc_serial_remove, 654 .driver = { 655 .name = DRIVER_NAME, 656 .of_match_table = arc_uart_dt_ids, 657 }, 658}; 659 660static int __init arc_serial_init(void) 661{ 662 int ret; 663 664 ret = uart_register_driver(&arc_uart_driver); 665 if (ret) 666 return ret; 667 668 ret = platform_driver_register(&arc_platform_driver); 669 if (ret) 670 uart_unregister_driver(&arc_uart_driver); 671 672 return ret; 673} 674 675static void __exit arc_serial_exit(void) 676{ 677 platform_driver_unregister(&arc_platform_driver); 678 uart_unregister_driver(&arc_uart_driver); 679} 680 681module_init(arc_serial_init); 682module_exit(arc_serial_exit); 683 684MODULE_LICENSE("GPL"); 685MODULE_ALIAS("platform:" DRIVER_NAME); 686MODULE_AUTHOR("Vineet Gupta"); 687MODULE_DESCRIPTION("ARC(Synopsys) On-Chip(fpga) serial driver"); 688