137 	val = readl_relaxed(port->membase + reg);  in stm32_set_bits()
139 	writel_relaxed(val, port->membase + reg);  in stm32_set_bits()
146 	val = readl_relaxed(port->membase + reg);  in stm32_clr_bits()
148 	writel_relaxed(val, port->membase + reg);  in stm32_clr_bits()
161 	while ((sr = readl_relaxed(port->membase + USART_SR)) & USART_SR_RXNE) {  in stm32_receive_chars()
163 		c = readl_relaxed(port->membase + USART_DR);  in stm32_receive_chars()
205 		writel_relaxed(port->x_char, port->membase + USART_DR);  in stm32_transmit_chars()
221 	writel_relaxed(xmit->buf[xmit->tail], port->membase + USART_DR);  in stm32_transmit_chars()
239 	sr = readl_relaxed(port->membase + USART_SR);  in stm32_interrupt()
254 	return readl_relaxed(port->membase + USART_SR) & USART_SR_TXE;  in stm32_tx_empty()
363 	writel_relaxed(0, port->membase + USART_CR1);  in stm32_set_termios()
405 	writel_relaxed(mantissa | fraction, port->membase + USART_BRR);  in stm32_set_termios()
433 	writel_relaxed(cr3, port->membase + USART_CR3);  in stm32_set_termios()
434 	writel_relaxed(cr2, port->membase + USART_CR2);  in stm32_set_termios()
435 	writel_relaxed(cr1, port->membase + USART_CR1);  in stm32_set_termios()
522 	port->membase = devm_ioremap_resource(&pdev->dev, res);  in stm32_init_port()
523 	if (IS_ERR(port->membase))  in stm32_init_port()
524 		return PTR_ERR(port->membase);  in stm32_init_port()
611 	while (!(readl_relaxed(port->membase + USART_SR) & USART_SR_TXE))  in stm32_console_putchar()
614 	writel_relaxed(ch, port->membase + USART_DR);  in stm32_console_putchar()
633 	old_cr1 = readl_relaxed(port->membase + USART_CR1);  in stm32_console_write()
635 	writel_relaxed(new_cr1, port->membase + USART_CR1);  in stm32_console_write()
640 	writel_relaxed(old_cr1, port->membase + USART_CR1);  in stm32_console_write()
666 	if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)  in stm32_console_setup()