Lines Matching refs:membase
296 ucr->ucr1 = readl(port->membase + UCR1); in imx_port_ucrs_save()
297 ucr->ucr2 = readl(port->membase + UCR2); in imx_port_ucrs_save()
298 ucr->ucr3 = readl(port->membase + UCR3); in imx_port_ucrs_save()
305 writel(ucr->ucr1, port->membase + UCR1); in imx_port_ucrs_restore()
306 writel(ucr->ucr2, port->membase + UCR2); in imx_port_ucrs_restore()
307 writel(ucr->ucr3, port->membase + UCR3); in imx_port_ucrs_restore()
371 temp = readl(port->membase + UCR1); in imx_stop_tx()
372 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); in imx_stop_tx()
376 readl(port->membase + USR2) & USR2_TXDC) { in imx_stop_tx()
377 temp = readl(port->membase + UCR2); in imx_stop_tx()
382 writel(temp, port->membase + UCR2); in imx_stop_tx()
384 temp = readl(port->membase + UCR4); in imx_stop_tx()
386 writel(temp, port->membase + UCR4); in imx_stop_tx()
407 temp = readl(sport->port.membase + UCR2); in imx_stop_rx()
408 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); in imx_stop_rx()
411 temp = readl(sport->port.membase + UCR1); in imx_stop_rx()
412 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); in imx_stop_rx()
433 writel(sport->port.x_char, sport->port.membase + URTX0); in imx_transmit_buffer()
449 temp = readl(sport->port.membase + UCR1); in imx_transmit_buffer()
453 writel(temp, sport->port.membase + UCR1); in imx_transmit_buffer()
455 writel(temp, sport->port.membase + UCR1); in imx_transmit_buffer()
461 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { in imx_transmit_buffer()
464 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); in imx_transmit_buffer()
488 temp = readl(sport->port.membase + UCR1); in dma_tx_callback()
490 writel(temp, sport->port.membase + UCR1); in dma_tx_callback()
562 temp = readl(sport->port.membase + UCR1); in imx_dma_tx()
564 writel(temp, sport->port.membase + UCR1); in imx_dma_tx()
583 temp = readl(port->membase + UCR2); in imx_start_tx()
588 writel(temp, port->membase + UCR2); in imx_start_tx()
590 temp = readl(port->membase + UCR4); in imx_start_tx()
592 writel(temp, port->membase + UCR4); in imx_start_tx()
596 temp = readl(sport->port.membase + UCR1); in imx_start_tx()
597 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); in imx_start_tx()
604 temp = readl(sport->port.membase + UCR1); in imx_start_tx()
607 writel(temp, sport->port.membase + UCR1); in imx_start_tx()
626 writel(USR1_RTSD, sport->port.membase + USR1); in imx_rtsint()
627 val = readl(sport->port.membase + USR1) & USR1_RTSS; in imx_rtsint()
655 while (readl(sport->port.membase + USR2) & USR2_RDR) { in imx_rxint()
659 rx = readl(sport->port.membase + URXD0); in imx_rxint()
661 temp = readl(sport->port.membase + USR2); in imx_rxint()
663 writel(USR2_BRCD, sport->port.membase + USR2); in imx_rxint()
728 temp = readl(sport->port.membase + USR2); in imx_dma_rxint()
733 temp = readl(sport->port.membase + UCR1); in imx_dma_rxint()
735 writel(temp, sport->port.membase + UCR1); in imx_dma_rxint()
737 temp = readl(sport->port.membase + UCR2); in imx_dma_rxint()
739 writel(temp, sport->port.membase + UCR2); in imx_dma_rxint()
754 sts = readl(sport->port.membase + USR1); in imx_int()
755 sts2 = readl(sport->port.membase + USR2); in imx_int()
765 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || in imx_int()
767 readl(sport->port.membase + UCR4) & UCR4_TCEN)) in imx_int()
774 writel(USR1_AWAKE, sport->port.membase + USR1); in imx_int()
778 writel(USR2_ORE, sport->port.membase + USR2); in imx_int()
792 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; in imx_tx_empty()
809 if (readl(sport->port.membase + USR1) & USR1_RTSS) in imx_get_mctrl()
812 if (readl(sport->port.membase + UCR2) & UCR2_CTS) in imx_get_mctrl()
815 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) in imx_get_mctrl()
827 temp = readl(sport->port.membase + UCR2); in imx_set_mctrl()
831 writel(temp, sport->port.membase + UCR2); in imx_set_mctrl()
834 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; in imx_set_mctrl()
837 writel(temp, sport->port.membase + uts_reg(sport)); in imx_set_mctrl()
850 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; in imx_break_ctl()
855 writel(temp, sport->port.membase + UCR1); in imx_break_ctl()
869 temp = readl(sport->port.membase + UCR1); in imx_rx_dma_done()
871 writel(temp, sport->port.membase + UCR1); in imx_rx_dma_done()
873 temp = readl(sport->port.membase + UCR2); in imx_rx_dma_done()
875 writel(temp, sport->port.membase + UCR2); in imx_rx_dma_done()
932 if (readl(sport->port.membase + USR2) & USR2_RDR) in dma_rx_callback()
979 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); in imx_setup_ufcr()
981 writel(val, sport->port.membase + UFCR); in imx_setup_ufcr()
1066 temp = readl(sport->port.membase + UCR1); in imx_enable_dma()
1068 writel(temp, sport->port.membase + UCR1); in imx_enable_dma()
1070 temp = readl(sport->port.membase + UCR2); in imx_enable_dma()
1072 writel(temp, sport->port.membase + UCR2); in imx_enable_dma()
1084 temp = readl(sport->port.membase + UCR1); in imx_disable_dma()
1086 writel(temp, sport->port.membase + UCR1); in imx_disable_dma()
1089 temp = readl(sport->port.membase + UCR2); in imx_disable_dma()
1091 writel(temp, sport->port.membase + UCR2); in imx_disable_dma()
1121 temp = readl(sport->port.membase + UCR4); in imx_startup()
1127 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); in imx_startup()
1138 temp = readl(sport->port.membase + UCR2); in imx_startup()
1140 writel(temp, sport->port.membase + UCR2); in imx_startup()
1142 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) in imx_startup()
1148 writel(USR1_RTSD, sport->port.membase + USR1); in imx_startup()
1149 writel(USR2_ORE, sport->port.membase + USR2); in imx_startup()
1154 temp = readl(sport->port.membase + UCR1); in imx_startup()
1157 writel(temp, sport->port.membase + UCR1); in imx_startup()
1159 temp = readl(sport->port.membase + UCR4); in imx_startup()
1161 writel(temp, sport->port.membase + UCR4); in imx_startup()
1163 temp = readl(sport->port.membase + UCR2); in imx_startup()
1167 writel(temp, sport->port.membase + UCR2); in imx_startup()
1170 temp = readl(sport->port.membase + UCR3); in imx_startup()
1172 writel(temp, sport->port.membase + UCR3); in imx_startup()
1211 temp = readl(sport->port.membase + UCR2); in imx_shutdown()
1213 writel(temp, sport->port.membase + UCR2); in imx_shutdown()
1226 temp = readl(sport->port.membase + UCR1); in imx_shutdown()
1229 writel(temp, sport->port.membase + UCR1); in imx_shutdown()
1251 temp = readl(sport->port.membase + UCR1); in imx_flush_buffer()
1253 writel(temp, sport->port.membase + UCR1); in imx_flush_buffer()
1264 ubir = readl(sport->port.membase + UBIR); in imx_flush_buffer()
1265 ubmr = readl(sport->port.membase + UBMR); in imx_flush_buffer()
1266 uts = readl(sport->port.membase + IMX21_UTS); in imx_flush_buffer()
1268 temp = readl(sport->port.membase + UCR2); in imx_flush_buffer()
1270 writel(temp, sport->port.membase + UCR2); in imx_flush_buffer()
1272 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) in imx_flush_buffer()
1276 writel(ubir, sport->port.membase + UBIR); in imx_flush_buffer()
1277 writel(ubmr, sport->port.membase + UBMR); in imx_flush_buffer()
1278 writel(uts, sport->port.membase + IMX21_UTS); in imx_flush_buffer()
1383 old_ucr1 = readl(sport->port.membase + UCR1); in imx_set_termios()
1385 sport->port.membase + UCR1); in imx_set_termios()
1387 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) in imx_set_termios()
1391 old_ucr2 = readl(sport->port.membase + UCR2); in imx_set_termios()
1393 sport->port.membase + UCR2); in imx_set_termios()
1419 ufcr = readl(sport->port.membase + UFCR); in imx_set_termios()
1423 writel(ufcr, sport->port.membase + UFCR); in imx_set_termios()
1425 writel(num, sport->port.membase + UBIR); in imx_set_termios()
1426 writel(denom, sport->port.membase + UBMR); in imx_set_termios()
1430 sport->port.membase + IMX21_ONEMS); in imx_set_termios()
1432 writel(old_ucr1, sport->port.membase + UCR1); in imx_set_termios()
1435 writel(ucr2 | old_ucr2, sport->port.membase + UCR2); in imx_set_termios()
1509 temp = readl(sport->port.membase + UCR1); in imx_poll_init()
1514 writel(temp, sport->port.membase + UCR1); in imx_poll_init()
1516 temp = readl(sport->port.membase + UCR2); in imx_poll_init()
1518 writel(temp, sport->port.membase + UCR2); in imx_poll_init()
1527 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) in imx_poll_get_char()
1530 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; in imx_poll_get_char()
1539 status = readl_relaxed(port->membase + USR1); in imx_poll_put_char()
1543 writel_relaxed(c, port->membase + URTX0); in imx_poll_put_char()
1547 status = readl_relaxed(port->membase + USR2); in imx_poll_put_char()
1570 temp = readl(sport->port.membase + UCR2); in imx_rs485_config()
1576 writel(temp, sport->port.membase + UCR2); in imx_rs485_config()
1614 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) in imx_console_putchar()
1617 writel(ch, sport->port.membase + URTX0); in imx_console_putchar()
1660 writel(ucr1, sport->port.membase + UCR1); in imx_console_write()
1662 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); in imx_console_write()
1670 while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); in imx_console_write()
1690 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { in imx_console_get_options()
1696 ucr2 = readl(sport->port.membase + UCR2); in imx_console_get_options()
1711 ubir = readl(sport->port.membase + UBIR) & 0xffff; in imx_console_get_options()
1712 ubmr = readl(sport->port.membase + UBMR) & 0xffff; in imx_console_get_options()
1714 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; in imx_console_get_options()
1809 while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL) in imx_console_early_putchar()
1812 writel_relaxed(ch, port->membase + URTX0); in imx_console_early_putchar()
1826 if (!dev->port.membase) in imx_console_early_setup()
1937 sport->port.membase = base; in serial_imx_probe()
1973 reg = readl_relaxed(sport->port.membase + UCR1); in serial_imx_probe()
1976 writel_relaxed(reg, sport->port.membase + UCR1); in serial_imx_probe()
2020 writel(sport->saved_reg[4], sport->port.membase + UFCR); in serial_imx_restore_context()
2021 writel(sport->saved_reg[5], sport->port.membase + UESC); in serial_imx_restore_context()
2022 writel(sport->saved_reg[6], sport->port.membase + UTIM); in serial_imx_restore_context()
2023 writel(sport->saved_reg[7], sport->port.membase + UBIR); in serial_imx_restore_context()
2024 writel(sport->saved_reg[8], sport->port.membase + UBMR); in serial_imx_restore_context()
2025 writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS); in serial_imx_restore_context()
2026 writel(sport->saved_reg[0], sport->port.membase + UCR1); in serial_imx_restore_context()
2027 writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2); in serial_imx_restore_context()
2028 writel(sport->saved_reg[2], sport->port.membase + UCR3); in serial_imx_restore_context()
2029 writel(sport->saved_reg[3], sport->port.membase + UCR4); in serial_imx_restore_context()
2036 sport->saved_reg[0] = readl(sport->port.membase + UCR1); in serial_imx_save_context()
2037 sport->saved_reg[1] = readl(sport->port.membase + UCR2); in serial_imx_save_context()
2038 sport->saved_reg[2] = readl(sport->port.membase + UCR3); in serial_imx_save_context()
2039 sport->saved_reg[3] = readl(sport->port.membase + UCR4); in serial_imx_save_context()
2040 sport->saved_reg[4] = readl(sport->port.membase + UFCR); in serial_imx_save_context()
2041 sport->saved_reg[5] = readl(sport->port.membase + UESC); in serial_imx_save_context()
2042 sport->saved_reg[6] = readl(sport->port.membase + UTIM); in serial_imx_save_context()
2043 sport->saved_reg[7] = readl(sport->port.membase + UBIR); in serial_imx_save_context()
2044 sport->saved_reg[8] = readl(sport->port.membase + UBMR); in serial_imx_save_context()
2045 sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS); in serial_imx_save_context()
2053 val = readl(sport->port.membase + UCR3); in serial_imx_enable_wakeup()
2058 writel(val, sport->port.membase + UCR3); in serial_imx_enable_wakeup()
2060 val = readl(sport->port.membase + UCR1); in serial_imx_enable_wakeup()
2065 writel(val, sport->port.membase + UCR1); in serial_imx_enable_wakeup()