82 	cr = readb(uap->port.membase + UART010_CR);  in pl010_stop_tx()
84 	writel(cr, uap->port.membase + UART010_CR);  in pl010_stop_tx()
93 	cr = readb(uap->port.membase + UART010_CR);  in pl010_start_tx()
95 	writel(cr, uap->port.membase + UART010_CR);  in pl010_start_tx()
104 	cr = readb(uap->port.membase + UART010_CR);  in pl010_stop_rx()
106 	writel(cr, uap->port.membase + UART010_CR);  in pl010_stop_rx()
114 	cr = readb(uap->port.membase + UART010_CR);  in pl010_disable_ms()
116 	writel(cr, uap->port.membase + UART010_CR);  in pl010_disable_ms()
125 	cr = readb(uap->port.membase + UART010_CR);  in pl010_enable_ms()
127 	writel(cr, uap->port.membase + UART010_CR);  in pl010_enable_ms()
134 	status = readb(uap->port.membase + UART01x_FR);  in pl010_rx_chars()
136 		ch = readb(uap->port.membase + UART01x_DR);  in pl010_rx_chars()
145 		rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;  in pl010_rx_chars()
147 			writel(0, uap->port.membase + UART01x_ECR);  in pl010_rx_chars()
177 		status = readb(uap->port.membase + UART01x_FR);  in pl010_rx_chars()
190 		writel(uap->port.x_char, uap->port.membase + UART01x_DR);  in pl010_tx_chars()
202 		writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);  in pl010_tx_chars()
220 	writel(0, uap->port.membase + UART010_ICR);  in pl010_modem_status()
222 	status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl010_modem_status()
250 	status = readb(uap->port.membase + UART010_IIR);  in pl010_int()
263 			status = readb(uap->port.membase + UART010_IIR);  in pl010_int()
278 	unsigned int status = readb(uap->port.membase + UART01x_FR);  in pl010_tx_empty()
289 	status = readb(uap->port.membase + UART01x_FR);  in pl010_get_mctrl()
306 		uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);  in pl010_set_mctrl()
317 	lcr_h = readb(uap->port.membase + UART010_LCRH);  in pl010_break_ctl()
322 	writel(lcr_h, uap->port.membase + UART010_LCRH);  in pl010_break_ctl()
351 	uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl010_startup()
357 	       uap->port.membase + UART010_CR);  in pl010_startup()
380 	writel(0, uap->port.membase + UART010_CR);  in pl010_shutdown()
383 	writel(readb(uap->port.membase + UART010_LCRH) &  in pl010_shutdown()
385 	       uap->port.membase + UART010_LCRH);  in pl010_shutdown()
469 	old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;  in pl010_set_termios()
474 	writel(0, uap->port.membase + UART010_CR);  in pl010_set_termios()
478 	writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);  in pl010_set_termios()
479 	writel(quot & 0xff, uap->port.membase + UART010_LCRL);  in pl010_set_termios()
486 	writel(lcr_h, uap->port.membase + UART010_LCRH);  in pl010_set_termios()
487 	writel(old_cr, uap->port.membase + UART010_CR);  in pl010_set_termios()
588 		status = readb(uap->port.membase + UART01x_FR);  in pl010_console_putchar()
591 	writel(ch, uap->port.membase + UART01x_DR);  in pl010_console_putchar()
605 	old_cr = readb(uap->port.membase + UART010_CR);  in pl010_console_write()
606 	writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);  in pl010_console_write()
615 		status = readb(uap->port.membase + UART01x_FR);  in pl010_console_write()
618 	writel(old_cr, uap->port.membase + UART010_CR);  in pl010_console_write()
627 	if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {  in pl010_console_get_options()
629 		lcr_h = readb(uap->port.membase + UART010_LCRH);  in pl010_console_get_options()
644 		quot = readb(uap->port.membase + UART010_LCRL) |  in pl010_console_get_options()
645 		       readb(uap->port.membase + UART010_LCRM) << 8;  in pl010_console_get_options()
739 	uap->port.membase = base;  in pl010_probe()