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Searched refs:WREG32 (Results 1 – 67 of 67) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Drv515.c148 WREG32(R_000300_VGA_RENDER_CONTROL, in rv515_vga_render_disable()
216 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); in rv515_mc_rreg()
218 WREG32(MC_IND_INDEX, 0); in rv515_mc_rreg()
229 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); in rv515_mc_wreg()
230 WREG32(MC_IND_DATA, (v)); in rv515_mc_wreg()
231 WREG32(MC_IND_INDEX, 0); in rv515_mc_wreg()
305 WREG32(R_000300_VGA_RENDER_CONTROL, 0); in rv515_mc_stop()
314 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
316 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
317 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
[all …]
Dradeon_bios.c264 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); in ni_read_disabled_bios()
267 WREG32(AVIVO_D1VGA_CONTROL, in ni_read_disabled_bios()
270 WREG32(AVIVO_D2VGA_CONTROL, in ni_read_disabled_bios()
273 WREG32(AVIVO_VGA_RENDER_CONTROL, in ni_read_disabled_bios()
276 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); in ni_read_disabled_bios()
281 WREG32(R600_BUS_CNTL, bus_cntl); in ni_read_disabled_bios()
283 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); in ni_read_disabled_bios()
284 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); in ni_read_disabled_bios()
285 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); in ni_read_disabled_bios()
287 WREG32(R600_ROM_CNTL, rom_cntl); in ni_read_disabled_bios()
[all …]
Dvce_v2_0.c41 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
45 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
49 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
51 WREG32(VCE_CGTT_CLK_OVERRIDE, 0); in vce_v2_0_set_sw_cg()
56 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
61 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
65 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_sw_cg()
81 WREG32(VCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_dyn_cg()
87 WREG32(VCE_UENC_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
92 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); in vce_v2_0_set_dyn_cg()
[all …]
Drv770.c812 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
816 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
817 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
819 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
820 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); in rv770_page_flip()
822 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
824 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
837 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
904 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
907 WREG32(VM_L2_CNTL2, 0); in rv770_pcie_gart_enable()
[all …]
Duvd_v1_0.c70 WREG32(UVD_RBC_RB_WPTR, ring->wptr); in uvd_v1_0_set_wptr()
123 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v1_0_resume()
124 WREG32(UVD_VCPU_CACHE_SIZE0, size); in uvd_v1_0_resume()
128 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); in uvd_v1_0_resume()
129 WREG32(UVD_VCPU_CACHE_SIZE1, size); in uvd_v1_0_resume()
133 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); in uvd_v1_0_resume()
134 WREG32(UVD_VCPU_CACHE_SIZE2, size); in uvd_v1_0_resume()
138 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); in uvd_v1_0_resume()
142 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); in uvd_v1_0_resume()
144 WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); in uvd_v1_0_resume()
[all …]
Dr600.c293 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
820 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
828 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
836 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
844 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_hpd_set_polarity()
852 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_hpd_set_polarity()
861 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_hpd_set_polarity()
874 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
882 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
890 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
[all …]
Dradeon_i2c.c117 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | in pre_xfer()
120 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | in pre_xfer()
131 WREG32(rec->mask_clk_reg, temp); in pre_xfer()
136 WREG32(rec->a_clk_reg, temp); in pre_xfer()
139 WREG32(rec->a_data_reg, temp); in pre_xfer()
143 WREG32(rec->en_clk_reg, temp); in pre_xfer()
146 WREG32(rec->en_data_reg, temp); in pre_xfer()
150 WREG32(rec->mask_clk_reg, temp); in pre_xfer()
154 WREG32(rec->mask_data_reg, temp); in pre_xfer()
169 WREG32(rec->mask_clk_reg, temp); in post_xfer()
[all …]
Dni.c649 WREG32(MC_SHARED_BLACKOUT_CNTL, 1); in ni_mc_load_microcode()
653 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
654 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ni_mc_load_microcode()
658 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in ni_mc_load_microcode()
659 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in ni_mc_load_microcode()
664 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in ni_mc_load_microcode()
667 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ni_mc_load_microcode()
668 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in ni_mc_load_microcode()
669 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in ni_mc_load_microcode()
679 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); in ni_mc_load_microcode()
[all …]
Devergreen.c1110 WREG32(CG_SCRATCH1, cg_scratch); in sumo_set_uvd_clocks()
1271 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
1352 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in evergreen_page_flip()
1355 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1357 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip()
1360 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1362 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip()
1375 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in evergreen_page_flip()
1628 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_prepare()
1653 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_finish()
[all …]
Devergreen_hdmi.c64 WREG32(AZ_HOT_PLUG_CONTROL, tmp); in dce4_audio_enable()
80 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
83 WREG32(HDMI_ACR_PACKET_CONTROL + offset, in evergreen_hdmi_update_acr()
87 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz)); in evergreen_hdmi_update_acr()
88 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz); in evergreen_hdmi_update_acr()
90 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz)); in evergreen_hdmi_update_acr()
91 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz); in evergreen_hdmi_update_acr()
93 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz)); in evergreen_hdmi_update_acr()
94 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz); in evergreen_hdmi_update_acr()
213 WREG32(AFMT_AVI_INFO0 + offset, in evergreen_set_avi_packet()
[all …]
Dradeon_legacy_encoders.c87 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); in radeon_legacy_lvds_update()
90 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); in radeon_legacy_lvds_update()
95 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); in radeon_legacy_lvds_update()
105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
115 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
118 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
122 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_update()
233 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); in radeon_legacy_lvds_mode_set()
234 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); in radeon_legacy_lvds_mode_set()
235 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); in radeon_legacy_lvds_mode_set()
[all …]
Dsi.c1598 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); in si_mc_load_microcode()
1602 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1603 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in si_mc_load_microcode()
1608 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in si_mc_load_microcode()
1609 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in si_mc_load_microcode()
1611 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in si_mc_load_microcode()
1612 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in si_mc_load_microcode()
1618 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in si_mc_load_microcode()
1620 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in si_mc_load_microcode()
1624 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
[all …]
Dcik.c223 WREG32(PCIE_INDEX, reg); in cik_pciep_rreg()
235 WREG32(PCIE_INDEX, reg); in cik_pciep_wreg()
237 WREG32(PCIE_DATA, v); in cik_pciep_wreg()
1831 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl); in cik_srbm_select()
1890 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); in ci_mc_load_microcode()
1894 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1895 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ci_mc_load_microcode()
1900 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1901 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1903 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in ci_mc_load_microcode()
[all …]
Dradeon_cursor.c42 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
49 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
56 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
94 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); in radeon_show_cursor()
95 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | in radeon_show_cursor()
99 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); in radeon_show_cursor()
100 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | in radeon_show_cursor()
105 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); in radeon_show_cursor()
108 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); in radeon_show_cursor()
186 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); in radeon_cursor_move_locked()
[all …]
Duvd_v4_2.c46 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v4_2_resume()
47 WREG32(UVD_VCPU_CACHE_SIZE0, size); in uvd_v4_2_resume()
51 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); in uvd_v4_2_resume()
52 WREG32(UVD_VCPU_CACHE_SIZE1, size); in uvd_v4_2_resume()
56 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); in uvd_v4_2_resume()
57 WREG32(UVD_VCPU_CACHE_SIZE2, size); in uvd_v4_2_resume()
61 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); in uvd_v4_2_resume()
65 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); in uvd_v4_2_resume()
Dvce_v1_0.c80 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
82 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
101 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start()
102 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_start()
103 WREG32(VCE_RB_BASE_LO, ring->gpu_addr); in vce_v1_0_start()
104 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
105 WREG32(VCE_RB_SIZE, ring->ring_size / 4); in vce_v1_0_start()
108 WREG32(VCE_RB_RPTR2, ring->wptr); in vce_v1_0_start()
109 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_start()
110 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); in vce_v1_0_start()
[all …]
Dradeon_dp_auxch.c101 WREG32(chan->rec.mask_clk_reg, tmp); in radeon_dp_aux_transfer_native()
110 WREG32(AUX_CONTROL + aux_offset[instance], tmp); in radeon_dp_aux_transfer_native()
113 WREG32(AUX_SW_CONTROL + aux_offset[instance], in radeon_dp_aux_transfer_native()
115 WREG32(AUX_SW_CONTROL + aux_offset[instance], in radeon_dp_aux_transfer_native()
121 WREG32(AUX_SW_DATA + aux_offset[instance], in radeon_dp_aux_transfer_native()
125 WREG32(AUX_SW_DATA + aux_offset[instance], in radeon_dp_aux_transfer_native()
129 WREG32(AUX_SW_DATA + aux_offset[instance], in radeon_dp_aux_transfer_native()
133 WREG32(AUX_SW_DATA + aux_offset[instance], in radeon_dp_aux_transfer_native()
139 WREG32(AUX_SW_DATA + aux_offset[instance], in radeon_dp_aux_transfer_native()
145 WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); in radeon_dp_aux_transfer_native()
[all …]
Drs600.c121 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
124 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
126 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
139 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
199 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
202 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
205 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
208 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); in avivo_program_fmt()
230 WREG32(voltage->gpio.reg, tmp); in rs600_pm_misc()
239 WREG32(voltage->gpio.reg, tmp); in rs600_pm_misc()
[all …]
Dradeon_legacy_tv.c282 WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); in radeon_wait_pll_lock()
294 WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); in radeon_wait_pll_lock()
306 WREG32(RADEON_TV_HOST_WRITE_DATA, value); in radeon_legacy_tv_write_fifo()
308 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); in radeon_legacy_tv_write_fifo()
309 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); in radeon_legacy_tv_write_fifo()
317 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); in radeon_legacy_tv_write_fifo()
328 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
329 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);
337 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
393 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); in radeon_restore_tv_timing_tables()
[all …]
Duvd_v2_2.c115 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); in uvd_v2_2_resume()
116 WREG32(UVD_VCPU_CACHE_SIZE0, size); in uvd_v2_2_resume()
120 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); in uvd_v2_2_resume()
121 WREG32(UVD_VCPU_CACHE_SIZE1, size); in uvd_v2_2_resume()
125 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); in uvd_v2_2_resume()
126 WREG32(UVD_VCPU_CACHE_SIZE2, size); in uvd_v2_2_resume()
130 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); in uvd_v2_2_resume()
134 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); in uvd_v2_2_resume()
195 WREG32(UVD_VCPU_CHIP_ID, chip_id); in uvd_v2_2_resume()
Dcik_sdma.c121 WREG32(reg, (ring->wptr << 2) & 0x3fffc); in cik_sdma_set_wptr()
266 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
267 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); in cik_sdma_gfx_stop()
277 WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1); in cik_sdma_gfx_stop()
280 WREG32(SRBM_SOFT_RESET, 0); in cik_sdma_gfx_stop()
319 WREG32(SDMA0_CNTL + reg_offset, value); in cik_sdma_ctx_switch_enable()
351 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); in cik_sdma_enable()
384 WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); in cik_sdma_gfx_resume()
385 WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); in cik_sdma_gfx_resume()
393 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_resume()
[all …]
Ddce3_1_afmt.c156 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); in dce3_2_audio_set_dto()
157 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); in dce3_2_audio_set_dto()
158 WREG32(DCCG_AUDIO_DTO0_MODULE, clock); in dce3_2_audio_set_dto()
159 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ in dce3_2_audio_set_dto()
163 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl); in dce3_2_audio_set_dto()
164 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); in dce3_2_audio_set_dto()
165 WREG32(DCCG_AUDIO_DTO1_MODULE, clock); in dce3_2_audio_set_dto()
166 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ in dce3_2_audio_set_dto()
176 WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset, in dce3_2_hdmi_update_acr()
207 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, in dce3_2_set_audio_packet()
[all …]
Ddce6_afmt.c39 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce6_endpoint_rreg()
53 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce6_endpoint_wreg()
55 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, in dce6_endpoint_wreg()
57 WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); in dce6_endpoint_wreg()
100 WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, in dce6_afmt_select_pin()
258 WREG32(DCCG_AUDIO_DTO_SOURCE, value); in dce6_hdmi_audio_set_dto()
264 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000); in dce6_hdmi_audio_set_dto()
265 WREG32(DCCG_AUDIO_DTO0_MODULE, clock); in dce6_hdmi_audio_set_dto()
278 WREG32(DCCG_AUDIO_DTO_SOURCE, value); in dce6_dp_audio_set_dto()
293 WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); in dce6_dp_audio_set_dto()
[all …]
Dr600_dma.c89 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); in r600_dma_set_wptr()
107 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
127 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); in r600_dma_resume()
128 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); in r600_dma_resume()
136 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
139 WREG32(DMA_RB_RPTR, 0); in r600_dma_resume()
140 WREG32(DMA_RB_WPTR, 0); in r600_dma_resume()
143 WREG32(DMA_RB_RPTR_ADDR_HI, in r600_dma_resume()
145 WREG32(DMA_RB_RPTR_ADDR_LO, in r600_dma_resume()
151 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); in r600_dma_resume()
[all …]
Dni_dma.c111 WREG32(reg, (ring->wptr << 2) & 0x3fffc); in cayman_dma_set_wptr()
168 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
173 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
206 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
207 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
215 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
218 WREG32(DMA_RB_RPTR + reg_offset, 0); in cayman_dma_resume()
219 WREG32(DMA_RB_WPTR + reg_offset, 0); in cayman_dma_resume()
222 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, in cayman_dma_resume()
224 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, in cayman_dma_resume()
[all …]
Dr100.c164 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
176 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
359 WREG32(voltage->gpio.reg, tmp); in r100_pm_misc()
368 WREG32(voltage->gpio.reg, tmp); in r100_pm_misc()
457 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); in r100_pm_prepare()
461 WREG32(RADEON_CRTC_GEN_CNTL, tmp); in r100_pm_prepare()
488 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); in r100_pm_finish()
492 WREG32(RADEON_CRTC_GEN_CNTL, tmp); in r100_pm_finish()
564 WREG32(RADEON_FP_GEN_CNTL, tmp); in r100_hpd_set_polarity()
572 WREG32(RADEON_FP2_GEN_CNTL, tmp); in r100_hpd_set_polarity()
[all …]
Dradeon_legacy_crtc.c40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
199 WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); in radeon_legacy_rmx_mode_set()
200 WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); in radeon_legacy_rmx_mode_set()
201 WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); in radeon_legacy_rmx_mode_set()
202 WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); in radeon_legacy_rmx_mode_set()
203 WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); in radeon_legacy_rmx_mode_set()
204 WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); in radeon_legacy_rmx_mode_set()
205 WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); in radeon_legacy_rmx_mode_set()
[all …]
Dr600_hdmi.c168 WREG32(AZ_HOT_PLUG_CONTROL, tmp); in r600_audio_enable()
222 WREG32(HDMI0_AVI_INFO0 + offset, in r600_set_avi_packet()
224 WREG32(HDMI0_AVI_INFO1 + offset, in r600_set_avi_packet()
226 WREG32(HDMI0_AVI_INFO2 + offset, in r600_set_avi_packet()
228 WREG32(HDMI0_AVI_INFO3 + offset, in r600_set_avi_packet()
253 WREG32(HDMI0_AUDIO_INFO0 + offset, in r600_hdmi_update_audio_infoframe()
255 WREG32(HDMI0_AUDIO_INFO1 + offset, in r600_hdmi_update_audio_infoframe()
330 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100); in r600_hdmi_audio_set_dto()
331 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); in r600_hdmi_audio_set_dto()
332 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ in r600_hdmi_audio_set_dto()
[all …]
Datombios_crtc.c235 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); in atombios_blank_crtc()
244 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); in atombios_blank_crtc()
399 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); in atombios_disable_ss()
404 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); in atombios_disable_ss()
415 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); in atombios_disable_ss()
420 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); in atombios_disable_ss()
1354 WREG32(AVIVO_D1VGA_CONTROL, 0); in dce4_crtc_do_set_base()
1357 WREG32(AVIVO_D2VGA_CONTROL, 0); in dce4_crtc_do_set_base()
1360 WREG32(EVERGREEN_D3VGA_CONTROL, 0); in dce4_crtc_do_set_base()
1363 WREG32(EVERGREEN_D4VGA_CONTROL, 0); in dce4_crtc_do_set_base()
[all …]
Dkv_smc.c35 WREG32(SMC_MESSAGE_0, id & SMC_MSG_MASK); in kv_notify_message_to_smu()
70 WREG32(SMC_MSG_ARG_0, parameter); in kv_send_msg_to_smc_with_parameter()
83 WREG32(SMC_IND_INDEX_0, smc_address); in kv_set_smc_sram_address()
165 WREG32(SMC_IND_DATA_0, data); in kv_copy_bytes_to_smc()
178 WREG32(SMC_IND_DATA_0, data); in kv_copy_bytes_to_smc()
211 WREG32(SMC_IND_DATA_0, data); in kv_copy_bytes_to_smc()
Dradeon_display.c48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); in avivo_crtc_load_lut()
59 WREG32(AVIVO_DC_LUT_RW_MODE, 0); in avivo_crtc_load_lut()
60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); in avivo_crtc_load_lut()
[all …]
Drs780_dpm.c278 WREG32(FVTHROT_PWM_CTRL_REG1, in rs780_voltage_scaling_init()
282 WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT); in rs780_voltage_scaling_init()
283 WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT); in rs780_voltage_scaling_init()
284 WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT); in rs780_voltage_scaling_init()
285 WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT); in rs780_voltage_scaling_init()
291 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2, in rs780_voltage_scaling_init()
295 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3, in rs780_voltage_scaling_init()
298 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4, in rs780_voltage_scaling_init()
323 WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT); in rs780_set_engine_clock_wfc()
324 WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT); in rs780_set_engine_clock_wfc()
[all …]
Dci_smc.c41 WREG32(SMC_IND_INDEX_0, smc_address); in ci_set_smc_sram_address()
73 WREG32(SMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
105 WREG32(SMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
174 WREG32(SMC_MESSAGE_0, msg); in ci_send_msg_to_smc()
250 WREG32(SMC_IND_INDEX_0, ucode_start_address); in ci_load_smc_ucode()
256 WREG32(SMC_IND_DATA_0, data); in ci_load_smc_ucode()
291 WREG32(SMC_IND_DATA_0, value); in ci_write_smc_sram_dword()
Dsi_smc.c41 WREG32(SMC_IND_INDEX_0, smc_address); in si_set_smc_sram_address()
71 WREG32(SMC_IND_DATA_0, data); in si_copy_bytes_to_smc()
104 WREG32(SMC_IND_DATA_0, data); in si_copy_bytes_to_smc()
180 WREG32(SMC_MESSAGE_0, msg); in si_send_msg_to_smc()
265 WREG32(SMC_IND_INDEX_0, ucode_start_address); in si_load_smc_ucode()
271 WREG32(SMC_IND_DATA_0, data); in si_load_smc_ucode()
306 WREG32(SMC_IND_DATA_0, value); in si_write_smc_sram_dword()
Drs400.c146 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); in rs400_gart_enable()
147 WREG32(RS480_AGP_BASE_2, 0); in rs400_gart_enable()
154 WREG32(RADEON_BUS_CNTL, tmp); in rs400_gart_enable()
156 WREG32(RADEON_MC_AGP_LOCATION, tmp); in rs400_gart_enable()
158 WREG32(RADEON_BUS_CNTL, tmp); in rs400_gart_enable()
286 WREG32(RS480_NB_MC_INDEX, reg & 0xff); in rs400_mc_rreg()
288 WREG32(RS480_NB_MC_INDEX, 0xff); in rs400_mc_rreg()
298 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); in rs400_mc_wreg()
299 WREG32(RS480_NB_MC_DATA, (v)); in rs400_mc_wreg()
300 WREG32(RS480_NB_MC_INDEX, 0xff); in rs400_mc_wreg()
[all …]
Drv730_dpm.c409 WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate); in rv730_program_memory_timing_parameters()
422 WREG32(MC_ARB_DRAM_TIMING_3, dram_timing); in rv730_program_memory_timing_parameters()
423 WREG32(MC_ARB_DRAM_TIMING2_3, dram_timing2); in rv730_program_memory_timing_parameters()
432 WREG32(MC_ARB_DRAM_TIMING_2, dram_timing); in rv730_program_memory_timing_parameters()
433 WREG32(MC_ARB_DRAM_TIMING2_2, dram_timing2); in rv730_program_memory_timing_parameters()
442 WREG32(MC_ARB_DRAM_TIMING_1, dram_timing); in rv730_program_memory_timing_parameters()
443 WREG32(MC_ARB_DRAM_TIMING2_1, dram_timing2); in rv730_program_memory_timing_parameters()
446 WREG32(MC_ARB_DRAM_TIMING, old_dram_timing); in rv730_program_memory_timing_parameters()
447 WREG32(MC_ARB_DRAM_TIMING2, old_dram_timing2); in rv730_program_memory_timing_parameters()
485 WREG32(MC4_IO_DQ_PAD_CNTL_D0_I0, mc4_io_pad_cntl); in rv730_program_dcodt()
[all …]
Dtrinity_smc.c35 WREG32(SMC_MESSAGE_0, id); in trinity_notify_message_to_smu()
116 WREG32(SMC_INT_REQ, 1); in trinity_acquire_mutex()
126 WREG32(SMC_INT_REQ, 0); in trinity_release_mutex()
Dsumo_dpm.c113 WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); in sumo_mg_clockgating_enable()
114 WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); in sumo_mg_clockgating_enable()
116 …WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); in sumo_mg_clockgating_enable()
117 …WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); in sumo_mg_clockgating_enable()
140 WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u)); in sumo_program_grsd()
171 WREG32(CG_SCRATCH2, 0x01B60A17); in sumo_gfx_powergating_initialize()
338 WREG32(CG_BSP_0, pi->psp); in sumo_init_bsp()
356 WREG32(CG_BSP_0 + (i * 4), pi->dsp); in sumo_program_bsp()
358 WREG32(CG_BSP_0 + (i * 4), pi->psp); in sumo_program_bsp()
361 WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp); in sumo_program_bsp()
[all …]
Dr420.c91 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | in r420_pipes_init()
126 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); in r420_pipes_init()
129 WREG32(R300_GB_TILE_CONFIG, tmp); in r420_pipes_init()
136 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); in r420_pipes_init()
138 WREG32(R300_RB2D_DSTCACHE_MODE, in r420_pipes_init()
167 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); in r420_mc_rreg()
178 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | in r420_mc_wreg()
180 WREG32(R_0001FC_MC_IND_DATA, v); in r420_mc_wreg()
Dr300.c362 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); in r300_gpu_init()
370 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); in r300_gpu_init()
372 WREG32(R300_RB2D_DSTCACHE_MODE, in r300_gpu_init()
402 WREG32(RADEON_CP_CSQ_CNTL, 0); in r300_asic_reset()
404 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in r300_asic_reset()
405 WREG32(RADEON_CP_RB_RPTR_WR, 0); in r300_asic_reset()
406 WREG32(RADEON_CP_RB_WPTR, 0); in r300_asic_reset()
407 WREG32(RADEON_CP_RB_CNTL, tmp); in r300_asic_reset()
412 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | in r300_asic_reset()
416 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); in r300_asic_reset()
[all …]
Drv770_smc.c290 WREG32(SMC_SRAM_ADDR, addr); in rv770_set_smc_sram_address()
320 WREG32(SMC_SRAM_DATA, data); in rv770_copy_bytes_to_smc()
353 WREG32(SMC_SRAM_DATA, data); in rv770_copy_bytes_to_smc()
386 WREG32(SMC_ISR_FFD8_FFDB + i, tmp); in rv770_program_interrupt_vectors()
475 WREG32(SMC_SRAM_DATA, 0); in rv770_clear_smc_sram()
627 WREG32(SMC_SRAM_DATA, value); in rv770_write_smc_sram_dword()
Drs690.c245 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); in rs690_line_buffer_adjust()
611 WREG32(R_006C9C_DCP_CONTROL, 0); in rs690_bandwidth_update()
613 WREG32(R_006C9C_DCP_CONTROL, 2); in rs690_bandwidth_update()
623 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); in rs690_bandwidth_update()
634 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); in rs690_bandwidth_update()
635 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt); in rs690_bandwidth_update()
636 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); in rs690_bandwidth_update()
637 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt); in rs690_bandwidth_update()
646 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); in rs690_mc_rreg()
648 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); in rs690_mc_rreg()
[all …]
Dcypress_dpm.c62 WREG32(CG_BIF_REQ_AND_RSP, bif); in cypress_enable_bif_dynamic_pcie_gen2()
126 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
153 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
187 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
195 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); in cypress_mg_clock_gating_enable()
208 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
216 WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0); in cypress_mg_clock_gating_enable()
944 WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time); in cypress_program_memory_timing_parameters()
1132 WREG32(MC_CONFIG_MCD, 0xf); in cypress_force_mc_use_s1()
1133 WREG32(MC_CG_CONFIG_MCD, 0xf); in cypress_force_mc_use_s1()
[all …]
Dbtc_dpm.c1346 WREG32(CG_BIF_REQ_AND_RSP, bif); in btc_enable_bif_dynamic_pcie_gen2()
1365 WREG32(CG_BIF_REQ_AND_RSP, bif); in btc_enable_bif_dynamic_pcie_gen2()
1418 WREG32(CG_ULV_CONTROL, BTC_CGULVCONTROL_DFLT); in btc_populate_ulv_state()
1419 WREG32(CG_ULV_PARAMETER, BTC_CGULVPARAMETER_DFLT); in btc_populate_ulv_state()
1450 WREG32(sequence[i], tmp); in btc_program_mgcg_hw_sequence()
1771 WREG32(MC_ARB_DRAM_TIMING, arb_registers->mc_arb_dram_timing); in btc_set_arb0_registers()
1772 WREG32(MC_ARB_DRAM_TIMING2, arb_registers->mc_arb_dram_timing2); in btc_set_arb0_registers()
2030 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); in btc_initialize_mc_reg_table()
2031 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); in btc_initialize_mc_reg_table()
2032 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in btc_initialize_mc_reg_table()
[all …]
Dr520.c79 WREG32(0x4128, 0xFF); in r520_gpu_init()
145 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); in r520_mc_program()
150 WREG32(R_000134_HDP_FB_LOCATION, in r520_mc_program()
Dr600_dpm.c248 WREG32(CG_RLC_REQ_AND_RSP, 0x2); in r600_gfx_clockgating_enable()
256 WREG32(CG_RLC_REQ_AND_RSP, 0x0); in r600_gfx_clockgating_enable()
258 WREG32(GRBM_PWR_CNTL, 0x1); in r600_gfx_clockgating_enable()
337 WREG32(CG_BSP, BSP(p) | BSU(u)); in r600_set_bsp()
344 WREG32(CG_RT, FLS(l_to_m) | FMS(m_to_h)); in r600_set_at()
345 WREG32(CG_LT, FHS(h_to_m) | FMS(m_to_l)); in r600_set_at()
351 WREG32(CG_FFCT_0 + (index * 4), UTC_0(u_t) | DTC_0(d_t)); in r600_set_tc()
369 WREG32(CG_FTV, vrv); in r600_set_vrc()
521 WREG32(LOWER_GPIO_ENABLE, mask & 0xffffffff); in r600_voltage_control_enable_pins()
522 WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask)); in r600_voltage_control_enable_pins()
[all …]
Dradeon.h2542 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) macro
2573 WREG32(reg, tmp_); \
2600 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); in rv370_pcie_rreg()
2611 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); in rv370_pcie_wreg()
2612 WREG32(RADEON_PCIE_DATA, (v)); in rv370_pcie_wreg()
2622 WREG32(TN_SMC_IND_INDEX_0, (reg)); in tn_smc_rreg()
2633 WREG32(TN_SMC_IND_INDEX_0, (reg)); in tn_smc_wreg()
2634 WREG32(TN_SMC_IND_DATA_0, (v)); in tn_smc_wreg()
2644 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_rreg()
2655 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); in r600_rcu_wreg()
[all …]
Dsumo_smc.c48 WREG32(GFX_INT_REQ, gfx_int_req); in sumo_send_msg_to_smu()
69 WREG32(GFX_INT_REQ, gfx_int_req); in sumo_send_msg_to_smu()
Dradeon_combios.c2909 WREG32(reg, val); in radeon_combios_external_tmds_setup()
2919 WREG32(reg, val); in radeon_combios_external_tmds_setup()
2963 WREG32(reg, val); in radeon_combios_external_tmds_setup()
2973 WREG32(reg, val); in radeon_combios_external_tmds_setup()
3026 WREG32(addr, val); in combios_parse_mmio_table()
3031 WREG32(addr, val); in combios_parse_mmio_table()
3041 WREG32(addr, tmp); in combios_parse_mmio_table()
3051 WREG32(addr, tmp); in combios_parse_mmio_table()
3213 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); in combios_parse_ram_reset_table()
3219 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); in combios_parse_ram_reset_table()
[all …]
Dni_dpm.c1039 WREG32(SMC_SCRATCH0, parameter); in ni_send_msg_to_smc_with_parameter()
1539 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); in ni_copy_and_switch_arb_sets()
1540 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); in ni_copy_and_switch_arb_sets()
1544 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); in ni_copy_and_switch_arb_sets()
1545 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); in ni_copy_and_switch_arb_sets()
1549 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); in ni_copy_and_switch_arb_sets()
1550 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); in ni_copy_and_switch_arb_sets()
1554 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); in ni_copy_and_switch_arb_sets()
1555 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); in ni_copy_and_switch_arb_sets()
1563 WREG32(MC_CG_CONFIG, mc_cg_config); in ni_copy_and_switch_arb_sets()
[all …]
Dsi_dpm.c2670 WREG32(CG_CAC_CTRL, reg); in si_initialize_smc_cac_tables()
2765 WREG32(config_regs->offset << 2, data); in si_program_cac_config_registers()
3154 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); in si_is_special_1gb_platform()
3326 WREG32(SMC_SCRATCH0, parameter); in si_send_msg_to_smc_with_parameter()
3544 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3555 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3636 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in si_program_display_gap()
3655 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); in si_program_display_gap()
3699 WREG32(CG_BSP, pi->dsp); in si_setup_bsp()
3713 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); in si_program_tp()
[all …]
Drv770_dpm.c156 WREG32(CG_CGTT_LOCAL_0, mgcg_cgtt_local0); in rv770_mg_clock_gating_enable()
157 WREG32(CG_CGTT_LOCAL_1, (RV770_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF)); in rv770_mg_clock_gating_enable()
160 WREG32(CGTS_SM_CTRL_REG, RV770_MGCGCGTSSMCTRL_DFLT); in rv770_mg_clock_gating_enable()
162 WREG32(CG_CGTT_LOCAL_0, 0xFFFFFFFF); in rv770_mg_clock_gating_enable()
163 WREG32(CG_CGTT_LOCAL_1, 0xFFFFCFFF); in rv770_mg_clock_gating_enable()
761 WREG32(MC_ARB_SQM_RATIO, sqm_ratio); in rv770_program_memory_timing_parameters()
768 WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate); in rv770_program_memory_timing_parameters()
810 WREG32(MPLL_TIME, in rv770_program_mpll_timing_parameters()
836 WREG32(CG_BSP, pi->dsp); in rv770_setup_bsp()
851 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); in rv770_program_tp()
[all …]
Datombios_encoders.c69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); in radeon_atom_set_backlight_level_to_reg()
71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); in radeon_atom_set_backlight_level_to_reg()
1554 WREG32(reg, (ATOM_S3_TV1_ACTIVE | in atombios_yuv_setup()
1557 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); in atombios_yuv_setup()
1559 WREG32(reg, 0); in atombios_yuv_setup()
1567 WREG32(reg, temp); in atombios_yuv_setup()
1628 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); in radeon_atom_encoder_dpms_avivo()
1630 WREG32(RADEON_BIOS_3_SCRATCH, reg); in radeon_atom_encoder_dpms_avivo()
2071 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); in atombios_apply_encoder_quirks()
2080 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, in atombios_apply_encoder_quirks()
[all …]
Dradeon_dp_mst.c48 WREG32(NI_DIG_BE_CNTL + primary->offset, reg); in radeon_dp_mst_set_be_cntl()
87 WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp); in radeon_dp_mst_set_stream_attrib()
89 WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1); in radeon_dp_mst_set_stream_attrib()
164 WREG32(NI_DP_MSE_RATE_CNTL + offset, val); in radeon_dp_mst_set_vcp_size()
Dci_dpm.c603 WREG32(config_regs->offset << 2, data); in ci_program_pt_config_registers()
1651 WREG32(SMC_MSG_ARG_0, parameter); in ci_send_msg_to_smc_with_parameter()
1899 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1910 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4581 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3); in ci_register_patching_mc_seq()
4584 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3); in ci_register_patching_mc_seq()
4585 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp); in ci_register_patching_mc_seq()
4603 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); in ci_initialize_mc_reg_table()
4604 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); in ci_initialize_mc_reg_table()
4605 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY)); in ci_initialize_mc_reg_table()
[all …]
Dradeon_atombios.c4087 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); in radeon_atom_initialize_bios_scratch_regs()
4088 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); in radeon_atom_initialize_bios_scratch_regs()
4090 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); in radeon_atom_initialize_bios_scratch_regs()
4091 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); in radeon_atom_initialize_bios_scratch_regs()
4121 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); in radeon_restore_bios_scratch_regs()
4144 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); in radeon_atom_output_lock()
4146 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); in radeon_atom_output_lock()
4326 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); in radeon_atombios_connected_scratch_regs()
4327 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); in radeon_atombios_connected_scratch_regs()
4328 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); in radeon_atombios_connected_scratch_regs()
[all …]
Dradeon_agp.c250 WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000); in radeon_agp_init()
Dtrinity_dpm.c385 WREG32(CG_PG_CTRL, SP(p) | SU(u)); in trinity_gfx_powergating_initialize()
415 WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_ENABLE); in trinity_mg_clockgating_enable()
417 WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_DISABLE); in trinity_mg_clockgating_enable()
468 WREG32(seq[i], seq[i+1]); in trinity_program_override_mgpg_sequences()
939 WREG32(CG_MISC_REG, tmp); in trinity_setup_uvd_clocks()
Dradeon_device.c196 WREG32(reg, tmp); in radeon_program_register_sequence()
225 WREG32(RADEON_SURFACE_CNTL, 0); in radeon_surface_init()
890 WREG32(reg*4, val); in cail_reg_write()
Drv6xx_dpm.c815 WREG32(SQM_RATIO, sqm_ratio); in rv6xx_program_memory_timing_parameters()
826 WREG32(ARB_RFSH_RATE, arb_refresh_rate); in rv6xx_program_memory_timing_parameters()
990 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in rv6xx_enable_display_gap()
1196 WREG32(CG_DISPLAY_GAP_CNTL, tmp); in rv6xx_program_display_gap()
Dradeon_ttm.c1070 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); in radeon_ttm_vram_read()
1072 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); in radeon_ttm_vram_read()
Dradeon_fence.c70 WREG32(drv->scratch_reg, seq); in radeon_fence_write()
Dradeon_audio.c125 WREG32(reg, v); in radeon_audio_wreg()
Dkv_dpm.c321 WREG32(config_regs->offset << 2, data); in kv_program_pt_config_registers()
/linux-4.1.27/drivers/gpu/drm/cirrus/
Dcirrus_drv.h41 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)cdev->rmmio) + (reg)) macro
/linux-4.1.27/drivers/gpu/drm/mgag200/
Dmgag200_drv.h47 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg)) macro
Dmgag200_mode.c1024 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000); in mga_crtc_mode_set()
1026 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000); in mga_crtc_mode_set()