Lines Matching refs:WREG32
362 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); in r300_gpu_init()
370 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); in r300_gpu_init()
372 WREG32(R300_RB2D_DSTCACHE_MODE, in r300_gpu_init()
402 WREG32(RADEON_CP_CSQ_CNTL, 0); in r300_asic_reset()
404 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in r300_asic_reset()
405 WREG32(RADEON_CP_RB_RPTR_WR, 0); in r300_asic_reset()
406 WREG32(RADEON_CP_RB_WPTR, 0); in r300_asic_reset()
407 WREG32(RADEON_CP_RB_CNTL, tmp); in r300_asic_reset()
412 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | in r300_asic_reset()
416 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); in r300_asic_reset()
425 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); in r300_asic_reset()
428 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); in r300_asic_reset()
1315 WREG32(R_00014C_MC_AGP_LOCATION, in r300_mc_program()
1318 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); in r300_mc_program()
1319 WREG32(R_00015C_AGP_BASE_2, in r300_mc_program()
1322 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); in r300_mc_program()
1323 WREG32(R_000170_AGP_BASE, 0); in r300_mc_program()
1324 WREG32(R_00015C_AGP_BASE_2, 0); in r300_mc_program()
1330 WREG32(R_000148_MC_FB_LOCATION, in r300_mc_program()