1346 				WREG32(CG_BIF_REQ_AND_RSP, bif);  in btc_enable_bif_dynamic_pcie_gen2()
1365 				WREG32(CG_BIF_REQ_AND_RSP, bif);  in btc_enable_bif_dynamic_pcie_gen2()
1418 			WREG32(CG_ULV_CONTROL, BTC_CGULVCONTROL_DFLT);  in btc_populate_ulv_state()
1419 			WREG32(CG_ULV_PARAMETER, BTC_CGULVPARAMETER_DFLT);  in btc_populate_ulv_state()
1450 		WREG32(sequence[i], tmp);  in btc_program_mgcg_hw_sequence()
1771 	WREG32(MC_ARB_DRAM_TIMING,  arb_registers->mc_arb_dram_timing);  in btc_set_arb0_registers()
1772 	WREG32(MC_ARB_DRAM_TIMING2, arb_registers->mc_arb_dram_timing2);  in btc_set_arb0_registers()
2030 	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));  in btc_initialize_mc_reg_table()
2031 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));  in btc_initialize_mc_reg_table()
2032 	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));  in btc_initialize_mc_reg_table()
2033 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));  in btc_initialize_mc_reg_table()
2034 	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));  in btc_initialize_mc_reg_table()
2035 	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));  in btc_initialize_mc_reg_table()
2036 	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));  in btc_initialize_mc_reg_table()
2037 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));  in btc_initialize_mc_reg_table()
2038 	WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));  in btc_initialize_mc_reg_table()
2039 	WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));  in btc_initialize_mc_reg_table()
2040 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));  in btc_initialize_mc_reg_table()
2076 				WREG32(MC_PMG_AUTO_CFG, tmp);  in btc_init_stutter_mode()