40 	WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);  in radeon_overscan_setup()
41 	WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);  in radeon_overscan_setup()
42 	WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);  in radeon_overscan_setup()
199 	WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);  in radeon_legacy_rmx_mode_set()
200 	WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);  in radeon_legacy_rmx_mode_set()
201 	WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);  in radeon_legacy_rmx_mode_set()
202 	WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);  in radeon_legacy_rmx_mode_set()
203 	WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);  in radeon_legacy_rmx_mode_set()
204 	WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);  in radeon_legacy_rmx_mode_set()
205 	WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);  in radeon_legacy_rmx_mode_set()
206 	WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);  in radeon_legacy_rmx_mode_set()
542 	WREG32(gen_cntl_reg, gen_cntl_val);  in radeon_crtc_do_set_base()
546 	WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);  in radeon_crtc_do_set_base()
550 			WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);  in radeon_crtc_do_set_base()
552 			WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);  in radeon_crtc_do_set_base()
554 	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);  in radeon_crtc_do_set_base()
555 	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);  in radeon_crtc_do_set_base()
556 	WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);  in radeon_crtc_do_set_base()
678 		WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);  in radeon_set_crtc_timing()
679 		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);  in radeon_set_crtc_timing()
681 		WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);  in radeon_set_crtc_timing()
682 		WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);  in radeon_set_crtc_timing()
715 		WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);  in radeon_set_crtc_timing()
716 		WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);  in radeon_set_crtc_timing()
717 		WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);  in radeon_set_crtc_timing()
725 	WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);  in radeon_set_crtc_timing()
726 	WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);  in radeon_set_crtc_timing()
727 	WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);  in radeon_set_crtc_timing()
728 	WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);  in radeon_set_crtc_timing()