48 	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
50 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
51 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
52 	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);  in avivo_crtc_load_lut()
54 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);  in avivo_crtc_load_lut()
55 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);  in avivo_crtc_load_lut()
56 	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);  in avivo_crtc_load_lut()
58 	WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);  in avivo_crtc_load_lut()
59 	WREG32(AVIVO_DC_LUT_RW_MODE, 0);  in avivo_crtc_load_lut()
60 	WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);  in avivo_crtc_load_lut()
64 		WREG32(AVIVO_DC_LUT_30_COLOR,  in avivo_crtc_load_lut()
82 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
84 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
85 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
86 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
88 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);  in dce4_crtc_load_lut()
89 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);  in dce4_crtc_load_lut()
90 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);  in dce4_crtc_load_lut()
92 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
93 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);  in dce4_crtc_load_lut()
95 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);  in dce4_crtc_load_lut()
97 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,  in dce4_crtc_load_lut()
113 	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
116 	WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
118 	WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
120 	WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
124 	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
126 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
127 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
128 	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
130 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);  in dce5_crtc_load_lut()
131 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);  in dce5_crtc_load_lut()
132 	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);  in dce5_crtc_load_lut()
134 	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
135 	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);  in dce5_crtc_load_lut()
137 	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
139 		WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
145 	WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
150 	WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
153 	WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
156 	WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
160 	WREG32(0x6940 + radeon_crtc->crtc_offset, 0);  in dce5_crtc_load_lut()
165 		WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,  in dce5_crtc_load_lut()
183 	WREG32(RADEON_DAC_CNTL2, dac2_cntl);  in legacy_crtc_load_lut()
187 		WREG32(RADEON_PALETTE_30_DATA,  in legacy_crtc_load_lut()