2542 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)  macro
2573 		WREG32(reg, tmp_);				\
2600 	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));  in rv370_pcie_rreg()
2611 	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));  in rv370_pcie_wreg()
2612 	WREG32(RADEON_PCIE_DATA, (v));  in rv370_pcie_wreg()
2622 	WREG32(TN_SMC_IND_INDEX_0, (reg));  in tn_smc_rreg()
2633 	WREG32(TN_SMC_IND_INDEX_0, (reg));  in tn_smc_wreg()
2634 	WREG32(TN_SMC_IND_DATA_0, (v));  in tn_smc_wreg()
2644 	WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));  in r600_rcu_rreg()
2655 	WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));  in r600_rcu_wreg()
2656 	WREG32(R600_RCU_DATA, (v));  in r600_rcu_wreg()
2666 	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));  in eg_cg_rreg()
2677 	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));  in eg_cg_wreg()
2678 	WREG32(EVERGREEN_CG_IND_DATA, (v));  in eg_cg_wreg()
2688 	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));  in eg_pif_phy0_rreg()
2699 	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));  in eg_pif_phy0_wreg()
2700 	WREG32(EVERGREEN_PIF_PHY0_DATA, (v));  in eg_pif_phy0_wreg()
2710 	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));  in eg_pif_phy1_rreg()
2721 	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));  in eg_pif_phy1_wreg()
2722 	WREG32(EVERGREEN_PIF_PHY1_DATA, (v));  in eg_pif_phy1_wreg()
2732 	WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));  in r600_uvd_ctx_rreg()
2743 	WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));  in r600_uvd_ctx_wreg()
2744 	WREG32(R600_UVD_CTX_DATA, (v));  in r600_uvd_ctx_wreg()
2755 	WREG32(CIK_DIDT_IND_INDEX, (reg));  in cik_didt_rreg()
2766 	WREG32(CIK_DIDT_IND_INDEX, (reg));  in cik_didt_wreg()
2767 	WREG32(CIK_DIDT_IND_DATA, (v));  in cik_didt_wreg()