Lines Matching refs:WREG32
1110 WREG32(CG_SCRATCH1, cg_scratch); in sumo_set_uvd_clocks()
1271 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
1352 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in evergreen_page_flip()
1355 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1357 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip()
1360 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1362 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip()
1375 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in evergreen_page_flip()
1628 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_prepare()
1653 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_finish()
1724 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1732 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1740 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1748 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1756 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1764 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1801 WREG32(DC_HPD1_CONTROL, tmp); in evergreen_hpd_init()
1804 WREG32(DC_HPD2_CONTROL, tmp); in evergreen_hpd_init()
1807 WREG32(DC_HPD3_CONTROL, tmp); in evergreen_hpd_init()
1810 WREG32(DC_HPD4_CONTROL, tmp); in evergreen_hpd_init()
1813 WREG32(DC_HPD5_CONTROL, tmp); in evergreen_hpd_init()
1816 WREG32(DC_HPD6_CONTROL, tmp); in evergreen_hpd_init()
1845 WREG32(DC_HPD1_CONTROL, 0); in evergreen_hpd_fini()
1848 WREG32(DC_HPD2_CONTROL, 0); in evergreen_hpd_fini()
1851 WREG32(DC_HPD3_CONTROL, 0); in evergreen_hpd_fini()
1854 WREG32(DC_HPD4_CONTROL, 0); in evergreen_hpd_fini()
1857 WREG32(DC_HPD5_CONTROL, 0); in evergreen_hpd_fini()
1860 WREG32(DC_HPD6_CONTROL, 0); in evergreen_hpd_fini()
1916 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); in evergreen_line_buffer_adjust()
1919 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in evergreen_line_buffer_adjust()
2337 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2338 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
2345 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2346 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
2350 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); in evergreen_program_watermarks()
2353 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in evergreen_program_watermarks()
2354 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); in evergreen_program_watermarks()
2428 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in evergreen_pcie_gart_tlb_flush()
2430 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); in evergreen_pcie_gart_tlb_flush()
2459 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2462 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_enable()
2463 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_enable()
2470 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2471 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2472 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2474 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2475 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2476 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2481 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_enable()
2483 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2484 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2485 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2486 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_enable()
2487 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in evergreen_pcie_gart_enable()
2488 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in evergreen_pcie_gart_enable()
2489 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in evergreen_pcie_gart_enable()
2490 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in evergreen_pcie_gart_enable()
2492 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in evergreen_pcie_gart_enable()
2494 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_enable()
2509 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_pcie_gart_disable()
2510 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_disable()
2513 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_disable()
2515 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_disable()
2516 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_disable()
2519 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_disable()
2520 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_disable()
2521 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_disable()
2522 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_disable()
2523 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_disable()
2524 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_disable()
2525 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_disable()
2542 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_agp_enable()
2545 WREG32(VM_L2_CNTL2, 0); in evergreen_agp_enable()
2546 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_agp_enable()
2552 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_agp_enable()
2553 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_agp_enable()
2554 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_agp_enable()
2555 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_agp_enable()
2556 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_agp_enable()
2557 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_agp_enable()
2558 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_agp_enable()
2559 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_agp_enable()
2560 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_agp_enable()
2684 WREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2700 WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl); in evergreen_blank_dp_output()
2715 WREG32(VGA_RENDER_CONTROL, 0); in evergreen_mc_stop()
2726 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2728 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2729 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
2735 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2737 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2738 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
2760 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2763 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2764 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
2777 WREG32(BIF_FB_EN, 0); in evergreen_mc_stop()
2780 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); in evergreen_mc_stop()
2791 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_stop()
2796 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in evergreen_mc_stop()
2809 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], in evergreen_mc_resume()
2811 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], in evergreen_mc_resume()
2813 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], in evergreen_mc_resume()
2815 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], in evergreen_mc_resume()
2820 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2821 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2831 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); in evergreen_mc_resume()
2836 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_resume()
2841 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in evergreen_mc_resume()
2855 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); in evergreen_mc_resume()
2857 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); in evergreen_mc_resume()
2864 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_resume()
2865 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_resume()
2866 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_resume()
2870 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_resume()
2871 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_resume()
2872 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_resume()
2885 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); in evergreen_mc_resume()
2887 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); in evergreen_mc_resume()
2899 WREG32((0x2c14 + j), 0x00000000); in evergreen_mc_program()
2900 WREG32((0x2c18 + j), 0x00000000); in evergreen_mc_program()
2901 WREG32((0x2c1c + j), 0x00000000); in evergreen_mc_program()
2902 WREG32((0x2c20 + j), 0x00000000); in evergreen_mc_program()
2903 WREG32((0x2c24 + j), 0x00000000); in evergreen_mc_program()
2905 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in evergreen_mc_program()
2912 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in evergreen_mc_program()
2917 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in evergreen_mc_program()
2919 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in evergreen_mc_program()
2923 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in evergreen_mc_program()
2925 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in evergreen_mc_program()
2929 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in evergreen_mc_program()
2931 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in evergreen_mc_program()
2934 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in evergreen_mc_program()
2942 WREG32(MC_FUS_VM_FB_OFFSET, tmp); in evergreen_mc_program()
2946 WREG32(MC_VM_FB_LOCATION, tmp); in evergreen_mc_program()
2947 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in evergreen_mc_program()
2948 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in evergreen_mc_program()
2949 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in evergreen_mc_program()
2951 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); in evergreen_mc_program()
2952 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); in evergreen_mc_program()
2953 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in evergreen_mc_program()
2955 WREG32(MC_VM_AGP_BASE, 0); in evergreen_mc_program()
2956 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in evergreen_mc_program()
2957 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in evergreen_mc_program()
3015 WREG32(CP_RB_CNTL, in evergreen_cp_load_microcode()
3022 WREG32(CP_PFP_UCODE_ADDR, 0); in evergreen_cp_load_microcode()
3024 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_cp_load_microcode()
3025 WREG32(CP_PFP_UCODE_ADDR, 0); in evergreen_cp_load_microcode()
3028 WREG32(CP_ME_RAM_WADDR, 0); in evergreen_cp_load_microcode()
3030 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in evergreen_cp_load_microcode()
3032 WREG32(CP_PFP_UCODE_ADDR, 0); in evergreen_cp_load_microcode()
3033 WREG32(CP_ME_RAM_WADDR, 0); in evergreen_cp_load_microcode()
3034 WREG32(CP_ME_RAM_RADDR, 0); in evergreen_cp_load_microcode()
3059 WREG32(CP_ME_CNTL, cp_me); in evergreen_cp_start()
3112 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | in evergreen_cp_resume()
3120 WREG32(GRBM_SOFT_RESET, 0); in evergreen_cp_resume()
3129 WREG32(CP_RB_CNTL, tmp); in evergreen_cp_resume()
3130 WREG32(CP_SEM_WAIT_TIMER, 0x0); in evergreen_cp_resume()
3131 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in evergreen_cp_resume()
3134 WREG32(CP_RB_WPTR_DELAY, 0); in evergreen_cp_resume()
3137 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); in evergreen_cp_resume()
3138 WREG32(CP_RB_RPTR_WR, 0); in evergreen_cp_resume()
3140 WREG32(CP_RB_WPTR, ring->wptr); in evergreen_cp_resume()
3143 WREG32(CP_RB_RPTR_ADDR, in evergreen_cp_resume()
3145 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in evergreen_cp_resume()
3146 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in evergreen_cp_resume()
3149 WREG32(SCRATCH_UMSK, 0xff); in evergreen_cp_resume()
3152 WREG32(SCRATCH_UMSK, 0); in evergreen_cp_resume()
3156 WREG32(CP_RB_CNTL, tmp); in evergreen_cp_resume()
3158 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in evergreen_cp_resume()
3159 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); in evergreen_cp_resume()
3428 WREG32((0x2c14 + j), 0x00000000); in evergreen_gpu_init()
3429 WREG32((0x2c18 + j), 0x00000000); in evergreen_gpu_init()
3430 WREG32((0x2c1c + j), 0x00000000); in evergreen_gpu_init()
3431 WREG32((0x2c20 + j), 0x00000000); in evergreen_gpu_init()
3432 WREG32((0x2c24 + j), 0x00000000); in evergreen_gpu_init()
3435 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in evergreen_gpu_init()
3436 WREG32(SRBM_INT_CNTL, 0x1); in evergreen_gpu_init()
3437 WREG32(SRBM_INT_ACK, 0x1); in evergreen_gpu_init()
3506 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3507 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3527 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3528 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3536 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
3537 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
3539 WREG32(GB_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3540 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3541 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3542 WREG32(DMA_TILING_CONFIG, gb_addr_config); in evergreen_gpu_init()
3543 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3544 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3545 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3561 WREG32(GB_BACKEND_MAP, tmp); in evergreen_gpu_init()
3563 WREG32(CGTS_SYS_TCC_DISABLE, 0); in evergreen_gpu_init()
3564 WREG32(CGTS_TCC_DISABLE, 0); in evergreen_gpu_init()
3565 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); in evergreen_gpu_init()
3566 WREG32(CGTS_USER_TCC_DISABLE, 0); in evergreen_gpu_init()
3569 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | in evergreen_gpu_init()
3572 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); in evergreen_gpu_init()
3574 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | in evergreen_gpu_init()
3581 WREG32(SX_DEBUG_1, sx_debug_1); in evergreen_gpu_init()
3587 WREG32(SMX_DC_CTL0, smx_dc_ctl0); in evergreen_gpu_init()
3590 WREG32(SMX_SAR_CTL0, 0x00010000); in evergreen_gpu_init()
3592 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) … in evergreen_gpu_init()
3596 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | in evergreen_gpu_init()
3600 WREG32(VGT_NUM_INSTANCES, 1); in evergreen_gpu_init()
3601 WREG32(SPI_CONFIG_CNTL, 0); in evergreen_gpu_init()
3602 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in evergreen_gpu_init()
3603 WREG32(CP_PERFMON_CNTL, 0); in evergreen_gpu_init()
3605 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | in evergreen_gpu_init()
3671 WREG32(SQ_CONFIG, sq_config); in evergreen_gpu_init()
3672 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); in evergreen_gpu_init()
3673 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); in evergreen_gpu_init()
3674 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); in evergreen_gpu_init()
3675 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); in evergreen_gpu_init()
3676 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); in evergreen_gpu_init()
3677 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); in evergreen_gpu_init()
3678 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); in evergreen_gpu_init()
3679 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); in evergreen_gpu_init()
3680 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); in evergreen_gpu_init()
3681 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); in evergreen_gpu_init()
3683 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in evergreen_gpu_init()
3699 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); in evergreen_gpu_init()
3701 WREG32(VGT_GS_VERTEX_REUSE, 16); in evergreen_gpu_init()
3702 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0); in evergreen_gpu_init()
3703 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in evergreen_gpu_init()
3705 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); in evergreen_gpu_init()
3706 WREG32(VGT_OUT_DEALLOC_CNTL, 16); in evergreen_gpu_init()
3708 WREG32(CB_PERF_CTR0_SEL_0, 0); in evergreen_gpu_init()
3709 WREG32(CB_PERF_CTR0_SEL_1, 0); in evergreen_gpu_init()
3710 WREG32(CB_PERF_CTR1_SEL_0, 0); in evergreen_gpu_init()
3711 WREG32(CB_PERF_CTR1_SEL_1, 0); in evergreen_gpu_init()
3712 WREG32(CB_PERF_CTR2_SEL_0, 0); in evergreen_gpu_init()
3713 WREG32(CB_PERF_CTR2_SEL_1, 0); in evergreen_gpu_init()
3714 WREG32(CB_PERF_CTR3_SEL_0, 0); in evergreen_gpu_init()
3715 WREG32(CB_PERF_CTR3_SEL_1, 0); in evergreen_gpu_init()
3718 WREG32(CB_COLOR0_BASE, 0); in evergreen_gpu_init()
3719 WREG32(CB_COLOR1_BASE, 0); in evergreen_gpu_init()
3720 WREG32(CB_COLOR2_BASE, 0); in evergreen_gpu_init()
3721 WREG32(CB_COLOR3_BASE, 0); in evergreen_gpu_init()
3722 WREG32(CB_COLOR4_BASE, 0); in evergreen_gpu_init()
3723 WREG32(CB_COLOR5_BASE, 0); in evergreen_gpu_init()
3724 WREG32(CB_COLOR6_BASE, 0); in evergreen_gpu_init()
3725 WREG32(CB_COLOR7_BASE, 0); in evergreen_gpu_init()
3726 WREG32(CB_COLOR8_BASE, 0); in evergreen_gpu_init()
3727 WREG32(CB_COLOR9_BASE, 0); in evergreen_gpu_init()
3728 WREG32(CB_COLOR10_BASE, 0); in evergreen_gpu_init()
3729 WREG32(CB_COLOR11_BASE, 0); in evergreen_gpu_init()
3733 WREG32(i, 0); in evergreen_gpu_init()
3735 WREG32(i, 0); in evergreen_gpu_init()
3739 WREG32(HDP_MISC_CNTL, tmp); in evergreen_gpu_init()
3742 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in evergreen_gpu_init()
3744 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in evergreen_gpu_init()
3949 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_soft_reset()
3955 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_soft_reset()
4016 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4022 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4030 WREG32(SRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4036 WREG32(SRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4059 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_pci_config_reset()
4064 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_pci_config_reset()
4413 WREG32(RLC_CNTL, mask); in evergreen_rlc_start()
4426 WREG32(RLC_HB_CNTL, 0); in evergreen_rlc_resume()
4437 WREG32(TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK, always_on_bitmap); in evergreen_rlc_resume()
4438 WREG32(TN_RLC_LB_PARAMS, 0x00601004); in evergreen_rlc_resume()
4439 WREG32(TN_RLC_LB_INIT_SIMD_MASK, 0xffffffff); in evergreen_rlc_resume()
4440 WREG32(TN_RLC_LB_CNTR_INIT, 0x00000000); in evergreen_rlc_resume()
4441 WREG32(TN_RLC_LB_CNTR_MAX, 0x00002000); in evergreen_rlc_resume()
4444 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); in evergreen_rlc_resume()
4445 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); in evergreen_rlc_resume()
4447 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in evergreen_rlc_resume()
4448 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
4450 WREG32(RLC_HB_BASE, 0); in evergreen_rlc_resume()
4451 WREG32(RLC_HB_RPTR, 0); in evergreen_rlc_resume()
4452 WREG32(RLC_HB_WPTR, 0); in evergreen_rlc_resume()
4453 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); in evergreen_rlc_resume()
4454 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); in evergreen_rlc_resume()
4456 WREG32(RLC_MC_CNTL, 0); in evergreen_rlc_resume()
4457 WREG32(RLC_UCODE_CNTL, 0); in evergreen_rlc_resume()
4462 WREG32(RLC_UCODE_ADDR, i); in evergreen_rlc_resume()
4463 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_rlc_resume()
4467 WREG32(RLC_UCODE_ADDR, i); in evergreen_rlc_resume()
4468 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_rlc_resume()
4472 WREG32(RLC_UCODE_ADDR, i); in evergreen_rlc_resume()
4473 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_rlc_resume()
4476 WREG32(RLC_UCODE_ADDR, 0); in evergreen_rlc_resume()
4503 WREG32(CAYMAN_DMA1_CNTL, tmp); in evergreen_disable_interrupt_state()
4505 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in evergreen_disable_interrupt_state()
4507 WREG32(DMA_CNTL, tmp); in evergreen_disable_interrupt_state()
4508 WREG32(GRBM_INT_CNTL, 0); in evergreen_disable_interrupt_state()
4509 WREG32(SRBM_INT_CNTL, 0); in evergreen_disable_interrupt_state()
4510 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4511 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4513 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4514 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4517 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4518 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4521 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4522 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4524 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4525 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4528 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4529 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in evergreen_disable_interrupt_state()
4534 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); in evergreen_disable_interrupt_state()
4535 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); in evergreen_disable_interrupt_state()
4538 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4540 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4542 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4544 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4546 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4548 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4721 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
4723 WREG32(DMA_CNTL, dma_cntl); in evergreen_irq_set()
4726 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1); in evergreen_irq_set()
4728 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in evergreen_irq_set()
4730 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in evergreen_irq_set()
4731 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in evergreen_irq_set()
4733 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in evergreen_irq_set()
4734 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in evergreen_irq_set()
4737 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in evergreen_irq_set()
4738 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in evergreen_irq_set()
4741 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in evergreen_irq_set()
4743 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in evergreen_irq_set()
4746 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in evergreen_irq_set()
4748 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in evergreen_irq_set()
4752 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in evergreen_irq_set()
4754 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in evergreen_irq_set()
4758 WREG32(DC_HPD1_INT_CONTROL, hpd1); in evergreen_irq_set()
4759 WREG32(DC_HPD2_INT_CONTROL, hpd2); in evergreen_irq_set()
4760 WREG32(DC_HPD3_INT_CONTROL, hpd3); in evergreen_irq_set()
4761 WREG32(DC_HPD4_INT_CONTROL, hpd4); in evergreen_irq_set()
4762 WREG32(DC_HPD5_INT_CONTROL, hpd5); in evergreen_irq_set()
4763 WREG32(DC_HPD6_INT_CONTROL, hpd6); in evergreen_irq_set()
4765 WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int); in evergreen_irq_set()
4767 WREG32(CG_THERMAL_INT, thermal_int); in evergreen_irq_set()
4769 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1); in evergreen_irq_set()
4770 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2); in evergreen_irq_set()
4771 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3); in evergreen_irq_set()
4772 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4); in evergreen_irq_set()
4773 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); in evergreen_irq_set()
4774 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); in evergreen_irq_set()
4811 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4813 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4815 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4817 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4819 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4821 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4825 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4827 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4829 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4831 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4833 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4835 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4840 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4842 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in evergreen_irq_ack()
4844 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4846 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4848 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in evergreen_irq_ack()
4850 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in evergreen_irq_ack()
4856 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack()
4861 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_irq_ack()
4866 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_irq_ack()
4871 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_irq_ack()
4876 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_irq_ack()
4881 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_irq_ack()
4887 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack()
4892 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_irq_ack()
4897 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_irq_ack()
4902 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_irq_ack()
4907 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_irq_ack()
4912 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_irq_ack()
4918 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4923 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4928 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4933 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4938 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4943 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4982 WREG32(IH_RB_CNTL, tmp); in evergreen_get_ih_wptr()
5374 WREG32(SRBM_INT_ACK, 0x1); in evergreen_irq_process()
5449 WREG32(IH_RB_RPTR, rptr); in evergreen_irq_process()