282 	WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);  in radeon_wait_pll_lock()
294 	WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);  in radeon_wait_pll_lock()
306 	WREG32(RADEON_TV_HOST_WRITE_DATA, value);  in radeon_legacy_tv_write_fifo()
308 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);  in radeon_legacy_tv_write_fifo()
309 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT);  in radeon_legacy_tv_write_fifo()
317 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);  in radeon_legacy_tv_write_fifo()
328 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);
329 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);
337 	WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);
393 	WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);  in radeon_restore_tv_timing_tables()
416 	WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);  in radeon_legacy_write_tv_restarts()
417 	WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);  in radeon_legacy_write_tv_restarts()
418 	WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);  in radeon_legacy_write_tv_restarts()
758 	WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |  in radeon_legacy_tv_mode_set()
767 	WREG32(RADEON_TV_DAC_CNTL, tmp);  in radeon_legacy_tv_mode_set()
788 	WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl);  in radeon_legacy_tv_mode_set()
789 	WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1);  in radeon_legacy_tv_mode_set()
790 	WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1);  in radeon_legacy_tv_mode_set()
791 	WREG32(RADEON_TV_HSTART, const_ptr->hor_start);  in radeon_legacy_tv_mode_set()
793 	WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1);  in radeon_legacy_tv_mode_set()
794 	WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1);  in radeon_legacy_tv_mode_set()
795 	WREG32(RADEON_TV_FTOTAL, tv_ftotal);  in radeon_legacy_tv_mode_set()
796 	WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1);  in radeon_legacy_tv_mode_set()
797 	WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2);  in radeon_legacy_tv_mode_set()
799 	WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl);  in radeon_legacy_tv_mode_set()
800 	WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl);  in radeon_legacy_tv_mode_set()
801 	WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl);  in radeon_legacy_tv_mode_set()
803 	WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |  in radeon_legacy_tv_mode_set()
812 	WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST));  in radeon_legacy_tv_mode_set()
815 	WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE));  in radeon_legacy_tv_mode_set()
816 	WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);  in radeon_legacy_tv_mode_set()
817 	WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1);  in radeon_legacy_tv_mode_set()
818 	WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2);  in radeon_legacy_tv_mode_set()
819 	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN |  in radeon_legacy_tv_mode_set()
824 	WREG32(RADEON_TV_CRC_CNTL, 0);  in radeon_legacy_tv_mode_set()
826 	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);  in radeon_legacy_tv_mode_set()
828 	WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |  in radeon_legacy_tv_mode_set()
830 	WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) |  in radeon_legacy_tv_mode_set()
833 	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);  in radeon_legacy_tv_mode_set()