Lines Matching refs:WREG32
156 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl); in dce3_2_audio_set_dto()
157 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase); in dce3_2_audio_set_dto()
158 WREG32(DCCG_AUDIO_DTO0_MODULE, clock); in dce3_2_audio_set_dto()
159 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ in dce3_2_audio_set_dto()
163 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl); in dce3_2_audio_set_dto()
164 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase); in dce3_2_audio_set_dto()
165 WREG32(DCCG_AUDIO_DTO1_MODULE, clock); in dce3_2_audio_set_dto()
166 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ in dce3_2_audio_set_dto()
176 WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset, in dce3_2_hdmi_update_acr()
207 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, in dce3_2_set_audio_packet()
211 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, in dce3_2_set_audio_packet()