Lines Matching refs:WREG32
89 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); in r600_dma_set_wptr()
107 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
127 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); in r600_dma_resume()
128 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); in r600_dma_resume()
136 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
139 WREG32(DMA_RB_RPTR, 0); in r600_dma_resume()
140 WREG32(DMA_RB_WPTR, 0); in r600_dma_resume()
143 WREG32(DMA_RB_RPTR_ADDR_HI, in r600_dma_resume()
145 WREG32(DMA_RB_RPTR_ADDR_LO, in r600_dma_resume()
151 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); in r600_dma_resume()
158 WREG32(DMA_IB_CNTL, ib_cntl); in r600_dma_resume()
162 WREG32(DMA_CNTL, dma_cntl); in r600_dma_resume()
165 WREG32(DMA_MODE, 1); in r600_dma_resume()
168 WREG32(DMA_RB_WPTR, ring->wptr << 2); in r600_dma_resume()
170 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()