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Searched refs:CLK_SET_RATE_PARENT (Results 1 – 125 of 125) sorted by relevance

/linux-4.4.14/drivers/clk/hisilicon/
Dclk-hi6220.c58 …{ HI6220_WDT0_PCLK, "wdt0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12,…
59 …{ HI6220_WDT1_PCLK, "wdt1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13,…
60 …{ HI6220_WDT2_PCLK, "wdt2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14,…
61 …{ HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15,…
62 …{ HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16,…
63 …{ HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17,…
64 …{ HI6220_TIMER3_PCLK, "timer3_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 18,…
65 …{ HI6220_TIMER4_PCLK, "timer4_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 19,…
66 …{ HI6220_TIMER5_PCLK, "timer5_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 20,…
67 …{ HI6220_TIMER6_PCLK, "timer6_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 21,…
[all …]
Dclk-hi3620.c100 …{ HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p), CLK_SET_RATE_PARENT, 0,…
101 …{ HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p), CLK_SET_RATE_PARENT, 0,…
102 …{ HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p), CLK_SET_RATE_PARENT, 0,…
103 …{ HI3620_TIMER3_MUX, "timer3_mux", timer3_mux_p, ARRAY_SIZE(timer3_mux_p), CLK_SET_RATE_PARENT, 0,…
104 …{ HI3620_TIMER4_MUX, "timer4_mux", timer4_mux_p, ARRAY_SIZE(timer4_mux_p), CLK_SET_RATE_PARENT, 0x…
105 …{ HI3620_TIMER5_MUX, "timer5_mux", timer5_mux_p, ARRAY_SIZE(timer5_mux_p), CLK_SET_RATE_PARENT, 0x…
106 …{ HI3620_TIMER6_MUX, "timer6_mux", timer6_mux_p, ARRAY_SIZE(timer6_mux_p), CLK_SET_RATE_PARENT, 0x…
107 …{ HI3620_TIMER7_MUX, "timer7_mux", timer7_mux_p, ARRAY_SIZE(timer7_mux_p), CLK_SET_RATE_PARENT, 0x…
108 …{ HI3620_TIMER8_MUX, "timer8_mux", timer8_mux_p, ARRAY_SIZE(timer8_mux_p), CLK_SET_RATE_PARENT, 0x…
109 …{ HI3620_TIMER9_MUX, "timer9_mux", timer9_mux_p, ARRAY_SIZE(timer9_mux_p), CLK_SET_RATE_PARENT, 0x…
[all …]
Dclk-hix5hd2.c63 CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
65 CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, },
67 CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, },
70 CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
76 CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
78 CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
81 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
83 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
85 CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, },
88 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
[all …]
/linux-4.4.14/drivers/clk/mmp/
Dclk-of-mmp2.c118 CLK_SET_RATE_PARENT, in mmp2_pll_init()
142 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
143 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
144 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
145 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3…
146 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
147 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
148 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
149 …{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4,…
150 …{0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIM…
[all …]
Dclk-of-pxa168.c106 CLK_SET_RATE_PARENT, in pxa168_pll_init()
131 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
132 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
133 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2…
134 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
135 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
136 …{0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4,…
137 …{0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4,…
138 …{0, "ssp4_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP4, 4,…
139 …{0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIM…
[all …]
Dclk-of-pxa910.c106 CLK_SET_RATE_PARENT, in pxa910_pll_init()
129 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
130 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
131 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
132 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
133 …{0, "timer0_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI…
134 …{0, "timer1_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI…
138 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART…
142 …{PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, …
143 …{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_l…
[all …]
Dclk-of-pxa1928.c81 CLK_SET_RATE_PARENT, in pxa1928_pll_init()
100 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
101 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
102 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
103 …{0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CL…
104 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S…
105 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_S…
109 …{PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0…
110 …{PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0…
111 …{PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0…
[all …]
Dclk-mmp2.c123 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
127 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
131 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
135 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
139 CLK_SET_RATE_PARENT, 1, 5); in mmp2_clk_init()
143 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
147 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
151 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
155 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
159 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
[all …]
Dclk-pxa168.c108 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
112 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
116 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
120 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
124 CLK_SET_RATE_PARENT, 1, 3); in pxa168_clk_init()
128 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
132 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
136 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
140 CLK_SET_RATE_PARENT, 1, 2); in pxa168_clk_init()
144 CLK_SET_RATE_PARENT, 1, 13); in pxa168_clk_init()
[all …]
Dclk-pxa910.c113 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
117 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
121 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
125 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
129 CLK_SET_RATE_PARENT, 1, 3); in pxa910_clk_init()
133 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
137 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
141 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
145 CLK_SET_RATE_PARENT, 1, 2); in pxa910_clk_init()
149 CLK_SET_RATE_PARENT, 1, 13); in pxa910_clk_init()
[all …]
Dclk-apmu.c81 init.flags = CLK_SET_RATE_PARENT; in mmp_clk_register_apmu()
Dclk-apbc.c136 init.flags = CLK_SET_RATE_PARENT; in mmp_clk_register_apbc()
/linux-4.4.14/drivers/clk/samsung/
Dclk-exynos4415.c403 CLK_SET_RATE_PARENT, 0),
480 CLK_SET_RATE_PARENT, 0),
487 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
490 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
500 CLK_SET_RATE_PARENT, 0),
505 CLK_SET_RATE_PARENT, 0),
508 CLK_SET_RATE_PARENT, 0),
513 CLK_SET_RATE_PARENT, 0),
515 CLK_SET_RATE_PARENT, 0),
525 CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos5250.c297 CLK_SET_RATE_PARENT, 0, "mout_apll"),
420 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
434 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
437 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
441 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
444 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
453 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
456 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
460 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
493 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos3250.c322 CLK_SET_RATE_PARENT, 0),
324 CLK_SET_RATE_PARENT, 0),
366 CLK_SET_RATE_PARENT, 0),
373 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
376 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
381 CLK_SET_RATE_PARENT, 0),
386 CLK_SET_RATE_PARENT, 0),
389 CLK_SET_RATE_PARENT, 0),
398 CLK_SET_RATE_PARENT, 0),
401 CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos4.c539 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0,
545 CLK_SET_RATE_PARENT, 0),
547 CLK_SET_RATE_PARENT, 0),
596 CLK_SET_RATE_PARENT, 0),
673 CLK_SET_RATE_PARENT, 0),
760 CLK_SET_RATE_PARENT, 0),
776 CLK_SET_RATE_PARENT, 0),
778 CLK_SET_RATE_PARENT, 0),
780 CLK_SET_RATE_PARENT, 0),
782 CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos7.c343 ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
345 ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
348 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
350 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
352 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
355 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
357 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
360 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
362 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
372 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-s5pv210.c630 CLK_SET_RATE_PARENT, 0),
632 CLK_SET_RATE_PARENT, 0),
634 CLK_SET_RATE_PARENT, 0),
636 CLK_SET_RATE_PARENT, 0),
638 CLK_SET_RATE_PARENT, 0),
640 CLK_SET_RATE_PARENT, 0),
642 CLK_SET_RATE_PARENT, 0),
644 CLK_SET_RATE_PARENT, 0),
646 CLK_SET_RATE_PARENT, 0),
648 CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos5410.c129 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
131 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
133 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
148 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
150 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
152 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
163 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
165 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
167 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
Dclk-exynos5420.c889 CLK_SET_RATE_PARENT, 0),
891 CLK_SET_RATE_PARENT, 0),
950 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
952 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
954 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
956 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
958 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
960 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
962 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
964 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos5433.c503 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
505 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
577 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
580 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
583 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
586 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
589 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
592 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
595 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
598 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
[all …]
Dclk-exynos-audss.c191 "dout_srp", CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
195 "dout_aud_bus", CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
199 "dout_i2s", CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
203 "sclk_pcm", CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
210 sclk_pcm_p, CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
215 "dout_srp", CLK_SET_RATE_PARENT, in exynos_audss_clk_probe()
Dclk-exynos5260.c118 EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),
120 EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
122 EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
289 EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),
292 EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
720 EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),
722 EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0),
887 EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0),
889 EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
891 EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
[all …]
Dclk-exynos-clkout.c106 &clk_gate_ops, CLK_SET_RATE_PARENT in exynos_clkout_init()
Dclk-s3c2410-dclk.c294 "div_dclk0", CLK_SET_RATE_PARENT, in s3c24xx_dclk_probe()
298 "div_dclk1", CLK_SET_RATE_PARENT, in s3c24xx_dclk_probe()
Dclk-s5pv210-audss.c143 "dout_i2s_audss", CLK_SET_RATE_PARENT, in s5pv210_audss_clk_probe()
Dclk-cpu.c295 init.flags = CLK_SET_RATE_PARENT; in exynos_register_cpu_clock()
Dclk-s3c2412.c114 FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT),
Dclk-s3c2410.c279 FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
Dclk-s3c64xx.c55 GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
/linux-4.4.14/drivers/clk/qcom/
Dmmcc-apq8084.c585 .flags = CLK_SET_RATE_PARENT,
599 .flags = CLK_SET_RATE_PARENT,
850 .flags = CLK_SET_RATE_PARENT,
863 .flags = CLK_SET_RATE_PARENT,
901 .flags = CLK_SET_RATE_PARENT,
970 .flags = CLK_SET_RATE_PARENT,
1119 .flags = CLK_SET_RATE_PARENT,
1136 .flags = CLK_SET_RATE_PARENT,
1153 .flags = CLK_SET_RATE_PARENT,
1170 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-msm8916.c992 .flags = CLK_SET_RATE_PARENT,
1049 .flags = CLK_SET_RATE_PARENT,
1238 .flags = CLK_SET_RATE_PARENT,
1255 .flags = CLK_SET_RATE_PARENT,
1312 .flags = CLK_SET_RATE_PARENT,
1343 .flags = CLK_SET_RATE_PARENT,
1374 .flags = CLK_SET_RATE_PARENT,
1409 .flags = CLK_SET_RATE_PARENT,
1426 .flags = CLK_SET_RATE_PARENT,
1462 .flags = CLK_SET_RATE_PARENT,
[all …]
Dmmcc-msm8974.c536 .flags = CLK_SET_RATE_PARENT,
550 .flags = CLK_SET_RATE_PARENT,
783 .flags = CLK_SET_RATE_PARENT,
797 .flags = CLK_SET_RATE_PARENT,
835 .flags = CLK_SET_RATE_PARENT,
904 .flags = CLK_SET_RATE_PARENT,
971 .flags = CLK_SET_RATE_PARENT,
1004 .flags = CLK_SET_RATE_PARENT,
1021 .flags = CLK_SET_RATE_PARENT,
1038 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-apq8084.c298 .flags = CLK_SET_RATE_PARENT,
315 .flags = CLK_SET_RATE_PARENT,
1341 .flags = CLK_SET_RATE_PARENT,
1428 .flags = CLK_SET_RATE_PARENT,
1445 .flags = CLK_SET_RATE_PARENT,
1462 .flags = CLK_SET_RATE_PARENT,
1479 .flags = CLK_SET_RATE_PARENT,
1496 .flags = CLK_SET_RATE_PARENT,
1513 .flags = CLK_SET_RATE_PARENT,
1530 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-msm8974.c1106 .flags = CLK_SET_RATE_PARENT,
1123 .flags = CLK_SET_RATE_PARENT,
1140 .flags = CLK_SET_RATE_PARENT,
1157 .flags = CLK_SET_RATE_PARENT,
1174 .flags = CLK_SET_RATE_PARENT,
1191 .flags = CLK_SET_RATE_PARENT,
1208 .flags = CLK_SET_RATE_PARENT,
1225 .flags = CLK_SET_RATE_PARENT,
1242 .flags = CLK_SET_RATE_PARENT,
1259 .flags = CLK_SET_RATE_PARENT,
[all …]
Dlcc-msm8960.c146 .flags = CLK_SET_RATE_PARENT,
179 .flags = CLK_SET_RATE_PARENT,
197 .flags = CLK_SET_RATE_PARENT,
252 .flags = CLK_SET_RATE_PARENT, \
285 .flags = CLK_SET_RATE_PARENT, \
303 .flags = CLK_SET_RATE_PARENT, \
392 .flags = CLK_SET_RATE_PARENT,
410 .flags = CLK_SET_RATE_PARENT,
464 .flags = CLK_SET_RATE_PARENT,
481 .flags = CLK_SET_RATE_PARENT,
Dgcc-msm8660.c154 .flags = CLK_SET_RATE_PARENT,
205 .flags = CLK_SET_RATE_PARENT,
256 .flags = CLK_SET_RATE_PARENT,
307 .flags = CLK_SET_RATE_PARENT,
358 .flags = CLK_SET_RATE_PARENT,
409 .flags = CLK_SET_RATE_PARENT,
460 .flags = CLK_SET_RATE_PARENT,
509 .flags = CLK_SET_RATE_PARENT,
558 .flags = CLK_SET_RATE_PARENT,
607 .flags = CLK_SET_RATE_PARENT,
[all …]
Dmmcc-msm8960.c374 .flags = CLK_SET_RATE_PARENT,
390 .flags = CLK_SET_RATE_PARENT,
438 .flags = CLK_SET_RATE_PARENT,
454 .flags = CLK_SET_RATE_PARENT,
502 .flags = CLK_SET_RATE_PARENT,
518 .flags = CLK_SET_RATE_PARENT,
756 .flags = CLK_SET_RATE_PARENT,
772 .flags = CLK_SET_RATE_PARENT,
788 .flags = CLK_SET_RATE_PARENT,
864 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-msm8960.c221 .flags = CLK_SET_RATE_PARENT,
272 .flags = CLK_SET_RATE_PARENT,
323 .flags = CLK_SET_RATE_PARENT,
374 .flags = CLK_SET_RATE_PARENT,
425 .flags = CLK_SET_RATE_PARENT,
476 .flags = CLK_SET_RATE_PARENT,
527 .flags = CLK_SET_RATE_PARENT,
576 .flags = CLK_SET_RATE_PARENT,
625 .flags = CLK_SET_RATE_PARENT,
674 .flags = CLK_SET_RATE_PARENT,
[all …]
Dgcc-ipq806x.c315 .flags = CLK_SET_RATE_PARENT,
366 .flags = CLK_SET_RATE_PARENT,
417 .flags = CLK_SET_RATE_PARENT,
468 .flags = CLK_SET_RATE_PARENT,
519 .flags = CLK_SET_RATE_PARENT,
570 .flags = CLK_SET_RATE_PARENT,
632 .flags = CLK_SET_RATE_PARENT,
681 .flags = CLK_SET_RATE_PARENT,
730 .flags = CLK_SET_RATE_PARENT,
779 .flags = CLK_SET_RATE_PARENT,
[all …]
Dlcc-ipq806x.c165 .flags = CLK_SET_RATE_PARENT,
196 .flags = CLK_SET_RATE_PARENT,
215 .flags = CLK_SET_RATE_PARENT,
275 .flags = CLK_SET_RATE_PARENT,
293 .flags = CLK_SET_RATE_PARENT,
359 .flags = CLK_SET_RATE_PARENT,
Dclk-rcg2.c197 if (clk_flags & CLK_SET_RATE_PARENT) { in _freq_tbl_determine_rate()
Dclk-rcg.c425 if (clk_flags & CLK_SET_RATE_PARENT) { in _freq_tbl_determine_rate()
/linux-4.4.14/drivers/clk/spear/
Dspear3xx_clock.c299 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
305 CLK_SET_RATE_PARENT, 1, in spear320_clk_init()
319 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
326 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
342 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
351 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
360 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
367 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
374 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
381 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
[all …]
Dspear1340_clock.c644 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1340_clk_init()
650 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, in spear1340_clk_init()
678 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, in spear1340_clk_init()
689 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, in spear1340_clk_init()
702 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1340_clk_init()
707 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT, in spear1340_clk_init()
747 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1340_clk_init()
765 CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG, in spear1340_clk_init()
772 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1340_clk_init()
861 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, in spear1340_clk_init()
[all …]
Dspear1310_clock.c496 CLK_SET_RATE_PARENT, 1, 2); in spear1310_clk_init()
565 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
571 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, in spear1310_clk_init()
582 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, in spear1310_clk_init()
593 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, in spear1310_clk_init()
606 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
651 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
675 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear1310_clk_init()
776 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, in spear1310_clk_init()
Dspear6xx_clock.c156 CLK_SET_RATE_PARENT, 1, 1); in spear6xx_clk_init()
160 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, in spear6xx_clk_init()
287 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, in spear6xx_clk_init()
Dclk-aux-synth.c183 CLK_SET_RATE_PARENT, reg, in clk_register_aux()
Dclk-vco-pll.c338 pll_init.flags = CLK_SET_RATE_PARENT; in clk_register_vco_pll()
/linux-4.4.14/drivers/clk/tegra/
Dclk-tegra-super-gen4.c65 CLK_SET_RATE_PARENT, in tegra_sclk_init()
78 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, in tegra_sclk_init()
92 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | in tegra_sclk_init()
111 CLK_SET_RATE_PARENT, in tegra_super_clk_gen4_init()
122 CLK_SET_RATE_PARENT, in tegra_super_clk_gen4_init()
146 CLK_SET_RATE_PARENT, 1, 2); in tegra_super_clk_gen4_init()
Dclk-tegra-fixed.c100 CLK_SET_RATE_PARENT, 1, 2); in tegra_fixed_clk_init()
108 CLK_SET_RATE_PARENT, 1, 4); in tegra_fixed_clk_init()
Dclk-tegra-audio.c161 CLK_SET_RATE_PARENT, 0, NULL); in tegra_audio_clk_init()
213 data->parent, CLK_SET_RATE_PARENT, 2, 1); in tegra_audio_clk_init()
220 clk_base, CLK_SET_RATE_PARENT, data->clk_num, in tegra_audio_clk_init()
Dclk-tegra20.c649 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra20_pll_init()
665 CLK_SET_RATE_PARENT, 0, NULL); in tegra20_pll_init()
685 CLK_SET_RATE_PARENT, 1, 2); in tegra20_pll_init()
699 CLK_SET_RATE_PARENT, 0, NULL); in tegra20_pll_init()
721 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, in tegra20_super_clk_init()
727 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT, in tegra20_super_clk_init()
756 CLK_SET_RATE_PARENT, 2, 1); in tegra20_audio_clk_init()
759 CLK_SET_RATE_PARENT, 89, in tegra20_audio_clk_init()
893 CLK_SET_RATE_PARENT, 1, pll_ref_div); in tegra20_osc_clk_init()
Dclk-tegra114.c956 CLK_SET_RATE_PARENT, 1, 2); in tegra114_fixed_clk_init()
961 CLK_SET_RATE_PARENT, 1, 4); in tegra114_fixed_clk_init()
1065 CLK_SET_RATE_PARENT, 0, NULL); in tegra114_pll_init()
1090 CLK_SET_RATE_PARENT, 0, NULL); in tegra114_pll_init()
1095 CLK_SET_RATE_PARENT, 1, 1); in tegra114_pll_init()
1110 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra114_pll_init()
1116 CLK_SET_RATE_PARENT, 1, 8); in tegra114_pll_init()
1121 CLK_SET_RATE_PARENT, 1, 10); in tegra114_pll_init()
1126 CLK_SET_RATE_PARENT, 1, 40); in tegra114_pll_init()
1136 CLK_SET_RATE_PARENT, 1, 2); in tegra114_pll_init()
[all …]
Dclk-tegra124.c1168 CLK_SET_RATE_PARENT, 0, NULL); in tegra124_pll_init()
1174 CLK_SET_RATE_PARENT, 1, 1); in tegra124_pll_init()
1203 CLK_SET_RATE_PARENT, 0, NULL); in tegra124_pll_init()
1209 CLK_SET_RATE_PARENT, 1, 1); in tegra124_pll_init()
1227 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra124_pll_init()
1234 CLK_SET_RATE_PARENT, 1, 8); in tegra124_pll_init()
1240 CLK_SET_RATE_PARENT, 1, 10); in tegra124_pll_init()
1246 CLK_SET_RATE_PARENT, 1, 40); in tegra124_pll_init()
1258 CLK_SET_RATE_PARENT, 1, 2); in tegra124_pll_init()
1300 CLK_SET_RATE_PARENT, 1, 1); in tegra124_pll_init()
Dclk-tegra30.c936 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra30_pll_init()
952 CLK_SET_RATE_PARENT, 0, NULL); in tegra30_pll_init()
962 CLK_SET_RATE_PARENT, 1, 2); in tegra30_pll_init()
979 CLK_SET_RATE_PARENT, 1, 2); in tegra30_pll_init()
989 CLK_SET_RATE_PARENT, 1, 2); in tegra30_pll_init()
1047 CLK_SET_RATE_PARENT, in tegra30_super_clk_init()
1082 CLK_SET_RATE_PARENT, in tegra30_super_clk_init()
1091 CLK_SET_RATE_PARENT, in tegra30_super_clk_init()
1098 CLK_SET_RATE_PARENT, 1, 2); in tegra30_super_clk_init()
Dclk-periph.c152 flags |= CLK_SET_RATE_PARENT; in _tegra_clk_register_periph()
204 periph, clk_base, offset, CLK_SET_RATE_PARENT); in tegra_clk_register_periph_nodiv()
Dclk-tegra-periph.c668 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, in init_pllp()
/linux-4.4.14/drivers/clk/zynq/
Dclkc.c154 CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, in zynq_clk_register_fclk()
159 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, in zynq_clk_register_fclk()
210 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); in zynq_clk_register_periph_clk()
213 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); in zynq_clk_register_periph_clk()
300 "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, in zynq_clk_setup()
334 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | in zynq_clk_setup()
356 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, in zynq_clk_setup()
360 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, in zynq_clk_setup()
407 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, in zynq_clk_setup()
411 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in zynq_clk_setup()
[all …]
/linux-4.4.14/drivers/clk/imx/
Dclk-imx6q.c184 …_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
185 …_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
186 …_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
187 …_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
188 …_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
189 …_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
190 …_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init()
272 … = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x7… in imx6q_clocks_init()
273 …V] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x1… in imx6q_clocks_init()
274 … = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa… in imx6q_clocks_init()
[all …]
Dclk.h57 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate2()
65 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate2_shared()
96 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, in imx_clk_divider()
111 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate()
118 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, in imx_clk_gate_dis()
143 CLK_SET_RATE_PARENT, mult, div); in imx_clk_fixed_factor()
Dclk-imx6sx.c183 …_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
184 …_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
185 …_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
186 …_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
187 …_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
188 …_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
189 …_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); in imx6sx_clocks_init()
261 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
263 CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); in imx6sx_clocks_init()
265 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
[all …]
Dclk-imx6sl.c229 …_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
230 …_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
231 …_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
232 …_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
233 …_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
234 …_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
235 …_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); in imx6sl_clocks_init()
271 …lk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x7… in imx6sl_clocks_init()
272 … clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x1… in imx6sl_clocks_init()
273 …lk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa… in imx6sl_clocks_init()
[all …]
Dclk-imx6ul.c141 …_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); in imx6ul_clocks_init()
142 …_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); in imx6ul_clocks_init()
143 …_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); in imx6ul_clocks_init()
144 …_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); in imx6ul_clocks_init()
145 …_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); in imx6ul_clocks_init()
146 …_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); in imx6ul_clocks_init()
147 …_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); in imx6ul_clocks_init()
148 …x_clk_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT); in imx6ul_clocks_init()
203 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
205 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock); in imx6ul_clocks_init()
[all …]
Dclk-vf610.c182 …l1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
183 …l2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
184 …l3_bypass", PLL3_CTRL, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
185 …l4_bypass", PLL4_CTRL, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
186 …l5_bypass", PLL5_CTRL, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
187 …l6_bypass", PLL6_CTRL, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
188 …l7_bypass", PLL7_CTRL, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); in vf610_clocks_init()
Dclk-gate-exclusive.c79 init.flags = CLK_SET_RATE_PARENT; in imx_clk_gate_exclusive()
Dclk-imx51-imx53.c297 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); in mx5_clocks_common_init()
423 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT); in mx51_clocks_init()
514 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT); in mx53_clocks_init()
519 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); in mx53_clocks_init()
527 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); in mx53_clocks_init()
Dclk-imx7d.c404 …ass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT); in imx7d_clocks_init()
405 …s", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT); in imx7d_clocks_init()
406 …ass", base + 0xb0, 16, 1, pll_sys_bypass_sel, ARRAY_SIZE(pll_sys_bypass_sel), CLK_SET_RATE_PARENT); in imx7d_clocks_init()
407 …s", base + 0xe0, 16, 1, pll_enet_bypass_sel, ARRAY_SIZE(pll_enet_bypass_sel), CLK_SET_RATE_PARENT); in imx7d_clocks_init()
408 …, base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT); in imx7d_clocks_init()
409 … base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT); in imx7d_clocks_init()
Dclk-fixup-div.c112 init.flags = CLK_SET_RATE_PARENT; in imx_clk_fixup_divider()
Dclk-busy.c104 init.flags = CLK_SET_RATE_PARENT; in imx_clk_busy_divider()
/linux-4.4.14/drivers/clk/sunxi/
Dclk-a10-pll2.c108 CLK_SET_RATE_PARENT); in sun4i_pll2_setup()
132 CLK_SET_RATE_PARENT, in sun4i_pll2_setup()
147 CLK_SET_RATE_PARENT, in sun4i_pll2_setup()
156 CLK_SET_RATE_PARENT, in sun4i_pll2_setup()
165 CLK_SET_RATE_PARENT, in sun4i_pll2_setup()
Dclk-a10-codec.c37 CLK_SET_RATE_PARENT, reg, in sun4i_codec_clk_setup()
Dclk-sunxi.c136 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) in sun6i_ahb1_clk_determine_rate()
796 CLK_SET_RATE_PARENT, reg, in sunxi_mux_clk_setup()
1012 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; in sunxi_divs_clk_setup()
Dclk-factors.c95 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) in clk_factors_determine_rate()
/linux-4.4.14/drivers/clk/mxs/
Dclk.h47 return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT, in mxs_clk_gate()
56 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mxs_clk_mux()
64 CLK_SET_RATE_PARENT, mult, div); in mxs_clk_fixed_factor()
Dclk-div.c89 init.flags = CLK_SET_RATE_PARENT; in mxs_clk_div()
Dclk-frac.c129 init.flags = CLK_SET_RATE_PARENT; in mxs_clk_frac()
/linux-4.4.14/drivers/clk/
Dclk-stm32f4.c178 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in clk_apb_mul_round_rate()
334 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, in stm32f4_rcc_init()
338 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, in stm32f4_rcc_init()
341 CLK_SET_RATE_PARENT, 12); in stm32f4_rcc_init()
344 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR, in stm32f4_rcc_init()
347 CLK_SET_RATE_PARENT, 15); in stm32f4_rcc_init()
Dclk-asm9260.c306 gd->parent_name, gd->flags | CLK_SET_RATE_PARENT, in asm9260_acc_init()
315 dc->parent_name, CLK_SET_RATE_PARENT, in asm9260_acc_init()
Dclk-fixed-factor.c44 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in clk_factor_round_rate()
Dclk-multiplier.c61 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) in __bestmult()
Dclk-cdce706.c313 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in cdce706_divider_round_rate()
563 .flags = CLK_SET_RATE_PARENT, in cdce706_register_dividers()
599 .flags = CLK_SET_RATE_PARENT, in cdce706_register_clkouts()
Dclk-si5351.c666 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in si5351_msynth_round_rate()
1016 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in si5351_clkout_round_rate()
1540 init.flags |= CLK_SET_RATE_PARENT; in si5351_i2c_probe()
1568 init.flags |= CLK_SET_RATE_PARENT; in si5351_i2c_probe()
Dclk-wm831x.c349 .flags = CLK_SET_RATE_PARENT,
Dclk.c465 if (core->flags & CLK_SET_RATE_PARENT) { in clk_mux_determine_rate_flags()
488 if (core->flags & CLK_SET_RATE_PARENT) { in clk_mux_determine_rate_flags()
814 } else if (core->flags & CLK_SET_RATE_PARENT) { in clk_core_round_rate_nolock()
1348 } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) { in clk_calc_new_rates()
1377 if ((core->flags & CLK_SET_RATE_PARENT) && parent && in clk_calc_new_rates()
Dclk-divider.c293 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in clk_divider_bestdiv()
Dclk-cdce925.c677 init.flags = CLK_SET_RATE_PARENT; in cdce925_probe()
/linux-4.4.14/drivers/clk/sirf/
Dclk-atlas7.c1503 CLK_SET_RATE_PARENT, 1, 2); in atlas7_clk_init()
1518 CLK_SET_RATE_PARENT, 1, 2); in atlas7_clk_init()
1533 CLK_SET_RATE_PARENT, 1, 2); in atlas7_clk_init()
1548 CLK_SET_RATE_PARENT, 1, 2); in atlas7_clk_init()
1552 CLK_SET_RATE_PARENT, 1, 4); in atlas7_clk_init()
1556 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, in atlas7_clk_init()
1560 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, in atlas7_clk_init()
1564 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, in atlas7_clk_init()
1569 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, in atlas7_clk_init()
1574 CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, in atlas7_clk_init()
[all …]
Dclk-common.c504 .flags = CLK_SET_RATE_PARENT,
/linux-4.4.14/drivers/clk/rockchip/
Dclk-rk3368.c251 MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT,
340 COMPOSITE_FRAC(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
343 MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
348 GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
353 COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
362 COMPOSITE_FRAC(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
380 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
563 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
566 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
572 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
[all …]
Dclk-rk3288.c286 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
307 COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
310 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
315 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
539 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
542 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
549 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
552 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
557 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
560 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
[all …]
Dclk-rockchip.c37 int clkflags = CLK_SET_RATE_PARENT; in rk2928_gate_clk_init()
Dclk-inverter.c97 init.flags = CLK_SET_RATE_PARENT; in rockchip_clk_register_inverter()
Dclk-rk3188.c330 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
353 COMPOSITE_FRAC(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
356 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
Dclk-cpu.c260 init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0; in rockchip_clk_register_cpuclk()
Dclk.c264 flags |= CLK_SET_RATE_PARENT; in rockchip_clk_register_branches()
Dclk-pll.c388 init.flags = CLK_SET_RATE_PARENT; in rockchip_clk_register_pll()
/linux-4.4.14/drivers/clk/mediatek/
Dclk-mtk.h97 .flags = CLK_SET_RATE_PARENT, \
110 .flags = CLK_SET_RATE_PARENT, \
Dclk-gate.c119 init.flags = CLK_SET_RATE_PARENT; in mtk_clk_register_gate()
Dclk-mtk.c85 CLK_SET_RATE_PARENT, ff->mult, ff->div); in mtk_clk_register_factors()
/linux-4.4.14/drivers/clk/ti/
Dfixed-factor.c55 flags |= CLK_SET_RATE_PARENT; in of_ti_fixed_factor_clk_setup()
Dmux.c166 flags |= CLK_SET_RATE_PARENT; in ti_clk_register_mux()
212 flags |= CLK_SET_RATE_PARENT; in of_mux_clk_setup()
Dgate.c152 flags |= CLK_SET_RATE_PARENT; in ti_clk_register_gate()
243 flags |= CLK_SET_RATE_PARENT; in _of_ti_gate_clk_setup()
Ddivider.c158 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in ti_clk_divider_bestdiv()
407 flags |= CLK_SET_RATE_PARENT; in ti_clk_register_divider()
542 *flags |= CLK_SET_RATE_PARENT; in ti_clk_divider_populate()
/linux-4.4.14/drivers/clk/at91/
Dclk-usb.c216 CLK_SET_RATE_PARENT; in at91sam9x5_clk_register_usb()
244 init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; in at91sam9n12_clk_register_usb()
359 init.flags = CLK_SET_RATE_PARENT; in at91rm9200_clk_register_usb()
Dclk-system.c122 init.flags = CLK_SET_RATE_PARENT; in at91_clk_register_system()
/linux-4.4.14/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll_28nm.c541 parent1, CLK_SET_RATE_PARENT, in pll_28nm_register()
549 parent1, CLK_SET_RATE_PARENT, in pll_28nm_register()
566 }, 2, CLK_SET_RATE_PARENT, pll_28nm->mmio + in pll_28nm_register()
573 parent1, CLK_SET_RATE_PARENT, 1, 4); in pll_28nm_register()
/linux-4.4.14/drivers/clk/pistachio/
Dclk.c69 CLK_SET_RATE_PARENT, in pistachio_clk_register_gate()
/linux-4.4.14/arch/powerpc/platforms/512x/
Dclock-commonclk.c233 clkflags = CLK_SET_RATE_PARENT; in mpc512x_clk_factor()
265 clkflags = CLK_SET_RATE_PARENT; in mpc512x_clk_gated()
277 clkflags = CLK_SET_RATE_PARENT; in mpc512x_clk_muxed()
/linux-4.4.14/drivers/clk/meson/
Dclk-cpu.c207 init.flags |= CLK_SET_RATE_PARENT; in meson_clk_register_cpu()
/linux-4.4.14/drivers/clk/ux500/
Du8500_of_clk.c517 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); in u8500_clk_init()
522 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); in u8500_clk_init()
Du8540_clk.c549 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); in u8540_clk_init()
554 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); in u8540_clk_init()
/linux-4.4.14/drivers/clk/st/
Dclkgen-mux.c661 data->clk_flags | CLK_SET_RATE_PARENT, in st_of_clkgen_mux_setup()
696 .clk_flags = CLK_SET_RATE_PARENT,
Dclk-flexgen.c112 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in flexgen_round_rate()
Dclkgen-pll.c1007 flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT; in clkgen_odf_register()
/linux-4.4.14/drivers/clk/shmobile/
Dclk-mstp.c146 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; in cpg_mstp_clock_register()
/linux-4.4.14/sound/soc/samsung/
Di2s.c1191 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, in i2s_register_clock_provider()
1197 CLK_SET_RATE_PARENT, in i2s_register_clock_provider()
1207 p_names[0], CLK_SET_RATE_PARENT, in i2s_register_clock_provider()
/linux-4.4.14/drivers/clk/bcm/
Dclk-bcm2835.c1373 init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; in bcm2835_register_pll_divider()
1401 CLK_SET_RATE_PARENT, in bcm2835_register_pll_divider()
1442 CLK_SET_RATE_PARENT, in bcm2835_register_clock()
/linux-4.4.14/drivers/mfd/
Dintel-lpss.c316 CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL); in intel_lpss_register_clock_divider()
/linux-4.4.14/arch/mips/alchemy/common/
Dclock.c764 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE; in alchemy_clk_init_fgens()
960 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE; in alchemy_clk_setup_imux()
/linux-4.4.14/include/linux/
Dclk-provider.h26 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ macro
/linux-4.4.14/drivers/clk/zte/
Dclk-zx296702.c225 reg, shift, CLK_SET_RATE_PARENT, &reg_lock); in zx_gate()
/linux-4.4.14/drivers/acpi/
Dacpi_lpss.c329 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, in register_device_clock()
/linux-4.4.14/drivers/clk/ingenic/
Dcgu.c618 clk_init.flags |= CLK_SET_RATE_PARENT; in ingenic_register_clock()
/linux-4.4.14/drivers/media/platform/exynos4-is/
Dmedia-dev.c1239 init.flags = CLK_SET_RATE_PARENT; in fimc_md_register_clk_provider()