1/* 2 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <linux/kernel.h> 15#include <linux/bitops.h> 16#include <linux/err.h> 17#include <linux/platform_device.h> 18#include <linux/module.h> 19#include <linux/of.h> 20#include <linux/of_device.h> 21#include <linux/clk-provider.h> 22#include <linux/regmap.h> 23#include <linux/reset-controller.h> 24 25#include <dt-bindings/clock/qcom,gcc-ipq806x.h> 26#include <dt-bindings/reset/qcom,gcc-ipq806x.h> 27 28#include "common.h" 29#include "clk-regmap.h" 30#include "clk-pll.h" 31#include "clk-rcg.h" 32#include "clk-branch.h" 33#include "reset.h" 34 35static struct clk_pll pll0 = { 36 .l_reg = 0x30c4, 37 .m_reg = 0x30c8, 38 .n_reg = 0x30cc, 39 .config_reg = 0x30d4, 40 .mode_reg = 0x30c0, 41 .status_reg = 0x30d8, 42 .status_bit = 16, 43 .clkr.hw.init = &(struct clk_init_data){ 44 .name = "pll0", 45 .parent_names = (const char *[]){ "pxo" }, 46 .num_parents = 1, 47 .ops = &clk_pll_ops, 48 }, 49}; 50 51static struct clk_regmap pll0_vote = { 52 .enable_reg = 0x34c0, 53 .enable_mask = BIT(0), 54 .hw.init = &(struct clk_init_data){ 55 .name = "pll0_vote", 56 .parent_names = (const char *[]){ "pll0" }, 57 .num_parents = 1, 58 .ops = &clk_pll_vote_ops, 59 }, 60}; 61 62static struct clk_pll pll3 = { 63 .l_reg = 0x3164, 64 .m_reg = 0x3168, 65 .n_reg = 0x316c, 66 .config_reg = 0x3174, 67 .mode_reg = 0x3160, 68 .status_reg = 0x3178, 69 .status_bit = 16, 70 .clkr.hw.init = &(struct clk_init_data){ 71 .name = "pll3", 72 .parent_names = (const char *[]){ "pxo" }, 73 .num_parents = 1, 74 .ops = &clk_pll_ops, 75 }, 76}; 77 78static struct clk_regmap pll4_vote = { 79 .enable_reg = 0x34c0, 80 .enable_mask = BIT(4), 81 .hw.init = &(struct clk_init_data){ 82 .name = "pll4_vote", 83 .parent_names = (const char *[]){ "pll4" }, 84 .num_parents = 1, 85 .ops = &clk_pll_vote_ops, 86 }, 87}; 88 89static struct clk_pll pll8 = { 90 .l_reg = 0x3144, 91 .m_reg = 0x3148, 92 .n_reg = 0x314c, 93 .config_reg = 0x3154, 94 .mode_reg = 0x3140, 95 .status_reg = 0x3158, 96 .status_bit = 16, 97 .clkr.hw.init = &(struct clk_init_data){ 98 .name = "pll8", 99 .parent_names = (const char *[]){ "pxo" }, 100 .num_parents = 1, 101 .ops = &clk_pll_ops, 102 }, 103}; 104 105static struct clk_regmap pll8_vote = { 106 .enable_reg = 0x34c0, 107 .enable_mask = BIT(8), 108 .hw.init = &(struct clk_init_data){ 109 .name = "pll8_vote", 110 .parent_names = (const char *[]){ "pll8" }, 111 .num_parents = 1, 112 .ops = &clk_pll_vote_ops, 113 }, 114}; 115 116static struct clk_pll pll14 = { 117 .l_reg = 0x31c4, 118 .m_reg = 0x31c8, 119 .n_reg = 0x31cc, 120 .config_reg = 0x31d4, 121 .mode_reg = 0x31c0, 122 .status_reg = 0x31d8, 123 .status_bit = 16, 124 .clkr.hw.init = &(struct clk_init_data){ 125 .name = "pll14", 126 .parent_names = (const char *[]){ "pxo" }, 127 .num_parents = 1, 128 .ops = &clk_pll_ops, 129 }, 130}; 131 132static struct clk_regmap pll14_vote = { 133 .enable_reg = 0x34c0, 134 .enable_mask = BIT(14), 135 .hw.init = &(struct clk_init_data){ 136 .name = "pll14_vote", 137 .parent_names = (const char *[]){ "pll14" }, 138 .num_parents = 1, 139 .ops = &clk_pll_vote_ops, 140 }, 141}; 142 143#define NSS_PLL_RATE(f, _l, _m, _n, i) \ 144 { \ 145 .freq = f, \ 146 .l = _l, \ 147 .m = _m, \ 148 .n = _n, \ 149 .ibits = i, \ 150 } 151 152static struct pll_freq_tbl pll18_freq_tbl[] = { 153 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), 154 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), 155}; 156 157static struct clk_pll pll18 = { 158 .l_reg = 0x31a4, 159 .m_reg = 0x31a8, 160 .n_reg = 0x31ac, 161 .config_reg = 0x31b4, 162 .mode_reg = 0x31a0, 163 .status_reg = 0x31b8, 164 .status_bit = 16, 165 .post_div_shift = 16, 166 .post_div_width = 1, 167 .freq_tbl = pll18_freq_tbl, 168 .clkr.hw.init = &(struct clk_init_data){ 169 .name = "pll18", 170 .parent_names = (const char *[]){ "pxo" }, 171 .num_parents = 1, 172 .ops = &clk_pll_ops, 173 }, 174}; 175 176enum { 177 P_PXO, 178 P_PLL8, 179 P_PLL3, 180 P_PLL0, 181 P_CXO, 182 P_PLL14, 183 P_PLL18, 184}; 185 186static const struct parent_map gcc_pxo_pll8_map[] = { 187 { P_PXO, 0 }, 188 { P_PLL8, 3 } 189}; 190 191static const char * const gcc_pxo_pll8[] = { 192 "pxo", 193 "pll8_vote", 194}; 195 196static const struct parent_map gcc_pxo_pll8_cxo_map[] = { 197 { P_PXO, 0 }, 198 { P_PLL8, 3 }, 199 { P_CXO, 5 } 200}; 201 202static const char * const gcc_pxo_pll8_cxo[] = { 203 "pxo", 204 "pll8_vote", 205 "cxo", 206}; 207 208static const struct parent_map gcc_pxo_pll3_map[] = { 209 { P_PXO, 0 }, 210 { P_PLL3, 1 } 211}; 212 213static const struct parent_map gcc_pxo_pll3_sata_map[] = { 214 { P_PXO, 0 }, 215 { P_PLL3, 6 } 216}; 217 218static const char * const gcc_pxo_pll3[] = { 219 "pxo", 220 "pll3", 221}; 222 223static const struct parent_map gcc_pxo_pll8_pll0[] = { 224 { P_PXO, 0 }, 225 { P_PLL8, 3 }, 226 { P_PLL0, 2 } 227}; 228 229static const char * const gcc_pxo_pll8_pll0_map[] = { 230 "pxo", 231 "pll8_vote", 232 "pll0_vote", 233}; 234 235static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { 236 { P_PXO, 0 }, 237 { P_PLL8, 4 }, 238 { P_PLL0, 2 }, 239 { P_PLL14, 5 }, 240 { P_PLL18, 1 } 241}; 242 243static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { 244 "pxo", 245 "pll8_vote", 246 "pll0_vote", 247 "pll14", 248 "pll18", 249}; 250 251static struct freq_tbl clk_tbl_gsbi_uart[] = { 252 { 1843200, P_PLL8, 2, 6, 625 }, 253 { 3686400, P_PLL8, 2, 12, 625 }, 254 { 7372800, P_PLL8, 2, 24, 625 }, 255 { 14745600, P_PLL8, 2, 48, 625 }, 256 { 16000000, P_PLL8, 4, 1, 6 }, 257 { 24000000, P_PLL8, 4, 1, 4 }, 258 { 32000000, P_PLL8, 4, 1, 3 }, 259 { 40000000, P_PLL8, 1, 5, 48 }, 260 { 46400000, P_PLL8, 1, 29, 240 }, 261 { 48000000, P_PLL8, 4, 1, 2 }, 262 { 51200000, P_PLL8, 1, 2, 15 }, 263 { 56000000, P_PLL8, 1, 7, 48 }, 264 { 58982400, P_PLL8, 1, 96, 625 }, 265 { 64000000, P_PLL8, 2, 1, 3 }, 266 { } 267}; 268 269static struct clk_rcg gsbi1_uart_src = { 270 .ns_reg = 0x29d4, 271 .md_reg = 0x29d0, 272 .mn = { 273 .mnctr_en_bit = 8, 274 .mnctr_reset_bit = 7, 275 .mnctr_mode_shift = 5, 276 .n_val_shift = 16, 277 .m_val_shift = 16, 278 .width = 16, 279 }, 280 .p = { 281 .pre_div_shift = 3, 282 .pre_div_width = 2, 283 }, 284 .s = { 285 .src_sel_shift = 0, 286 .parent_map = gcc_pxo_pll8_map, 287 }, 288 .freq_tbl = clk_tbl_gsbi_uart, 289 .clkr = { 290 .enable_reg = 0x29d4, 291 .enable_mask = BIT(11), 292 .hw.init = &(struct clk_init_data){ 293 .name = "gsbi1_uart_src", 294 .parent_names = gcc_pxo_pll8, 295 .num_parents = 2, 296 .ops = &clk_rcg_ops, 297 .flags = CLK_SET_PARENT_GATE, 298 }, 299 }, 300}; 301 302static struct clk_branch gsbi1_uart_clk = { 303 .halt_reg = 0x2fcc, 304 .halt_bit = 12, 305 .clkr = { 306 .enable_reg = 0x29d4, 307 .enable_mask = BIT(9), 308 .hw.init = &(struct clk_init_data){ 309 .name = "gsbi1_uart_clk", 310 .parent_names = (const char *[]){ 311 "gsbi1_uart_src", 312 }, 313 .num_parents = 1, 314 .ops = &clk_branch_ops, 315 .flags = CLK_SET_RATE_PARENT, 316 }, 317 }, 318}; 319 320static struct clk_rcg gsbi2_uart_src = { 321 .ns_reg = 0x29f4, 322 .md_reg = 0x29f0, 323 .mn = { 324 .mnctr_en_bit = 8, 325 .mnctr_reset_bit = 7, 326 .mnctr_mode_shift = 5, 327 .n_val_shift = 16, 328 .m_val_shift = 16, 329 .width = 16, 330 }, 331 .p = { 332 .pre_div_shift = 3, 333 .pre_div_width = 2, 334 }, 335 .s = { 336 .src_sel_shift = 0, 337 .parent_map = gcc_pxo_pll8_map, 338 }, 339 .freq_tbl = clk_tbl_gsbi_uart, 340 .clkr = { 341 .enable_reg = 0x29f4, 342 .enable_mask = BIT(11), 343 .hw.init = &(struct clk_init_data){ 344 .name = "gsbi2_uart_src", 345 .parent_names = gcc_pxo_pll8, 346 .num_parents = 2, 347 .ops = &clk_rcg_ops, 348 .flags = CLK_SET_PARENT_GATE, 349 }, 350 }, 351}; 352 353static struct clk_branch gsbi2_uart_clk = { 354 .halt_reg = 0x2fcc, 355 .halt_bit = 8, 356 .clkr = { 357 .enable_reg = 0x29f4, 358 .enable_mask = BIT(9), 359 .hw.init = &(struct clk_init_data){ 360 .name = "gsbi2_uart_clk", 361 .parent_names = (const char *[]){ 362 "gsbi2_uart_src", 363 }, 364 .num_parents = 1, 365 .ops = &clk_branch_ops, 366 .flags = CLK_SET_RATE_PARENT, 367 }, 368 }, 369}; 370 371static struct clk_rcg gsbi4_uart_src = { 372 .ns_reg = 0x2a34, 373 .md_reg = 0x2a30, 374 .mn = { 375 .mnctr_en_bit = 8, 376 .mnctr_reset_bit = 7, 377 .mnctr_mode_shift = 5, 378 .n_val_shift = 16, 379 .m_val_shift = 16, 380 .width = 16, 381 }, 382 .p = { 383 .pre_div_shift = 3, 384 .pre_div_width = 2, 385 }, 386 .s = { 387 .src_sel_shift = 0, 388 .parent_map = gcc_pxo_pll8_map, 389 }, 390 .freq_tbl = clk_tbl_gsbi_uart, 391 .clkr = { 392 .enable_reg = 0x2a34, 393 .enable_mask = BIT(11), 394 .hw.init = &(struct clk_init_data){ 395 .name = "gsbi4_uart_src", 396 .parent_names = gcc_pxo_pll8, 397 .num_parents = 2, 398 .ops = &clk_rcg_ops, 399 .flags = CLK_SET_PARENT_GATE, 400 }, 401 }, 402}; 403 404static struct clk_branch gsbi4_uart_clk = { 405 .halt_reg = 0x2fd0, 406 .halt_bit = 26, 407 .clkr = { 408 .enable_reg = 0x2a34, 409 .enable_mask = BIT(9), 410 .hw.init = &(struct clk_init_data){ 411 .name = "gsbi4_uart_clk", 412 .parent_names = (const char *[]){ 413 "gsbi4_uart_src", 414 }, 415 .num_parents = 1, 416 .ops = &clk_branch_ops, 417 .flags = CLK_SET_RATE_PARENT, 418 }, 419 }, 420}; 421 422static struct clk_rcg gsbi5_uart_src = { 423 .ns_reg = 0x2a54, 424 .md_reg = 0x2a50, 425 .mn = { 426 .mnctr_en_bit = 8, 427 .mnctr_reset_bit = 7, 428 .mnctr_mode_shift = 5, 429 .n_val_shift = 16, 430 .m_val_shift = 16, 431 .width = 16, 432 }, 433 .p = { 434 .pre_div_shift = 3, 435 .pre_div_width = 2, 436 }, 437 .s = { 438 .src_sel_shift = 0, 439 .parent_map = gcc_pxo_pll8_map, 440 }, 441 .freq_tbl = clk_tbl_gsbi_uart, 442 .clkr = { 443 .enable_reg = 0x2a54, 444 .enable_mask = BIT(11), 445 .hw.init = &(struct clk_init_data){ 446 .name = "gsbi5_uart_src", 447 .parent_names = gcc_pxo_pll8, 448 .num_parents = 2, 449 .ops = &clk_rcg_ops, 450 .flags = CLK_SET_PARENT_GATE, 451 }, 452 }, 453}; 454 455static struct clk_branch gsbi5_uart_clk = { 456 .halt_reg = 0x2fd0, 457 .halt_bit = 22, 458 .clkr = { 459 .enable_reg = 0x2a54, 460 .enable_mask = BIT(9), 461 .hw.init = &(struct clk_init_data){ 462 .name = "gsbi5_uart_clk", 463 .parent_names = (const char *[]){ 464 "gsbi5_uart_src", 465 }, 466 .num_parents = 1, 467 .ops = &clk_branch_ops, 468 .flags = CLK_SET_RATE_PARENT, 469 }, 470 }, 471}; 472 473static struct clk_rcg gsbi6_uart_src = { 474 .ns_reg = 0x2a74, 475 .md_reg = 0x2a70, 476 .mn = { 477 .mnctr_en_bit = 8, 478 .mnctr_reset_bit = 7, 479 .mnctr_mode_shift = 5, 480 .n_val_shift = 16, 481 .m_val_shift = 16, 482 .width = 16, 483 }, 484 .p = { 485 .pre_div_shift = 3, 486 .pre_div_width = 2, 487 }, 488 .s = { 489 .src_sel_shift = 0, 490 .parent_map = gcc_pxo_pll8_map, 491 }, 492 .freq_tbl = clk_tbl_gsbi_uart, 493 .clkr = { 494 .enable_reg = 0x2a74, 495 .enable_mask = BIT(11), 496 .hw.init = &(struct clk_init_data){ 497 .name = "gsbi6_uart_src", 498 .parent_names = gcc_pxo_pll8, 499 .num_parents = 2, 500 .ops = &clk_rcg_ops, 501 .flags = CLK_SET_PARENT_GATE, 502 }, 503 }, 504}; 505 506static struct clk_branch gsbi6_uart_clk = { 507 .halt_reg = 0x2fd0, 508 .halt_bit = 18, 509 .clkr = { 510 .enable_reg = 0x2a74, 511 .enable_mask = BIT(9), 512 .hw.init = &(struct clk_init_data){ 513 .name = "gsbi6_uart_clk", 514 .parent_names = (const char *[]){ 515 "gsbi6_uart_src", 516 }, 517 .num_parents = 1, 518 .ops = &clk_branch_ops, 519 .flags = CLK_SET_RATE_PARENT, 520 }, 521 }, 522}; 523 524static struct clk_rcg gsbi7_uart_src = { 525 .ns_reg = 0x2a94, 526 .md_reg = 0x2a90, 527 .mn = { 528 .mnctr_en_bit = 8, 529 .mnctr_reset_bit = 7, 530 .mnctr_mode_shift = 5, 531 .n_val_shift = 16, 532 .m_val_shift = 16, 533 .width = 16, 534 }, 535 .p = { 536 .pre_div_shift = 3, 537 .pre_div_width = 2, 538 }, 539 .s = { 540 .src_sel_shift = 0, 541 .parent_map = gcc_pxo_pll8_map, 542 }, 543 .freq_tbl = clk_tbl_gsbi_uart, 544 .clkr = { 545 .enable_reg = 0x2a94, 546 .enable_mask = BIT(11), 547 .hw.init = &(struct clk_init_data){ 548 .name = "gsbi7_uart_src", 549 .parent_names = gcc_pxo_pll8, 550 .num_parents = 2, 551 .ops = &clk_rcg_ops, 552 .flags = CLK_SET_PARENT_GATE, 553 }, 554 }, 555}; 556 557static struct clk_branch gsbi7_uart_clk = { 558 .halt_reg = 0x2fd0, 559 .halt_bit = 14, 560 .clkr = { 561 .enable_reg = 0x2a94, 562 .enable_mask = BIT(9), 563 .hw.init = &(struct clk_init_data){ 564 .name = "gsbi7_uart_clk", 565 .parent_names = (const char *[]){ 566 "gsbi7_uart_src", 567 }, 568 .num_parents = 1, 569 .ops = &clk_branch_ops, 570 .flags = CLK_SET_RATE_PARENT, 571 }, 572 }, 573}; 574 575static struct freq_tbl clk_tbl_gsbi_qup[] = { 576 { 1100000, P_PXO, 1, 2, 49 }, 577 { 5400000, P_PXO, 1, 1, 5 }, 578 { 10800000, P_PXO, 1, 2, 5 }, 579 { 15060000, P_PLL8, 1, 2, 51 }, 580 { 24000000, P_PLL8, 4, 1, 4 }, 581 { 25000000, P_PXO, 1, 0, 0 }, 582 { 25600000, P_PLL8, 1, 1, 15 }, 583 { 48000000, P_PLL8, 4, 1, 2 }, 584 { 51200000, P_PLL8, 1, 2, 15 }, 585 { } 586}; 587 588static struct clk_rcg gsbi1_qup_src = { 589 .ns_reg = 0x29cc, 590 .md_reg = 0x29c8, 591 .mn = { 592 .mnctr_en_bit = 8, 593 .mnctr_reset_bit = 7, 594 .mnctr_mode_shift = 5, 595 .n_val_shift = 16, 596 .m_val_shift = 16, 597 .width = 8, 598 }, 599 .p = { 600 .pre_div_shift = 3, 601 .pre_div_width = 2, 602 }, 603 .s = { 604 .src_sel_shift = 0, 605 .parent_map = gcc_pxo_pll8_map, 606 }, 607 .freq_tbl = clk_tbl_gsbi_qup, 608 .clkr = { 609 .enable_reg = 0x29cc, 610 .enable_mask = BIT(11), 611 .hw.init = &(struct clk_init_data){ 612 .name = "gsbi1_qup_src", 613 .parent_names = gcc_pxo_pll8, 614 .num_parents = 2, 615 .ops = &clk_rcg_ops, 616 .flags = CLK_SET_PARENT_GATE, 617 }, 618 }, 619}; 620 621static struct clk_branch gsbi1_qup_clk = { 622 .halt_reg = 0x2fcc, 623 .halt_bit = 11, 624 .clkr = { 625 .enable_reg = 0x29cc, 626 .enable_mask = BIT(9), 627 .hw.init = &(struct clk_init_data){ 628 .name = "gsbi1_qup_clk", 629 .parent_names = (const char *[]){ "gsbi1_qup_src" }, 630 .num_parents = 1, 631 .ops = &clk_branch_ops, 632 .flags = CLK_SET_RATE_PARENT, 633 }, 634 }, 635}; 636 637static struct clk_rcg gsbi2_qup_src = { 638 .ns_reg = 0x29ec, 639 .md_reg = 0x29e8, 640 .mn = { 641 .mnctr_en_bit = 8, 642 .mnctr_reset_bit = 7, 643 .mnctr_mode_shift = 5, 644 .n_val_shift = 16, 645 .m_val_shift = 16, 646 .width = 8, 647 }, 648 .p = { 649 .pre_div_shift = 3, 650 .pre_div_width = 2, 651 }, 652 .s = { 653 .src_sel_shift = 0, 654 .parent_map = gcc_pxo_pll8_map, 655 }, 656 .freq_tbl = clk_tbl_gsbi_qup, 657 .clkr = { 658 .enable_reg = 0x29ec, 659 .enable_mask = BIT(11), 660 .hw.init = &(struct clk_init_data){ 661 .name = "gsbi2_qup_src", 662 .parent_names = gcc_pxo_pll8, 663 .num_parents = 2, 664 .ops = &clk_rcg_ops, 665 .flags = CLK_SET_PARENT_GATE, 666 }, 667 }, 668}; 669 670static struct clk_branch gsbi2_qup_clk = { 671 .halt_reg = 0x2fcc, 672 .halt_bit = 6, 673 .clkr = { 674 .enable_reg = 0x29ec, 675 .enable_mask = BIT(9), 676 .hw.init = &(struct clk_init_data){ 677 .name = "gsbi2_qup_clk", 678 .parent_names = (const char *[]){ "gsbi2_qup_src" }, 679 .num_parents = 1, 680 .ops = &clk_branch_ops, 681 .flags = CLK_SET_RATE_PARENT, 682 }, 683 }, 684}; 685 686static struct clk_rcg gsbi4_qup_src = { 687 .ns_reg = 0x2a2c, 688 .md_reg = 0x2a28, 689 .mn = { 690 .mnctr_en_bit = 8, 691 .mnctr_reset_bit = 7, 692 .mnctr_mode_shift = 5, 693 .n_val_shift = 16, 694 .m_val_shift = 16, 695 .width = 8, 696 }, 697 .p = { 698 .pre_div_shift = 3, 699 .pre_div_width = 2, 700 }, 701 .s = { 702 .src_sel_shift = 0, 703 .parent_map = gcc_pxo_pll8_map, 704 }, 705 .freq_tbl = clk_tbl_gsbi_qup, 706 .clkr = { 707 .enable_reg = 0x2a2c, 708 .enable_mask = BIT(11), 709 .hw.init = &(struct clk_init_data){ 710 .name = "gsbi4_qup_src", 711 .parent_names = gcc_pxo_pll8, 712 .num_parents = 2, 713 .ops = &clk_rcg_ops, 714 .flags = CLK_SET_PARENT_GATE, 715 }, 716 }, 717}; 718 719static struct clk_branch gsbi4_qup_clk = { 720 .halt_reg = 0x2fd0, 721 .halt_bit = 24, 722 .clkr = { 723 .enable_reg = 0x2a2c, 724 .enable_mask = BIT(9), 725 .hw.init = &(struct clk_init_data){ 726 .name = "gsbi4_qup_clk", 727 .parent_names = (const char *[]){ "gsbi4_qup_src" }, 728 .num_parents = 1, 729 .ops = &clk_branch_ops, 730 .flags = CLK_SET_RATE_PARENT, 731 }, 732 }, 733}; 734 735static struct clk_rcg gsbi5_qup_src = { 736 .ns_reg = 0x2a4c, 737 .md_reg = 0x2a48, 738 .mn = { 739 .mnctr_en_bit = 8, 740 .mnctr_reset_bit = 7, 741 .mnctr_mode_shift = 5, 742 .n_val_shift = 16, 743 .m_val_shift = 16, 744 .width = 8, 745 }, 746 .p = { 747 .pre_div_shift = 3, 748 .pre_div_width = 2, 749 }, 750 .s = { 751 .src_sel_shift = 0, 752 .parent_map = gcc_pxo_pll8_map, 753 }, 754 .freq_tbl = clk_tbl_gsbi_qup, 755 .clkr = { 756 .enable_reg = 0x2a4c, 757 .enable_mask = BIT(11), 758 .hw.init = &(struct clk_init_data){ 759 .name = "gsbi5_qup_src", 760 .parent_names = gcc_pxo_pll8, 761 .num_parents = 2, 762 .ops = &clk_rcg_ops, 763 .flags = CLK_SET_PARENT_GATE, 764 }, 765 }, 766}; 767 768static struct clk_branch gsbi5_qup_clk = { 769 .halt_reg = 0x2fd0, 770 .halt_bit = 20, 771 .clkr = { 772 .enable_reg = 0x2a4c, 773 .enable_mask = BIT(9), 774 .hw.init = &(struct clk_init_data){ 775 .name = "gsbi5_qup_clk", 776 .parent_names = (const char *[]){ "gsbi5_qup_src" }, 777 .num_parents = 1, 778 .ops = &clk_branch_ops, 779 .flags = CLK_SET_RATE_PARENT, 780 }, 781 }, 782}; 783 784static struct clk_rcg gsbi6_qup_src = { 785 .ns_reg = 0x2a6c, 786 .md_reg = 0x2a68, 787 .mn = { 788 .mnctr_en_bit = 8, 789 .mnctr_reset_bit = 7, 790 .mnctr_mode_shift = 5, 791 .n_val_shift = 16, 792 .m_val_shift = 16, 793 .width = 8, 794 }, 795 .p = { 796 .pre_div_shift = 3, 797 .pre_div_width = 2, 798 }, 799 .s = { 800 .src_sel_shift = 0, 801 .parent_map = gcc_pxo_pll8_map, 802 }, 803 .freq_tbl = clk_tbl_gsbi_qup, 804 .clkr = { 805 .enable_reg = 0x2a6c, 806 .enable_mask = BIT(11), 807 .hw.init = &(struct clk_init_data){ 808 .name = "gsbi6_qup_src", 809 .parent_names = gcc_pxo_pll8, 810 .num_parents = 2, 811 .ops = &clk_rcg_ops, 812 .flags = CLK_SET_PARENT_GATE, 813 }, 814 }, 815}; 816 817static struct clk_branch gsbi6_qup_clk = { 818 .halt_reg = 0x2fd0, 819 .halt_bit = 16, 820 .clkr = { 821 .enable_reg = 0x2a6c, 822 .enable_mask = BIT(9), 823 .hw.init = &(struct clk_init_data){ 824 .name = "gsbi6_qup_clk", 825 .parent_names = (const char *[]){ "gsbi6_qup_src" }, 826 .num_parents = 1, 827 .ops = &clk_branch_ops, 828 .flags = CLK_SET_RATE_PARENT, 829 }, 830 }, 831}; 832 833static struct clk_rcg gsbi7_qup_src = { 834 .ns_reg = 0x2a8c, 835 .md_reg = 0x2a88, 836 .mn = { 837 .mnctr_en_bit = 8, 838 .mnctr_reset_bit = 7, 839 .mnctr_mode_shift = 5, 840 .n_val_shift = 16, 841 .m_val_shift = 16, 842 .width = 8, 843 }, 844 .p = { 845 .pre_div_shift = 3, 846 .pre_div_width = 2, 847 }, 848 .s = { 849 .src_sel_shift = 0, 850 .parent_map = gcc_pxo_pll8_map, 851 }, 852 .freq_tbl = clk_tbl_gsbi_qup, 853 .clkr = { 854 .enable_reg = 0x2a8c, 855 .enable_mask = BIT(11), 856 .hw.init = &(struct clk_init_data){ 857 .name = "gsbi7_qup_src", 858 .parent_names = gcc_pxo_pll8, 859 .num_parents = 2, 860 .ops = &clk_rcg_ops, 861 .flags = CLK_SET_PARENT_GATE, 862 }, 863 }, 864}; 865 866static struct clk_branch gsbi7_qup_clk = { 867 .halt_reg = 0x2fd0, 868 .halt_bit = 12, 869 .clkr = { 870 .enable_reg = 0x2a8c, 871 .enable_mask = BIT(9), 872 .hw.init = &(struct clk_init_data){ 873 .name = "gsbi7_qup_clk", 874 .parent_names = (const char *[]){ "gsbi7_qup_src" }, 875 .num_parents = 1, 876 .ops = &clk_branch_ops, 877 .flags = CLK_SET_RATE_PARENT, 878 }, 879 }, 880}; 881 882static struct clk_branch gsbi1_h_clk = { 883 .hwcg_reg = 0x29c0, 884 .hwcg_bit = 6, 885 .halt_reg = 0x2fcc, 886 .halt_bit = 13, 887 .clkr = { 888 .enable_reg = 0x29c0, 889 .enable_mask = BIT(4), 890 .hw.init = &(struct clk_init_data){ 891 .name = "gsbi1_h_clk", 892 .ops = &clk_branch_ops, 893 .flags = CLK_IS_ROOT, 894 }, 895 }, 896}; 897 898static struct clk_branch gsbi2_h_clk = { 899 .hwcg_reg = 0x29e0, 900 .hwcg_bit = 6, 901 .halt_reg = 0x2fcc, 902 .halt_bit = 9, 903 .clkr = { 904 .enable_reg = 0x29e0, 905 .enable_mask = BIT(4), 906 .hw.init = &(struct clk_init_data){ 907 .name = "gsbi2_h_clk", 908 .ops = &clk_branch_ops, 909 .flags = CLK_IS_ROOT, 910 }, 911 }, 912}; 913 914static struct clk_branch gsbi4_h_clk = { 915 .hwcg_reg = 0x2a20, 916 .hwcg_bit = 6, 917 .halt_reg = 0x2fd0, 918 .halt_bit = 27, 919 .clkr = { 920 .enable_reg = 0x2a20, 921 .enable_mask = BIT(4), 922 .hw.init = &(struct clk_init_data){ 923 .name = "gsbi4_h_clk", 924 .ops = &clk_branch_ops, 925 .flags = CLK_IS_ROOT, 926 }, 927 }, 928}; 929 930static struct clk_branch gsbi5_h_clk = { 931 .hwcg_reg = 0x2a40, 932 .hwcg_bit = 6, 933 .halt_reg = 0x2fd0, 934 .halt_bit = 23, 935 .clkr = { 936 .enable_reg = 0x2a40, 937 .enable_mask = BIT(4), 938 .hw.init = &(struct clk_init_data){ 939 .name = "gsbi5_h_clk", 940 .ops = &clk_branch_ops, 941 .flags = CLK_IS_ROOT, 942 }, 943 }, 944}; 945 946static struct clk_branch gsbi6_h_clk = { 947 .hwcg_reg = 0x2a60, 948 .hwcg_bit = 6, 949 .halt_reg = 0x2fd0, 950 .halt_bit = 19, 951 .clkr = { 952 .enable_reg = 0x2a60, 953 .enable_mask = BIT(4), 954 .hw.init = &(struct clk_init_data){ 955 .name = "gsbi6_h_clk", 956 .ops = &clk_branch_ops, 957 .flags = CLK_IS_ROOT, 958 }, 959 }, 960}; 961 962static struct clk_branch gsbi7_h_clk = { 963 .hwcg_reg = 0x2a80, 964 .hwcg_bit = 6, 965 .halt_reg = 0x2fd0, 966 .halt_bit = 15, 967 .clkr = { 968 .enable_reg = 0x2a80, 969 .enable_mask = BIT(4), 970 .hw.init = &(struct clk_init_data){ 971 .name = "gsbi7_h_clk", 972 .ops = &clk_branch_ops, 973 .flags = CLK_IS_ROOT, 974 }, 975 }, 976}; 977 978static const struct freq_tbl clk_tbl_gp[] = { 979 { 12500000, P_PXO, 2, 0, 0 }, 980 { 25000000, P_PXO, 1, 0, 0 }, 981 { 64000000, P_PLL8, 2, 1, 3 }, 982 { 76800000, P_PLL8, 1, 1, 5 }, 983 { 96000000, P_PLL8, 4, 0, 0 }, 984 { 128000000, P_PLL8, 3, 0, 0 }, 985 { 192000000, P_PLL8, 2, 0, 0 }, 986 { } 987}; 988 989static struct clk_rcg gp0_src = { 990 .ns_reg = 0x2d24, 991 .md_reg = 0x2d00, 992 .mn = { 993 .mnctr_en_bit = 8, 994 .mnctr_reset_bit = 7, 995 .mnctr_mode_shift = 5, 996 .n_val_shift = 16, 997 .m_val_shift = 16, 998 .width = 8, 999 }, 1000 .p = { 1001 .pre_div_shift = 3, 1002 .pre_div_width = 2, 1003 }, 1004 .s = { 1005 .src_sel_shift = 0, 1006 .parent_map = gcc_pxo_pll8_cxo_map, 1007 }, 1008 .freq_tbl = clk_tbl_gp, 1009 .clkr = { 1010 .enable_reg = 0x2d24, 1011 .enable_mask = BIT(11), 1012 .hw.init = &(struct clk_init_data){ 1013 .name = "gp0_src", 1014 .parent_names = gcc_pxo_pll8_cxo, 1015 .num_parents = 3, 1016 .ops = &clk_rcg_ops, 1017 .flags = CLK_SET_PARENT_GATE, 1018 }, 1019 } 1020}; 1021 1022static struct clk_branch gp0_clk = { 1023 .halt_reg = 0x2fd8, 1024 .halt_bit = 7, 1025 .clkr = { 1026 .enable_reg = 0x2d24, 1027 .enable_mask = BIT(9), 1028 .hw.init = &(struct clk_init_data){ 1029 .name = "gp0_clk", 1030 .parent_names = (const char *[]){ "gp0_src" }, 1031 .num_parents = 1, 1032 .ops = &clk_branch_ops, 1033 .flags = CLK_SET_RATE_PARENT, 1034 }, 1035 }, 1036}; 1037 1038static struct clk_rcg gp1_src = { 1039 .ns_reg = 0x2d44, 1040 .md_reg = 0x2d40, 1041 .mn = { 1042 .mnctr_en_bit = 8, 1043 .mnctr_reset_bit = 7, 1044 .mnctr_mode_shift = 5, 1045 .n_val_shift = 16, 1046 .m_val_shift = 16, 1047 .width = 8, 1048 }, 1049 .p = { 1050 .pre_div_shift = 3, 1051 .pre_div_width = 2, 1052 }, 1053 .s = { 1054 .src_sel_shift = 0, 1055 .parent_map = gcc_pxo_pll8_cxo_map, 1056 }, 1057 .freq_tbl = clk_tbl_gp, 1058 .clkr = { 1059 .enable_reg = 0x2d44, 1060 .enable_mask = BIT(11), 1061 .hw.init = &(struct clk_init_data){ 1062 .name = "gp1_src", 1063 .parent_names = gcc_pxo_pll8_cxo, 1064 .num_parents = 3, 1065 .ops = &clk_rcg_ops, 1066 .flags = CLK_SET_RATE_GATE, 1067 }, 1068 } 1069}; 1070 1071static struct clk_branch gp1_clk = { 1072 .halt_reg = 0x2fd8, 1073 .halt_bit = 6, 1074 .clkr = { 1075 .enable_reg = 0x2d44, 1076 .enable_mask = BIT(9), 1077 .hw.init = &(struct clk_init_data){ 1078 .name = "gp1_clk", 1079 .parent_names = (const char *[]){ "gp1_src" }, 1080 .num_parents = 1, 1081 .ops = &clk_branch_ops, 1082 .flags = CLK_SET_RATE_PARENT, 1083 }, 1084 }, 1085}; 1086 1087static struct clk_rcg gp2_src = { 1088 .ns_reg = 0x2d64, 1089 .md_reg = 0x2d60, 1090 .mn = { 1091 .mnctr_en_bit = 8, 1092 .mnctr_reset_bit = 7, 1093 .mnctr_mode_shift = 5, 1094 .n_val_shift = 16, 1095 .m_val_shift = 16, 1096 .width = 8, 1097 }, 1098 .p = { 1099 .pre_div_shift = 3, 1100 .pre_div_width = 2, 1101 }, 1102 .s = { 1103 .src_sel_shift = 0, 1104 .parent_map = gcc_pxo_pll8_cxo_map, 1105 }, 1106 .freq_tbl = clk_tbl_gp, 1107 .clkr = { 1108 .enable_reg = 0x2d64, 1109 .enable_mask = BIT(11), 1110 .hw.init = &(struct clk_init_data){ 1111 .name = "gp2_src", 1112 .parent_names = gcc_pxo_pll8_cxo, 1113 .num_parents = 3, 1114 .ops = &clk_rcg_ops, 1115 .flags = CLK_SET_RATE_GATE, 1116 }, 1117 } 1118}; 1119 1120static struct clk_branch gp2_clk = { 1121 .halt_reg = 0x2fd8, 1122 .halt_bit = 5, 1123 .clkr = { 1124 .enable_reg = 0x2d64, 1125 .enable_mask = BIT(9), 1126 .hw.init = &(struct clk_init_data){ 1127 .name = "gp2_clk", 1128 .parent_names = (const char *[]){ "gp2_src" }, 1129 .num_parents = 1, 1130 .ops = &clk_branch_ops, 1131 .flags = CLK_SET_RATE_PARENT, 1132 }, 1133 }, 1134}; 1135 1136static struct clk_branch pmem_clk = { 1137 .hwcg_reg = 0x25a0, 1138 .hwcg_bit = 6, 1139 .halt_reg = 0x2fc8, 1140 .halt_bit = 20, 1141 .clkr = { 1142 .enable_reg = 0x25a0, 1143 .enable_mask = BIT(4), 1144 .hw.init = &(struct clk_init_data){ 1145 .name = "pmem_clk", 1146 .ops = &clk_branch_ops, 1147 .flags = CLK_IS_ROOT, 1148 }, 1149 }, 1150}; 1151 1152static struct clk_rcg prng_src = { 1153 .ns_reg = 0x2e80, 1154 .p = { 1155 .pre_div_shift = 3, 1156 .pre_div_width = 4, 1157 }, 1158 .s = { 1159 .src_sel_shift = 0, 1160 .parent_map = gcc_pxo_pll8_map, 1161 }, 1162 .clkr = { 1163 .hw.init = &(struct clk_init_data){ 1164 .name = "prng_src", 1165 .parent_names = gcc_pxo_pll8, 1166 .num_parents = 2, 1167 .ops = &clk_rcg_ops, 1168 }, 1169 }, 1170}; 1171 1172static struct clk_branch prng_clk = { 1173 .halt_reg = 0x2fd8, 1174 .halt_check = BRANCH_HALT_VOTED, 1175 .halt_bit = 10, 1176 .clkr = { 1177 .enable_reg = 0x3080, 1178 .enable_mask = BIT(10), 1179 .hw.init = &(struct clk_init_data){ 1180 .name = "prng_clk", 1181 .parent_names = (const char *[]){ "prng_src" }, 1182 .num_parents = 1, 1183 .ops = &clk_branch_ops, 1184 }, 1185 }, 1186}; 1187 1188static const struct freq_tbl clk_tbl_sdc[] = { 1189 { 200000, P_PXO, 2, 2, 125 }, 1190 { 400000, P_PLL8, 4, 1, 240 }, 1191 { 16000000, P_PLL8, 4, 1, 6 }, 1192 { 17070000, P_PLL8, 1, 2, 45 }, 1193 { 20210000, P_PLL8, 1, 1, 19 }, 1194 { 24000000, P_PLL8, 4, 1, 4 }, 1195 { 48000000, P_PLL8, 4, 1, 2 }, 1196 { 64000000, P_PLL8, 3, 1, 2 }, 1197 { 96000000, P_PLL8, 4, 0, 0 }, 1198 { 192000000, P_PLL8, 2, 0, 0 }, 1199 { } 1200}; 1201 1202static struct clk_rcg sdc1_src = { 1203 .ns_reg = 0x282c, 1204 .md_reg = 0x2828, 1205 .mn = { 1206 .mnctr_en_bit = 8, 1207 .mnctr_reset_bit = 7, 1208 .mnctr_mode_shift = 5, 1209 .n_val_shift = 16, 1210 .m_val_shift = 16, 1211 .width = 8, 1212 }, 1213 .p = { 1214 .pre_div_shift = 3, 1215 .pre_div_width = 2, 1216 }, 1217 .s = { 1218 .src_sel_shift = 0, 1219 .parent_map = gcc_pxo_pll8_map, 1220 }, 1221 .freq_tbl = clk_tbl_sdc, 1222 .clkr = { 1223 .enable_reg = 0x282c, 1224 .enable_mask = BIT(11), 1225 .hw.init = &(struct clk_init_data){ 1226 .name = "sdc1_src", 1227 .parent_names = gcc_pxo_pll8, 1228 .num_parents = 2, 1229 .ops = &clk_rcg_ops, 1230 .flags = CLK_SET_RATE_GATE, 1231 }, 1232 } 1233}; 1234 1235static struct clk_branch sdc1_clk = { 1236 .halt_reg = 0x2fc8, 1237 .halt_bit = 6, 1238 .clkr = { 1239 .enable_reg = 0x282c, 1240 .enable_mask = BIT(9), 1241 .hw.init = &(struct clk_init_data){ 1242 .name = "sdc1_clk", 1243 .parent_names = (const char *[]){ "sdc1_src" }, 1244 .num_parents = 1, 1245 .ops = &clk_branch_ops, 1246 .flags = CLK_SET_RATE_PARENT, 1247 }, 1248 }, 1249}; 1250 1251static struct clk_rcg sdc3_src = { 1252 .ns_reg = 0x286c, 1253 .md_reg = 0x2868, 1254 .mn = { 1255 .mnctr_en_bit = 8, 1256 .mnctr_reset_bit = 7, 1257 .mnctr_mode_shift = 5, 1258 .n_val_shift = 16, 1259 .m_val_shift = 16, 1260 .width = 8, 1261 }, 1262 .p = { 1263 .pre_div_shift = 3, 1264 .pre_div_width = 2, 1265 }, 1266 .s = { 1267 .src_sel_shift = 0, 1268 .parent_map = gcc_pxo_pll8_map, 1269 }, 1270 .freq_tbl = clk_tbl_sdc, 1271 .clkr = { 1272 .enable_reg = 0x286c, 1273 .enable_mask = BIT(11), 1274 .hw.init = &(struct clk_init_data){ 1275 .name = "sdc3_src", 1276 .parent_names = gcc_pxo_pll8, 1277 .num_parents = 2, 1278 .ops = &clk_rcg_ops, 1279 .flags = CLK_SET_RATE_GATE, 1280 }, 1281 } 1282}; 1283 1284static struct clk_branch sdc3_clk = { 1285 .halt_reg = 0x2fc8, 1286 .halt_bit = 4, 1287 .clkr = { 1288 .enable_reg = 0x286c, 1289 .enable_mask = BIT(9), 1290 .hw.init = &(struct clk_init_data){ 1291 .name = "sdc3_clk", 1292 .parent_names = (const char *[]){ "sdc3_src" }, 1293 .num_parents = 1, 1294 .ops = &clk_branch_ops, 1295 .flags = CLK_SET_RATE_PARENT, 1296 }, 1297 }, 1298}; 1299 1300static struct clk_branch sdc1_h_clk = { 1301 .hwcg_reg = 0x2820, 1302 .hwcg_bit = 6, 1303 .halt_reg = 0x2fc8, 1304 .halt_bit = 11, 1305 .clkr = { 1306 .enable_reg = 0x2820, 1307 .enable_mask = BIT(4), 1308 .hw.init = &(struct clk_init_data){ 1309 .name = "sdc1_h_clk", 1310 .ops = &clk_branch_ops, 1311 .flags = CLK_IS_ROOT, 1312 }, 1313 }, 1314}; 1315 1316static struct clk_branch sdc3_h_clk = { 1317 .hwcg_reg = 0x2860, 1318 .hwcg_bit = 6, 1319 .halt_reg = 0x2fc8, 1320 .halt_bit = 9, 1321 .clkr = { 1322 .enable_reg = 0x2860, 1323 .enable_mask = BIT(4), 1324 .hw.init = &(struct clk_init_data){ 1325 .name = "sdc3_h_clk", 1326 .ops = &clk_branch_ops, 1327 .flags = CLK_IS_ROOT, 1328 }, 1329 }, 1330}; 1331 1332static const struct freq_tbl clk_tbl_tsif_ref[] = { 1333 { 105000, P_PXO, 1, 1, 256 }, 1334 { } 1335}; 1336 1337static struct clk_rcg tsif_ref_src = { 1338 .ns_reg = 0x2710, 1339 .md_reg = 0x270c, 1340 .mn = { 1341 .mnctr_en_bit = 8, 1342 .mnctr_reset_bit = 7, 1343 .mnctr_mode_shift = 5, 1344 .n_val_shift = 16, 1345 .m_val_shift = 16, 1346 .width = 16, 1347 }, 1348 .p = { 1349 .pre_div_shift = 3, 1350 .pre_div_width = 2, 1351 }, 1352 .s = { 1353 .src_sel_shift = 0, 1354 .parent_map = gcc_pxo_pll8_map, 1355 }, 1356 .freq_tbl = clk_tbl_tsif_ref, 1357 .clkr = { 1358 .enable_reg = 0x2710, 1359 .enable_mask = BIT(11), 1360 .hw.init = &(struct clk_init_data){ 1361 .name = "tsif_ref_src", 1362 .parent_names = gcc_pxo_pll8, 1363 .num_parents = 2, 1364 .ops = &clk_rcg_ops, 1365 .flags = CLK_SET_RATE_GATE, 1366 }, 1367 } 1368}; 1369 1370static struct clk_branch tsif_ref_clk = { 1371 .halt_reg = 0x2fd4, 1372 .halt_bit = 5, 1373 .clkr = { 1374 .enable_reg = 0x2710, 1375 .enable_mask = BIT(9), 1376 .hw.init = &(struct clk_init_data){ 1377 .name = "tsif_ref_clk", 1378 .parent_names = (const char *[]){ "tsif_ref_src" }, 1379 .num_parents = 1, 1380 .ops = &clk_branch_ops, 1381 .flags = CLK_SET_RATE_PARENT, 1382 }, 1383 }, 1384}; 1385 1386static struct clk_branch tsif_h_clk = { 1387 .hwcg_reg = 0x2700, 1388 .hwcg_bit = 6, 1389 .halt_reg = 0x2fd4, 1390 .halt_bit = 7, 1391 .clkr = { 1392 .enable_reg = 0x2700, 1393 .enable_mask = BIT(4), 1394 .hw.init = &(struct clk_init_data){ 1395 .name = "tsif_h_clk", 1396 .ops = &clk_branch_ops, 1397 .flags = CLK_IS_ROOT, 1398 }, 1399 }, 1400}; 1401 1402static struct clk_branch dma_bam_h_clk = { 1403 .hwcg_reg = 0x25c0, 1404 .hwcg_bit = 6, 1405 .halt_reg = 0x2fc8, 1406 .halt_bit = 12, 1407 .clkr = { 1408 .enable_reg = 0x25c0, 1409 .enable_mask = BIT(4), 1410 .hw.init = &(struct clk_init_data){ 1411 .name = "dma_bam_h_clk", 1412 .ops = &clk_branch_ops, 1413 .flags = CLK_IS_ROOT, 1414 }, 1415 }, 1416}; 1417 1418static struct clk_branch adm0_clk = { 1419 .halt_reg = 0x2fdc, 1420 .halt_check = BRANCH_HALT_VOTED, 1421 .halt_bit = 12, 1422 .clkr = { 1423 .enable_reg = 0x3080, 1424 .enable_mask = BIT(2), 1425 .hw.init = &(struct clk_init_data){ 1426 .name = "adm0_clk", 1427 .ops = &clk_branch_ops, 1428 .flags = CLK_IS_ROOT, 1429 }, 1430 }, 1431}; 1432 1433static struct clk_branch adm0_pbus_clk = { 1434 .hwcg_reg = 0x2208, 1435 .hwcg_bit = 6, 1436 .halt_reg = 0x2fdc, 1437 .halt_check = BRANCH_HALT_VOTED, 1438 .halt_bit = 11, 1439 .clkr = { 1440 .enable_reg = 0x3080, 1441 .enable_mask = BIT(3), 1442 .hw.init = &(struct clk_init_data){ 1443 .name = "adm0_pbus_clk", 1444 .ops = &clk_branch_ops, 1445 .flags = CLK_IS_ROOT, 1446 }, 1447 }, 1448}; 1449 1450static struct clk_branch pmic_arb0_h_clk = { 1451 .halt_reg = 0x2fd8, 1452 .halt_check = BRANCH_HALT_VOTED, 1453 .halt_bit = 22, 1454 .clkr = { 1455 .enable_reg = 0x3080, 1456 .enable_mask = BIT(8), 1457 .hw.init = &(struct clk_init_data){ 1458 .name = "pmic_arb0_h_clk", 1459 .ops = &clk_branch_ops, 1460 .flags = CLK_IS_ROOT, 1461 }, 1462 }, 1463}; 1464 1465static struct clk_branch pmic_arb1_h_clk = { 1466 .halt_reg = 0x2fd8, 1467 .halt_check = BRANCH_HALT_VOTED, 1468 .halt_bit = 21, 1469 .clkr = { 1470 .enable_reg = 0x3080, 1471 .enable_mask = BIT(9), 1472 .hw.init = &(struct clk_init_data){ 1473 .name = "pmic_arb1_h_clk", 1474 .ops = &clk_branch_ops, 1475 .flags = CLK_IS_ROOT, 1476 }, 1477 }, 1478}; 1479 1480static struct clk_branch pmic_ssbi2_clk = { 1481 .halt_reg = 0x2fd8, 1482 .halt_check = BRANCH_HALT_VOTED, 1483 .halt_bit = 23, 1484 .clkr = { 1485 .enable_reg = 0x3080, 1486 .enable_mask = BIT(7), 1487 .hw.init = &(struct clk_init_data){ 1488 .name = "pmic_ssbi2_clk", 1489 .ops = &clk_branch_ops, 1490 .flags = CLK_IS_ROOT, 1491 }, 1492 }, 1493}; 1494 1495static struct clk_branch rpm_msg_ram_h_clk = { 1496 .hwcg_reg = 0x27e0, 1497 .hwcg_bit = 6, 1498 .halt_reg = 0x2fd8, 1499 .halt_check = BRANCH_HALT_VOTED, 1500 .halt_bit = 12, 1501 .clkr = { 1502 .enable_reg = 0x3080, 1503 .enable_mask = BIT(6), 1504 .hw.init = &(struct clk_init_data){ 1505 .name = "rpm_msg_ram_h_clk", 1506 .ops = &clk_branch_ops, 1507 .flags = CLK_IS_ROOT, 1508 }, 1509 }, 1510}; 1511 1512static const struct freq_tbl clk_tbl_pcie_ref[] = { 1513 { 100000000, P_PLL3, 12, 0, 0 }, 1514 { } 1515}; 1516 1517static struct clk_rcg pcie_ref_src = { 1518 .ns_reg = 0x3860, 1519 .p = { 1520 .pre_div_shift = 3, 1521 .pre_div_width = 4, 1522 }, 1523 .s = { 1524 .src_sel_shift = 0, 1525 .parent_map = gcc_pxo_pll3_map, 1526 }, 1527 .freq_tbl = clk_tbl_pcie_ref, 1528 .clkr = { 1529 .enable_reg = 0x3860, 1530 .enable_mask = BIT(11), 1531 .hw.init = &(struct clk_init_data){ 1532 .name = "pcie_ref_src", 1533 .parent_names = gcc_pxo_pll3, 1534 .num_parents = 2, 1535 .ops = &clk_rcg_ops, 1536 .flags = CLK_SET_RATE_GATE, 1537 }, 1538 }, 1539}; 1540 1541static struct clk_branch pcie_ref_src_clk = { 1542 .halt_reg = 0x2fdc, 1543 .halt_bit = 30, 1544 .clkr = { 1545 .enable_reg = 0x3860, 1546 .enable_mask = BIT(9), 1547 .hw.init = &(struct clk_init_data){ 1548 .name = "pcie_ref_src_clk", 1549 .parent_names = (const char *[]){ "pcie_ref_src" }, 1550 .num_parents = 1, 1551 .ops = &clk_branch_ops, 1552 .flags = CLK_SET_RATE_PARENT, 1553 }, 1554 }, 1555}; 1556 1557static struct clk_branch pcie_a_clk = { 1558 .halt_reg = 0x2fc0, 1559 .halt_bit = 13, 1560 .clkr = { 1561 .enable_reg = 0x22c0, 1562 .enable_mask = BIT(4), 1563 .hw.init = &(struct clk_init_data){ 1564 .name = "pcie_a_clk", 1565 .ops = &clk_branch_ops, 1566 .flags = CLK_IS_ROOT, 1567 }, 1568 }, 1569}; 1570 1571static struct clk_branch pcie_aux_clk = { 1572 .halt_reg = 0x2fdc, 1573 .halt_bit = 31, 1574 .clkr = { 1575 .enable_reg = 0x22c8, 1576 .enable_mask = BIT(4), 1577 .hw.init = &(struct clk_init_data){ 1578 .name = "pcie_aux_clk", 1579 .ops = &clk_branch_ops, 1580 .flags = CLK_IS_ROOT, 1581 }, 1582 }, 1583}; 1584 1585static struct clk_branch pcie_h_clk = { 1586 .halt_reg = 0x2fd4, 1587 .halt_bit = 8, 1588 .clkr = { 1589 .enable_reg = 0x22cc, 1590 .enable_mask = BIT(4), 1591 .hw.init = &(struct clk_init_data){ 1592 .name = "pcie_h_clk", 1593 .ops = &clk_branch_ops, 1594 .flags = CLK_IS_ROOT, 1595 }, 1596 }, 1597}; 1598 1599static struct clk_branch pcie_phy_clk = { 1600 .halt_reg = 0x2fdc, 1601 .halt_bit = 29, 1602 .clkr = { 1603 .enable_reg = 0x22d0, 1604 .enable_mask = BIT(4), 1605 .hw.init = &(struct clk_init_data){ 1606 .name = "pcie_phy_clk", 1607 .ops = &clk_branch_ops, 1608 .flags = CLK_IS_ROOT, 1609 }, 1610 }, 1611}; 1612 1613static struct clk_rcg pcie1_ref_src = { 1614 .ns_reg = 0x3aa0, 1615 .p = { 1616 .pre_div_shift = 3, 1617 .pre_div_width = 4, 1618 }, 1619 .s = { 1620 .src_sel_shift = 0, 1621 .parent_map = gcc_pxo_pll3_map, 1622 }, 1623 .freq_tbl = clk_tbl_pcie_ref, 1624 .clkr = { 1625 .enable_reg = 0x3aa0, 1626 .enable_mask = BIT(11), 1627 .hw.init = &(struct clk_init_data){ 1628 .name = "pcie1_ref_src", 1629 .parent_names = gcc_pxo_pll3, 1630 .num_parents = 2, 1631 .ops = &clk_rcg_ops, 1632 .flags = CLK_SET_RATE_GATE, 1633 }, 1634 }, 1635}; 1636 1637static struct clk_branch pcie1_ref_src_clk = { 1638 .halt_reg = 0x2fdc, 1639 .halt_bit = 27, 1640 .clkr = { 1641 .enable_reg = 0x3aa0, 1642 .enable_mask = BIT(9), 1643 .hw.init = &(struct clk_init_data){ 1644 .name = "pcie1_ref_src_clk", 1645 .parent_names = (const char *[]){ "pcie1_ref_src" }, 1646 .num_parents = 1, 1647 .ops = &clk_branch_ops, 1648 .flags = CLK_SET_RATE_PARENT, 1649 }, 1650 }, 1651}; 1652 1653static struct clk_branch pcie1_a_clk = { 1654 .halt_reg = 0x2fc0, 1655 .halt_bit = 10, 1656 .clkr = { 1657 .enable_reg = 0x3a80, 1658 .enable_mask = BIT(4), 1659 .hw.init = &(struct clk_init_data){ 1660 .name = "pcie1_a_clk", 1661 .ops = &clk_branch_ops, 1662 .flags = CLK_IS_ROOT, 1663 }, 1664 }, 1665}; 1666 1667static struct clk_branch pcie1_aux_clk = { 1668 .halt_reg = 0x2fdc, 1669 .halt_bit = 28, 1670 .clkr = { 1671 .enable_reg = 0x3a88, 1672 .enable_mask = BIT(4), 1673 .hw.init = &(struct clk_init_data){ 1674 .name = "pcie1_aux_clk", 1675 .ops = &clk_branch_ops, 1676 .flags = CLK_IS_ROOT, 1677 }, 1678 }, 1679}; 1680 1681static struct clk_branch pcie1_h_clk = { 1682 .halt_reg = 0x2fd4, 1683 .halt_bit = 9, 1684 .clkr = { 1685 .enable_reg = 0x3a8c, 1686 .enable_mask = BIT(4), 1687 .hw.init = &(struct clk_init_data){ 1688 .name = "pcie1_h_clk", 1689 .ops = &clk_branch_ops, 1690 .flags = CLK_IS_ROOT, 1691 }, 1692 }, 1693}; 1694 1695static struct clk_branch pcie1_phy_clk = { 1696 .halt_reg = 0x2fdc, 1697 .halt_bit = 26, 1698 .clkr = { 1699 .enable_reg = 0x3a90, 1700 .enable_mask = BIT(4), 1701 .hw.init = &(struct clk_init_data){ 1702 .name = "pcie1_phy_clk", 1703 .ops = &clk_branch_ops, 1704 .flags = CLK_IS_ROOT, 1705 }, 1706 }, 1707}; 1708 1709static struct clk_rcg pcie2_ref_src = { 1710 .ns_reg = 0x3ae0, 1711 .p = { 1712 .pre_div_shift = 3, 1713 .pre_div_width = 4, 1714 }, 1715 .s = { 1716 .src_sel_shift = 0, 1717 .parent_map = gcc_pxo_pll3_map, 1718 }, 1719 .freq_tbl = clk_tbl_pcie_ref, 1720 .clkr = { 1721 .enable_reg = 0x3ae0, 1722 .enable_mask = BIT(11), 1723 .hw.init = &(struct clk_init_data){ 1724 .name = "pcie2_ref_src", 1725 .parent_names = gcc_pxo_pll3, 1726 .num_parents = 2, 1727 .ops = &clk_rcg_ops, 1728 .flags = CLK_SET_RATE_GATE, 1729 }, 1730 }, 1731}; 1732 1733static struct clk_branch pcie2_ref_src_clk = { 1734 .halt_reg = 0x2fdc, 1735 .halt_bit = 24, 1736 .clkr = { 1737 .enable_reg = 0x3ae0, 1738 .enable_mask = BIT(9), 1739 .hw.init = &(struct clk_init_data){ 1740 .name = "pcie2_ref_src_clk", 1741 .parent_names = (const char *[]){ "pcie2_ref_src" }, 1742 .num_parents = 1, 1743 .ops = &clk_branch_ops, 1744 .flags = CLK_SET_RATE_PARENT, 1745 }, 1746 }, 1747}; 1748 1749static struct clk_branch pcie2_a_clk = { 1750 .halt_reg = 0x2fc0, 1751 .halt_bit = 9, 1752 .clkr = { 1753 .enable_reg = 0x3ac0, 1754 .enable_mask = BIT(4), 1755 .hw.init = &(struct clk_init_data){ 1756 .name = "pcie2_a_clk", 1757 .ops = &clk_branch_ops, 1758 .flags = CLK_IS_ROOT, 1759 }, 1760 }, 1761}; 1762 1763static struct clk_branch pcie2_aux_clk = { 1764 .halt_reg = 0x2fdc, 1765 .halt_bit = 25, 1766 .clkr = { 1767 .enable_reg = 0x3ac8, 1768 .enable_mask = BIT(4), 1769 .hw.init = &(struct clk_init_data){ 1770 .name = "pcie2_aux_clk", 1771 .ops = &clk_branch_ops, 1772 .flags = CLK_IS_ROOT, 1773 }, 1774 }, 1775}; 1776 1777static struct clk_branch pcie2_h_clk = { 1778 .halt_reg = 0x2fd4, 1779 .halt_bit = 10, 1780 .clkr = { 1781 .enable_reg = 0x3acc, 1782 .enable_mask = BIT(4), 1783 .hw.init = &(struct clk_init_data){ 1784 .name = "pcie2_h_clk", 1785 .ops = &clk_branch_ops, 1786 .flags = CLK_IS_ROOT, 1787 }, 1788 }, 1789}; 1790 1791static struct clk_branch pcie2_phy_clk = { 1792 .halt_reg = 0x2fdc, 1793 .halt_bit = 23, 1794 .clkr = { 1795 .enable_reg = 0x3ad0, 1796 .enable_mask = BIT(4), 1797 .hw.init = &(struct clk_init_data){ 1798 .name = "pcie2_phy_clk", 1799 .ops = &clk_branch_ops, 1800 .flags = CLK_IS_ROOT, 1801 }, 1802 }, 1803}; 1804 1805static const struct freq_tbl clk_tbl_sata_ref[] = { 1806 { 100000000, P_PLL3, 12, 0, 0 }, 1807 { } 1808}; 1809 1810static struct clk_rcg sata_ref_src = { 1811 .ns_reg = 0x2c08, 1812 .p = { 1813 .pre_div_shift = 3, 1814 .pre_div_width = 4, 1815 }, 1816 .s = { 1817 .src_sel_shift = 0, 1818 .parent_map = gcc_pxo_pll3_sata_map, 1819 }, 1820 .freq_tbl = clk_tbl_sata_ref, 1821 .clkr = { 1822 .enable_reg = 0x2c08, 1823 .enable_mask = BIT(7), 1824 .hw.init = &(struct clk_init_data){ 1825 .name = "sata_ref_src", 1826 .parent_names = gcc_pxo_pll3, 1827 .num_parents = 2, 1828 .ops = &clk_rcg_ops, 1829 .flags = CLK_SET_RATE_GATE, 1830 }, 1831 }, 1832}; 1833 1834static struct clk_branch sata_rxoob_clk = { 1835 .halt_reg = 0x2fdc, 1836 .halt_bit = 20, 1837 .clkr = { 1838 .enable_reg = 0x2c0c, 1839 .enable_mask = BIT(4), 1840 .hw.init = &(struct clk_init_data){ 1841 .name = "sata_rxoob_clk", 1842 .parent_names = (const char *[]){ "sata_ref_src" }, 1843 .num_parents = 1, 1844 .ops = &clk_branch_ops, 1845 .flags = CLK_SET_RATE_PARENT, 1846 }, 1847 }, 1848}; 1849 1850static struct clk_branch sata_pmalive_clk = { 1851 .halt_reg = 0x2fdc, 1852 .halt_bit = 19, 1853 .clkr = { 1854 .enable_reg = 0x2c10, 1855 .enable_mask = BIT(4), 1856 .hw.init = &(struct clk_init_data){ 1857 .name = "sata_pmalive_clk", 1858 .parent_names = (const char *[]){ "sata_ref_src" }, 1859 .num_parents = 1, 1860 .ops = &clk_branch_ops, 1861 .flags = CLK_SET_RATE_PARENT, 1862 }, 1863 }, 1864}; 1865 1866static struct clk_branch sata_phy_ref_clk = { 1867 .halt_reg = 0x2fdc, 1868 .halt_bit = 18, 1869 .clkr = { 1870 .enable_reg = 0x2c14, 1871 .enable_mask = BIT(4), 1872 .hw.init = &(struct clk_init_data){ 1873 .name = "sata_phy_ref_clk", 1874 .parent_names = (const char *[]){ "pxo" }, 1875 .num_parents = 1, 1876 .ops = &clk_branch_ops, 1877 }, 1878 }, 1879}; 1880 1881static struct clk_branch sata_a_clk = { 1882 .halt_reg = 0x2fc0, 1883 .halt_bit = 12, 1884 .clkr = { 1885 .enable_reg = 0x2c20, 1886 .enable_mask = BIT(4), 1887 .hw.init = &(struct clk_init_data){ 1888 .name = "sata_a_clk", 1889 .ops = &clk_branch_ops, 1890 .flags = CLK_IS_ROOT, 1891 }, 1892 }, 1893}; 1894 1895static struct clk_branch sata_h_clk = { 1896 .halt_reg = 0x2fdc, 1897 .halt_bit = 21, 1898 .clkr = { 1899 .enable_reg = 0x2c00, 1900 .enable_mask = BIT(4), 1901 .hw.init = &(struct clk_init_data){ 1902 .name = "sata_h_clk", 1903 .ops = &clk_branch_ops, 1904 .flags = CLK_IS_ROOT, 1905 }, 1906 }, 1907}; 1908 1909static struct clk_branch sfab_sata_s_h_clk = { 1910 .halt_reg = 0x2fc4, 1911 .halt_bit = 14, 1912 .clkr = { 1913 .enable_reg = 0x2480, 1914 .enable_mask = BIT(4), 1915 .hw.init = &(struct clk_init_data){ 1916 .name = "sfab_sata_s_h_clk", 1917 .ops = &clk_branch_ops, 1918 .flags = CLK_IS_ROOT, 1919 }, 1920 }, 1921}; 1922 1923static struct clk_branch sata_phy_cfg_clk = { 1924 .halt_reg = 0x2fcc, 1925 .halt_bit = 14, 1926 .clkr = { 1927 .enable_reg = 0x2c40, 1928 .enable_mask = BIT(4), 1929 .hw.init = &(struct clk_init_data){ 1930 .name = "sata_phy_cfg_clk", 1931 .ops = &clk_branch_ops, 1932 .flags = CLK_IS_ROOT, 1933 }, 1934 }, 1935}; 1936 1937static const struct freq_tbl clk_tbl_usb30_master[] = { 1938 { 125000000, P_PLL0, 1, 5, 32 }, 1939 { } 1940}; 1941 1942static struct clk_rcg usb30_master_clk_src = { 1943 .ns_reg = 0x3b2c, 1944 .md_reg = 0x3b28, 1945 .mn = { 1946 .mnctr_en_bit = 8, 1947 .mnctr_reset_bit = 7, 1948 .mnctr_mode_shift = 5, 1949 .n_val_shift = 16, 1950 .m_val_shift = 16, 1951 .width = 8, 1952 }, 1953 .p = { 1954 .pre_div_shift = 3, 1955 .pre_div_width = 2, 1956 }, 1957 .s = { 1958 .src_sel_shift = 0, 1959 .parent_map = gcc_pxo_pll8_pll0, 1960 }, 1961 .freq_tbl = clk_tbl_usb30_master, 1962 .clkr = { 1963 .enable_reg = 0x3b2c, 1964 .enable_mask = BIT(11), 1965 .hw.init = &(struct clk_init_data){ 1966 .name = "usb30_master_ref_src", 1967 .parent_names = gcc_pxo_pll8_pll0_map, 1968 .num_parents = 3, 1969 .ops = &clk_rcg_ops, 1970 .flags = CLK_SET_RATE_GATE, 1971 }, 1972 }, 1973}; 1974 1975static struct clk_branch usb30_0_branch_clk = { 1976 .halt_reg = 0x2fc4, 1977 .halt_bit = 22, 1978 .clkr = { 1979 .enable_reg = 0x3b24, 1980 .enable_mask = BIT(4), 1981 .hw.init = &(struct clk_init_data){ 1982 .name = "usb30_0_branch_clk", 1983 .parent_names = (const char *[]){ "usb30_master_ref_src", }, 1984 .num_parents = 1, 1985 .ops = &clk_branch_ops, 1986 .flags = CLK_SET_RATE_PARENT, 1987 }, 1988 }, 1989}; 1990 1991static struct clk_branch usb30_1_branch_clk = { 1992 .halt_reg = 0x2fc4, 1993 .halt_bit = 17, 1994 .clkr = { 1995 .enable_reg = 0x3b34, 1996 .enable_mask = BIT(4), 1997 .hw.init = &(struct clk_init_data){ 1998 .name = "usb30_1_branch_clk", 1999 .parent_names = (const char *[]){ "usb30_master_ref_src", }, 2000 .num_parents = 1, 2001 .ops = &clk_branch_ops, 2002 .flags = CLK_SET_RATE_PARENT, 2003 }, 2004 }, 2005}; 2006 2007static const struct freq_tbl clk_tbl_usb30_utmi[] = { 2008 { 60000000, P_PLL8, 1, 5, 32 }, 2009 { } 2010}; 2011 2012static struct clk_rcg usb30_utmi_clk = { 2013 .ns_reg = 0x3b44, 2014 .md_reg = 0x3b40, 2015 .mn = { 2016 .mnctr_en_bit = 8, 2017 .mnctr_reset_bit = 7, 2018 .mnctr_mode_shift = 5, 2019 .n_val_shift = 16, 2020 .m_val_shift = 16, 2021 .width = 8, 2022 }, 2023 .p = { 2024 .pre_div_shift = 3, 2025 .pre_div_width = 2, 2026 }, 2027 .s = { 2028 .src_sel_shift = 0, 2029 .parent_map = gcc_pxo_pll8_pll0, 2030 }, 2031 .freq_tbl = clk_tbl_usb30_utmi, 2032 .clkr = { 2033 .enable_reg = 0x3b44, 2034 .enable_mask = BIT(11), 2035 .hw.init = &(struct clk_init_data){ 2036 .name = "usb30_utmi_clk", 2037 .parent_names = gcc_pxo_pll8_pll0_map, 2038 .num_parents = 3, 2039 .ops = &clk_rcg_ops, 2040 .flags = CLK_SET_RATE_GATE, 2041 }, 2042 }, 2043}; 2044 2045static struct clk_branch usb30_0_utmi_clk_ctl = { 2046 .halt_reg = 0x2fc4, 2047 .halt_bit = 21, 2048 .clkr = { 2049 .enable_reg = 0x3b48, 2050 .enable_mask = BIT(4), 2051 .hw.init = &(struct clk_init_data){ 2052 .name = "usb30_0_utmi_clk_ctl", 2053 .parent_names = (const char *[]){ "usb30_utmi_clk", }, 2054 .num_parents = 1, 2055 .ops = &clk_branch_ops, 2056 .flags = CLK_SET_RATE_PARENT, 2057 }, 2058 }, 2059}; 2060 2061static struct clk_branch usb30_1_utmi_clk_ctl = { 2062 .halt_reg = 0x2fc4, 2063 .halt_bit = 15, 2064 .clkr = { 2065 .enable_reg = 0x3b4c, 2066 .enable_mask = BIT(4), 2067 .hw.init = &(struct clk_init_data){ 2068 .name = "usb30_1_utmi_clk_ctl", 2069 .parent_names = (const char *[]){ "usb30_utmi_clk", }, 2070 .num_parents = 1, 2071 .ops = &clk_branch_ops, 2072 .flags = CLK_SET_RATE_PARENT, 2073 }, 2074 }, 2075}; 2076 2077static const struct freq_tbl clk_tbl_usb[] = { 2078 { 60000000, P_PLL8, 1, 5, 32 }, 2079 { } 2080}; 2081 2082static struct clk_rcg usb_hs1_xcvr_clk_src = { 2083 .ns_reg = 0x290C, 2084 .md_reg = 0x2908, 2085 .mn = { 2086 .mnctr_en_bit = 8, 2087 .mnctr_reset_bit = 7, 2088 .mnctr_mode_shift = 5, 2089 .n_val_shift = 16, 2090 .m_val_shift = 16, 2091 .width = 8, 2092 }, 2093 .p = { 2094 .pre_div_shift = 3, 2095 .pre_div_width = 2, 2096 }, 2097 .s = { 2098 .src_sel_shift = 0, 2099 .parent_map = gcc_pxo_pll8_pll0, 2100 }, 2101 .freq_tbl = clk_tbl_usb, 2102 .clkr = { 2103 .enable_reg = 0x2968, 2104 .enable_mask = BIT(11), 2105 .hw.init = &(struct clk_init_data){ 2106 .name = "usb_hs1_xcvr_src", 2107 .parent_names = gcc_pxo_pll8_pll0_map, 2108 .num_parents = 3, 2109 .ops = &clk_rcg_ops, 2110 .flags = CLK_SET_RATE_GATE, 2111 }, 2112 }, 2113}; 2114 2115static struct clk_branch usb_hs1_xcvr_clk = { 2116 .halt_reg = 0x2fcc, 2117 .halt_bit = 17, 2118 .clkr = { 2119 .enable_reg = 0x290c, 2120 .enable_mask = BIT(9), 2121 .hw.init = &(struct clk_init_data){ 2122 .name = "usb_hs1_xcvr_clk", 2123 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, 2124 .num_parents = 1, 2125 .ops = &clk_branch_ops, 2126 .flags = CLK_SET_RATE_PARENT, 2127 }, 2128 }, 2129}; 2130 2131static struct clk_branch usb_hs1_h_clk = { 2132 .hwcg_reg = 0x2900, 2133 .hwcg_bit = 6, 2134 .halt_reg = 0x2fc8, 2135 .halt_bit = 1, 2136 .clkr = { 2137 .enable_reg = 0x2900, 2138 .enable_mask = BIT(4), 2139 .hw.init = &(struct clk_init_data){ 2140 .name = "usb_hs1_h_clk", 2141 .ops = &clk_branch_ops, 2142 .flags = CLK_IS_ROOT, 2143 }, 2144 }, 2145}; 2146 2147static struct clk_rcg usb_fs1_xcvr_clk_src = { 2148 .ns_reg = 0x2968, 2149 .md_reg = 0x2964, 2150 .mn = { 2151 .mnctr_en_bit = 8, 2152 .mnctr_reset_bit = 7, 2153 .mnctr_mode_shift = 5, 2154 .n_val_shift = 16, 2155 .m_val_shift = 16, 2156 .width = 8, 2157 }, 2158 .p = { 2159 .pre_div_shift = 3, 2160 .pre_div_width = 2, 2161 }, 2162 .s = { 2163 .src_sel_shift = 0, 2164 .parent_map = gcc_pxo_pll8_pll0, 2165 }, 2166 .freq_tbl = clk_tbl_usb, 2167 .clkr = { 2168 .enable_reg = 0x2968, 2169 .enable_mask = BIT(11), 2170 .hw.init = &(struct clk_init_data){ 2171 .name = "usb_fs1_xcvr_src", 2172 .parent_names = gcc_pxo_pll8_pll0_map, 2173 .num_parents = 3, 2174 .ops = &clk_rcg_ops, 2175 .flags = CLK_SET_RATE_GATE, 2176 }, 2177 }, 2178}; 2179 2180static struct clk_branch usb_fs1_xcvr_clk = { 2181 .halt_reg = 0x2fcc, 2182 .halt_bit = 17, 2183 .clkr = { 2184 .enable_reg = 0x2968, 2185 .enable_mask = BIT(9), 2186 .hw.init = &(struct clk_init_data){ 2187 .name = "usb_fs1_xcvr_clk", 2188 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, 2189 .num_parents = 1, 2190 .ops = &clk_branch_ops, 2191 .flags = CLK_SET_RATE_PARENT, 2192 }, 2193 }, 2194}; 2195 2196static struct clk_branch usb_fs1_sys_clk = { 2197 .halt_reg = 0x2fcc, 2198 .halt_bit = 18, 2199 .clkr = { 2200 .enable_reg = 0x296c, 2201 .enable_mask = BIT(4), 2202 .hw.init = &(struct clk_init_data){ 2203 .name = "usb_fs1_sys_clk", 2204 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, 2205 .num_parents = 1, 2206 .ops = &clk_branch_ops, 2207 .flags = CLK_SET_RATE_PARENT, 2208 }, 2209 }, 2210}; 2211 2212static struct clk_branch usb_fs1_h_clk = { 2213 .halt_reg = 0x2fcc, 2214 .halt_bit = 19, 2215 .clkr = { 2216 .enable_reg = 0x2960, 2217 .enable_mask = BIT(4), 2218 .hw.init = &(struct clk_init_data){ 2219 .name = "usb_fs1_h_clk", 2220 .ops = &clk_branch_ops, 2221 .flags = CLK_IS_ROOT, 2222 }, 2223 }, 2224}; 2225 2226static struct clk_branch ebi2_clk = { 2227 .hwcg_reg = 0x3b00, 2228 .hwcg_bit = 6, 2229 .halt_reg = 0x2fcc, 2230 .halt_bit = 1, 2231 .clkr = { 2232 .enable_reg = 0x3b00, 2233 .enable_mask = BIT(4), 2234 .hw.init = &(struct clk_init_data){ 2235 .name = "ebi2_clk", 2236 .ops = &clk_branch_ops, 2237 .flags = CLK_IS_ROOT, 2238 }, 2239 }, 2240}; 2241 2242static struct clk_branch ebi2_aon_clk = { 2243 .halt_reg = 0x2fcc, 2244 .halt_bit = 0, 2245 .clkr = { 2246 .enable_reg = 0x3b00, 2247 .enable_mask = BIT(8), 2248 .hw.init = &(struct clk_init_data){ 2249 .name = "ebi2_always_on_clk", 2250 .ops = &clk_branch_ops, 2251 .flags = CLK_IS_ROOT, 2252 }, 2253 }, 2254}; 2255 2256static const struct freq_tbl clk_tbl_gmac[] = { 2257 { 133000000, P_PLL0, 1, 50, 301 }, 2258 { 266000000, P_PLL0, 1, 127, 382 }, 2259 { } 2260}; 2261 2262static struct clk_dyn_rcg gmac_core1_src = { 2263 .ns_reg[0] = 0x3cac, 2264 .ns_reg[1] = 0x3cb0, 2265 .md_reg[0] = 0x3ca4, 2266 .md_reg[1] = 0x3ca8, 2267 .bank_reg = 0x3ca0, 2268 .mn[0] = { 2269 .mnctr_en_bit = 8, 2270 .mnctr_reset_bit = 7, 2271 .mnctr_mode_shift = 5, 2272 .n_val_shift = 16, 2273 .m_val_shift = 16, 2274 .width = 8, 2275 }, 2276 .mn[1] = { 2277 .mnctr_en_bit = 8, 2278 .mnctr_reset_bit = 7, 2279 .mnctr_mode_shift = 5, 2280 .n_val_shift = 16, 2281 .m_val_shift = 16, 2282 .width = 8, 2283 }, 2284 .s[0] = { 2285 .src_sel_shift = 0, 2286 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2287 }, 2288 .s[1] = { 2289 .src_sel_shift = 0, 2290 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2291 }, 2292 .p[0] = { 2293 .pre_div_shift = 3, 2294 .pre_div_width = 2, 2295 }, 2296 .p[1] = { 2297 .pre_div_shift = 3, 2298 .pre_div_width = 2, 2299 }, 2300 .mux_sel_bit = 0, 2301 .freq_tbl = clk_tbl_gmac, 2302 .clkr = { 2303 .enable_reg = 0x3ca0, 2304 .enable_mask = BIT(1), 2305 .hw.init = &(struct clk_init_data){ 2306 .name = "gmac_core1_src", 2307 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2308 .num_parents = 5, 2309 .ops = &clk_dyn_rcg_ops, 2310 }, 2311 }, 2312}; 2313 2314static struct clk_branch gmac_core1_clk = { 2315 .halt_reg = 0x3c20, 2316 .halt_bit = 4, 2317 .hwcg_reg = 0x3cb4, 2318 .hwcg_bit = 6, 2319 .clkr = { 2320 .enable_reg = 0x3cb4, 2321 .enable_mask = BIT(4), 2322 .hw.init = &(struct clk_init_data){ 2323 .name = "gmac_core1_clk", 2324 .parent_names = (const char *[]){ 2325 "gmac_core1_src", 2326 }, 2327 .num_parents = 1, 2328 .ops = &clk_branch_ops, 2329 .flags = CLK_SET_RATE_PARENT, 2330 }, 2331 }, 2332}; 2333 2334static struct clk_dyn_rcg gmac_core2_src = { 2335 .ns_reg[0] = 0x3ccc, 2336 .ns_reg[1] = 0x3cd0, 2337 .md_reg[0] = 0x3cc4, 2338 .md_reg[1] = 0x3cc8, 2339 .bank_reg = 0x3ca0, 2340 .mn[0] = { 2341 .mnctr_en_bit = 8, 2342 .mnctr_reset_bit = 7, 2343 .mnctr_mode_shift = 5, 2344 .n_val_shift = 16, 2345 .m_val_shift = 16, 2346 .width = 8, 2347 }, 2348 .mn[1] = { 2349 .mnctr_en_bit = 8, 2350 .mnctr_reset_bit = 7, 2351 .mnctr_mode_shift = 5, 2352 .n_val_shift = 16, 2353 .m_val_shift = 16, 2354 .width = 8, 2355 }, 2356 .s[0] = { 2357 .src_sel_shift = 0, 2358 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2359 }, 2360 .s[1] = { 2361 .src_sel_shift = 0, 2362 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2363 }, 2364 .p[0] = { 2365 .pre_div_shift = 3, 2366 .pre_div_width = 2, 2367 }, 2368 .p[1] = { 2369 .pre_div_shift = 3, 2370 .pre_div_width = 2, 2371 }, 2372 .mux_sel_bit = 0, 2373 .freq_tbl = clk_tbl_gmac, 2374 .clkr = { 2375 .enable_reg = 0x3cc0, 2376 .enable_mask = BIT(1), 2377 .hw.init = &(struct clk_init_data){ 2378 .name = "gmac_core2_src", 2379 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2380 .num_parents = 5, 2381 .ops = &clk_dyn_rcg_ops, 2382 }, 2383 }, 2384}; 2385 2386static struct clk_branch gmac_core2_clk = { 2387 .halt_reg = 0x3c20, 2388 .halt_bit = 5, 2389 .hwcg_reg = 0x3cd4, 2390 .hwcg_bit = 6, 2391 .clkr = { 2392 .enable_reg = 0x3cd4, 2393 .enable_mask = BIT(4), 2394 .hw.init = &(struct clk_init_data){ 2395 .name = "gmac_core2_clk", 2396 .parent_names = (const char *[]){ 2397 "gmac_core2_src", 2398 }, 2399 .num_parents = 1, 2400 .ops = &clk_branch_ops, 2401 .flags = CLK_SET_RATE_PARENT, 2402 }, 2403 }, 2404}; 2405 2406static struct clk_dyn_rcg gmac_core3_src = { 2407 .ns_reg[0] = 0x3cec, 2408 .ns_reg[1] = 0x3cf0, 2409 .md_reg[0] = 0x3ce4, 2410 .md_reg[1] = 0x3ce8, 2411 .bank_reg = 0x3ce0, 2412 .mn[0] = { 2413 .mnctr_en_bit = 8, 2414 .mnctr_reset_bit = 7, 2415 .mnctr_mode_shift = 5, 2416 .n_val_shift = 16, 2417 .m_val_shift = 16, 2418 .width = 8, 2419 }, 2420 .mn[1] = { 2421 .mnctr_en_bit = 8, 2422 .mnctr_reset_bit = 7, 2423 .mnctr_mode_shift = 5, 2424 .n_val_shift = 16, 2425 .m_val_shift = 16, 2426 .width = 8, 2427 }, 2428 .s[0] = { 2429 .src_sel_shift = 0, 2430 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2431 }, 2432 .s[1] = { 2433 .src_sel_shift = 0, 2434 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2435 }, 2436 .p[0] = { 2437 .pre_div_shift = 3, 2438 .pre_div_width = 2, 2439 }, 2440 .p[1] = { 2441 .pre_div_shift = 3, 2442 .pre_div_width = 2, 2443 }, 2444 .mux_sel_bit = 0, 2445 .freq_tbl = clk_tbl_gmac, 2446 .clkr = { 2447 .enable_reg = 0x3ce0, 2448 .enable_mask = BIT(1), 2449 .hw.init = &(struct clk_init_data){ 2450 .name = "gmac_core3_src", 2451 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2452 .num_parents = 5, 2453 .ops = &clk_dyn_rcg_ops, 2454 }, 2455 }, 2456}; 2457 2458static struct clk_branch gmac_core3_clk = { 2459 .halt_reg = 0x3c20, 2460 .halt_bit = 6, 2461 .hwcg_reg = 0x3cf4, 2462 .hwcg_bit = 6, 2463 .clkr = { 2464 .enable_reg = 0x3cf4, 2465 .enable_mask = BIT(4), 2466 .hw.init = &(struct clk_init_data){ 2467 .name = "gmac_core3_clk", 2468 .parent_names = (const char *[]){ 2469 "gmac_core3_src", 2470 }, 2471 .num_parents = 1, 2472 .ops = &clk_branch_ops, 2473 .flags = CLK_SET_RATE_PARENT, 2474 }, 2475 }, 2476}; 2477 2478static struct clk_dyn_rcg gmac_core4_src = { 2479 .ns_reg[0] = 0x3d0c, 2480 .ns_reg[1] = 0x3d10, 2481 .md_reg[0] = 0x3d04, 2482 .md_reg[1] = 0x3d08, 2483 .bank_reg = 0x3d00, 2484 .mn[0] = { 2485 .mnctr_en_bit = 8, 2486 .mnctr_reset_bit = 7, 2487 .mnctr_mode_shift = 5, 2488 .n_val_shift = 16, 2489 .m_val_shift = 16, 2490 .width = 8, 2491 }, 2492 .mn[1] = { 2493 .mnctr_en_bit = 8, 2494 .mnctr_reset_bit = 7, 2495 .mnctr_mode_shift = 5, 2496 .n_val_shift = 16, 2497 .m_val_shift = 16, 2498 .width = 8, 2499 }, 2500 .s[0] = { 2501 .src_sel_shift = 0, 2502 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2503 }, 2504 .s[1] = { 2505 .src_sel_shift = 0, 2506 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2507 }, 2508 .p[0] = { 2509 .pre_div_shift = 3, 2510 .pre_div_width = 2, 2511 }, 2512 .p[1] = { 2513 .pre_div_shift = 3, 2514 .pre_div_width = 2, 2515 }, 2516 .mux_sel_bit = 0, 2517 .freq_tbl = clk_tbl_gmac, 2518 .clkr = { 2519 .enable_reg = 0x3d00, 2520 .enable_mask = BIT(1), 2521 .hw.init = &(struct clk_init_data){ 2522 .name = "gmac_core4_src", 2523 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2524 .num_parents = 5, 2525 .ops = &clk_dyn_rcg_ops, 2526 }, 2527 }, 2528}; 2529 2530static struct clk_branch gmac_core4_clk = { 2531 .halt_reg = 0x3c20, 2532 .halt_bit = 7, 2533 .hwcg_reg = 0x3d14, 2534 .hwcg_bit = 6, 2535 .clkr = { 2536 .enable_reg = 0x3d14, 2537 .enable_mask = BIT(4), 2538 .hw.init = &(struct clk_init_data){ 2539 .name = "gmac_core4_clk", 2540 .parent_names = (const char *[]){ 2541 "gmac_core4_src", 2542 }, 2543 .num_parents = 1, 2544 .ops = &clk_branch_ops, 2545 .flags = CLK_SET_RATE_PARENT, 2546 }, 2547 }, 2548}; 2549 2550static const struct freq_tbl clk_tbl_nss_tcm[] = { 2551 { 266000000, P_PLL0, 3, 0, 0 }, 2552 { 400000000, P_PLL0, 2, 0, 0 }, 2553 { } 2554}; 2555 2556static struct clk_dyn_rcg nss_tcm_src = { 2557 .ns_reg[0] = 0x3dc4, 2558 .ns_reg[1] = 0x3dc8, 2559 .bank_reg = 0x3dc0, 2560 .s[0] = { 2561 .src_sel_shift = 0, 2562 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2563 }, 2564 .s[1] = { 2565 .src_sel_shift = 0, 2566 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2567 }, 2568 .p[0] = { 2569 .pre_div_shift = 3, 2570 .pre_div_width = 4, 2571 }, 2572 .p[1] = { 2573 .pre_div_shift = 3, 2574 .pre_div_width = 4, 2575 }, 2576 .mux_sel_bit = 0, 2577 .freq_tbl = clk_tbl_nss_tcm, 2578 .clkr = { 2579 .enable_reg = 0x3dc0, 2580 .enable_mask = BIT(1), 2581 .hw.init = &(struct clk_init_data){ 2582 .name = "nss_tcm_src", 2583 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2584 .num_parents = 5, 2585 .ops = &clk_dyn_rcg_ops, 2586 }, 2587 }, 2588}; 2589 2590static struct clk_branch nss_tcm_clk = { 2591 .halt_reg = 0x3c20, 2592 .halt_bit = 14, 2593 .clkr = { 2594 .enable_reg = 0x3dd0, 2595 .enable_mask = BIT(6) | BIT(4), 2596 .hw.init = &(struct clk_init_data){ 2597 .name = "nss_tcm_clk", 2598 .parent_names = (const char *[]){ 2599 "nss_tcm_src", 2600 }, 2601 .num_parents = 1, 2602 .ops = &clk_branch_ops, 2603 .flags = CLK_SET_RATE_PARENT, 2604 }, 2605 }, 2606}; 2607 2608static const struct freq_tbl clk_tbl_nss[] = { 2609 { 110000000, P_PLL18, 1, 1, 5 }, 2610 { 275000000, P_PLL18, 2, 0, 0 }, 2611 { 550000000, P_PLL18, 1, 0, 0 }, 2612 { 733000000, P_PLL18, 1, 0, 0 }, 2613 { } 2614}; 2615 2616static struct clk_dyn_rcg ubi32_core1_src_clk = { 2617 .ns_reg[0] = 0x3d2c, 2618 .ns_reg[1] = 0x3d30, 2619 .md_reg[0] = 0x3d24, 2620 .md_reg[1] = 0x3d28, 2621 .bank_reg = 0x3d20, 2622 .mn[0] = { 2623 .mnctr_en_bit = 8, 2624 .mnctr_reset_bit = 7, 2625 .mnctr_mode_shift = 5, 2626 .n_val_shift = 16, 2627 .m_val_shift = 16, 2628 .width = 8, 2629 }, 2630 .mn[1] = { 2631 .mnctr_en_bit = 8, 2632 .mnctr_reset_bit = 7, 2633 .mnctr_mode_shift = 5, 2634 .n_val_shift = 16, 2635 .m_val_shift = 16, 2636 .width = 8, 2637 }, 2638 .s[0] = { 2639 .src_sel_shift = 0, 2640 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2641 }, 2642 .s[1] = { 2643 .src_sel_shift = 0, 2644 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2645 }, 2646 .p[0] = { 2647 .pre_div_shift = 3, 2648 .pre_div_width = 2, 2649 }, 2650 .p[1] = { 2651 .pre_div_shift = 3, 2652 .pre_div_width = 2, 2653 }, 2654 .mux_sel_bit = 0, 2655 .freq_tbl = clk_tbl_nss, 2656 .clkr = { 2657 .enable_reg = 0x3d20, 2658 .enable_mask = BIT(1), 2659 .hw.init = &(struct clk_init_data){ 2660 .name = "ubi32_core1_src_clk", 2661 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2662 .num_parents = 5, 2663 .ops = &clk_dyn_rcg_ops, 2664 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 2665 }, 2666 }, 2667}; 2668 2669static struct clk_dyn_rcg ubi32_core2_src_clk = { 2670 .ns_reg[0] = 0x3d4c, 2671 .ns_reg[1] = 0x3d50, 2672 .md_reg[0] = 0x3d44, 2673 .md_reg[1] = 0x3d48, 2674 .bank_reg = 0x3d40, 2675 .mn[0] = { 2676 .mnctr_en_bit = 8, 2677 .mnctr_reset_bit = 7, 2678 .mnctr_mode_shift = 5, 2679 .n_val_shift = 16, 2680 .m_val_shift = 16, 2681 .width = 8, 2682 }, 2683 .mn[1] = { 2684 .mnctr_en_bit = 8, 2685 .mnctr_reset_bit = 7, 2686 .mnctr_mode_shift = 5, 2687 .n_val_shift = 16, 2688 .m_val_shift = 16, 2689 .width = 8, 2690 }, 2691 .s[0] = { 2692 .src_sel_shift = 0, 2693 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2694 }, 2695 .s[1] = { 2696 .src_sel_shift = 0, 2697 .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, 2698 }, 2699 .p[0] = { 2700 .pre_div_shift = 3, 2701 .pre_div_width = 2, 2702 }, 2703 .p[1] = { 2704 .pre_div_shift = 3, 2705 .pre_div_width = 2, 2706 }, 2707 .mux_sel_bit = 0, 2708 .freq_tbl = clk_tbl_nss, 2709 .clkr = { 2710 .enable_reg = 0x3d40, 2711 .enable_mask = BIT(1), 2712 .hw.init = &(struct clk_init_data){ 2713 .name = "ubi32_core2_src_clk", 2714 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, 2715 .num_parents = 5, 2716 .ops = &clk_dyn_rcg_ops, 2717 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 2718 }, 2719 }, 2720}; 2721 2722static struct clk_regmap *gcc_ipq806x_clks[] = { 2723 [PLL0] = &pll0.clkr, 2724 [PLL0_VOTE] = &pll0_vote, 2725 [PLL3] = &pll3.clkr, 2726 [PLL4_VOTE] = &pll4_vote, 2727 [PLL8] = &pll8.clkr, 2728 [PLL8_VOTE] = &pll8_vote, 2729 [PLL14] = &pll14.clkr, 2730 [PLL14_VOTE] = &pll14_vote, 2731 [PLL18] = &pll18.clkr, 2732 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, 2733 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, 2734 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, 2735 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, 2736 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, 2737 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, 2738 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, 2739 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, 2740 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, 2741 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, 2742 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 2743 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 2744 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, 2745 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, 2746 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, 2747 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, 2748 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, 2749 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, 2750 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, 2751 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, 2752 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, 2753 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, 2754 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 2755 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 2756 [GP0_SRC] = &gp0_src.clkr, 2757 [GP0_CLK] = &gp0_clk.clkr, 2758 [GP1_SRC] = &gp1_src.clkr, 2759 [GP1_CLK] = &gp1_clk.clkr, 2760 [GP2_SRC] = &gp2_src.clkr, 2761 [GP2_CLK] = &gp2_clk.clkr, 2762 [PMEM_A_CLK] = &pmem_clk.clkr, 2763 [PRNG_SRC] = &prng_src.clkr, 2764 [PRNG_CLK] = &prng_clk.clkr, 2765 [SDC1_SRC] = &sdc1_src.clkr, 2766 [SDC1_CLK] = &sdc1_clk.clkr, 2767 [SDC3_SRC] = &sdc3_src.clkr, 2768 [SDC3_CLK] = &sdc3_clk.clkr, 2769 [TSIF_REF_SRC] = &tsif_ref_src.clkr, 2770 [TSIF_REF_CLK] = &tsif_ref_clk.clkr, 2771 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr, 2772 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, 2773 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, 2774 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, 2775 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, 2776 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, 2777 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 2778 [TSIF_H_CLK] = &tsif_h_clk.clkr, 2779 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 2780 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 2781 [ADM0_CLK] = &adm0_clk.clkr, 2782 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 2783 [PCIE_A_CLK] = &pcie_a_clk.clkr, 2784 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr, 2785 [PCIE_H_CLK] = &pcie_h_clk.clkr, 2786 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr, 2787 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr, 2788 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, 2789 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, 2790 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, 2791 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, 2792 [SATA_H_CLK] = &sata_h_clk.clkr, 2793 [SATA_CLK_SRC] = &sata_ref_src.clkr, 2794 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr, 2795 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr, 2796 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr, 2797 [SATA_A_CLK] = &sata_a_clk.clkr, 2798 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr, 2799 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr, 2800 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr, 2801 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr, 2802 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr, 2803 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr, 2804 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr, 2805 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr, 2806 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr, 2807 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr, 2808 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr, 2809 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr, 2810 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr, 2811 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr, 2812 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr, 2813 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr, 2814 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr, 2815 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr, 2816 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr, 2817 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr, 2818 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr, 2819 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, 2820 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr, 2821 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, 2822 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, 2823 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, 2824 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, 2825 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, 2826 [EBI2_CLK] = &ebi2_clk.clkr, 2827 [EBI2_AON_CLK] = &ebi2_aon_clk.clkr, 2828 [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr, 2829 [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr, 2830 [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr, 2831 [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr, 2832 [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr, 2833 [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr, 2834 [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr, 2835 [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr, 2836 [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr, 2837 [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr, 2838 [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr, 2839 [NSSTCM_CLK] = &nss_tcm_clk.clkr, 2840}; 2841 2842static const struct qcom_reset_map gcc_ipq806x_resets[] = { 2843 [QDSS_STM_RESET] = { 0x2060, 6 }, 2844 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, 2845 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, 2846 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 }, 2847 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 }, 2848 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 }, 2849 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, 2850 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, 2851 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 }, 2852 [ADM0_C2_RESET] = { 0x220c, 4 }, 2853 [ADM0_C1_RESET] = { 0x220c, 3 }, 2854 [ADM0_C0_RESET] = { 0x220c, 2 }, 2855 [ADM0_PBUS_RESET] = { 0x220c, 1 }, 2856 [ADM0_RESET] = { 0x220c, 0 }, 2857 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 }, 2858 [QDSS_POR_RESET] = { 0x2260, 4 }, 2859 [QDSS_TSCTR_RESET] = { 0x2260, 3 }, 2860 [QDSS_HRESET_RESET] = { 0x2260, 2 }, 2861 [QDSS_AXI_RESET] = { 0x2260, 1 }, 2862 [QDSS_DBG_RESET] = { 0x2260, 0 }, 2863 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 }, 2864 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 }, 2865 [PCIE_EXT_RESET] = { 0x22dc, 6 }, 2866 [PCIE_PHY_RESET] = { 0x22dc, 5 }, 2867 [PCIE_PCI_RESET] = { 0x22dc, 4 }, 2868 [PCIE_POR_RESET] = { 0x22dc, 3 }, 2869 [PCIE_HCLK_RESET] = { 0x22dc, 2 }, 2870 [PCIE_ACLK_RESET] = { 0x22dc, 0 }, 2871 [SFAB_LPASS_RESET] = { 0x23a0, 7 }, 2872 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, 2873 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, 2874 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, 2875 [SFAB_SATA_S_RESET] = { 0x2480, 7 }, 2876 [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, 2877 [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, 2878 [DFAB_SWAY0_RESET] = { 0x2540, 7 }, 2879 [DFAB_SWAY1_RESET] = { 0x2544, 7 }, 2880 [DFAB_ARB0_RESET] = { 0x2560, 7 }, 2881 [DFAB_ARB1_RESET] = { 0x2564, 7 }, 2882 [PPSS_PROC_RESET] = { 0x2594, 1 }, 2883 [PPSS_RESET] = { 0x2594, 0 }, 2884 [DMA_BAM_RESET] = { 0x25c0, 7 }, 2885 [SPS_TIC_H_RESET] = { 0x2600, 7 }, 2886 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 2887 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 2888 [TSIF_H_RESET] = { 0x2700, 7 }, 2889 [CE1_H_RESET] = { 0x2720, 7 }, 2890 [CE1_CORE_RESET] = { 0x2724, 7 }, 2891 [CE1_SLEEP_RESET] = { 0x2728, 7 }, 2892 [CE2_H_RESET] = { 0x2740, 7 }, 2893 [CE2_CORE_RESET] = { 0x2744, 7 }, 2894 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 2895 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 2896 [RPM_PROC_RESET] = { 0x27c0, 7 }, 2897 [PMIC_SSBI2_RESET] = { 0x280c, 12 }, 2898 [SDC1_RESET] = { 0x2830, 0 }, 2899 [SDC2_RESET] = { 0x2850, 0 }, 2900 [SDC3_RESET] = { 0x2870, 0 }, 2901 [SDC4_RESET] = { 0x2890, 0 }, 2902 [USB_HS1_RESET] = { 0x2910, 0 }, 2903 [USB_HSIC_RESET] = { 0x2934, 0 }, 2904 [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, 2905 [USB_FS1_RESET] = { 0x2974, 0 }, 2906 [GSBI1_RESET] = { 0x29dc, 0 }, 2907 [GSBI2_RESET] = { 0x29fc, 0 }, 2908 [GSBI3_RESET] = { 0x2a1c, 0 }, 2909 [GSBI4_RESET] = { 0x2a3c, 0 }, 2910 [GSBI5_RESET] = { 0x2a5c, 0 }, 2911 [GSBI6_RESET] = { 0x2a7c, 0 }, 2912 [GSBI7_RESET] = { 0x2a9c, 0 }, 2913 [SPDM_RESET] = { 0x2b6c, 0 }, 2914 [SEC_CTRL_RESET] = { 0x2b80, 7 }, 2915 [TLMM_H_RESET] = { 0x2ba0, 7 }, 2916 [SFAB_SATA_M_RESET] = { 0x2c18, 0 }, 2917 [SATA_RESET] = { 0x2c1c, 0 }, 2918 [TSSC_RESET] = { 0x2ca0, 7 }, 2919 [PDM_RESET] = { 0x2cc0, 12 }, 2920 [MPM_H_RESET] = { 0x2da0, 7 }, 2921 [MPM_RESET] = { 0x2da4, 0 }, 2922 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, 2923 [PRNG_RESET] = { 0x2e80, 12 }, 2924 [SFAB_CE3_M_RESET] = { 0x36c8, 1 }, 2925 [SFAB_CE3_S_RESET] = { 0x36c8, 0 }, 2926 [CE3_SLEEP_RESET] = { 0x36d0, 7 }, 2927 [PCIE_1_M_RESET] = { 0x3a98, 1 }, 2928 [PCIE_1_S_RESET] = { 0x3a98, 0 }, 2929 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 }, 2930 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 }, 2931 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 }, 2932 [PCIE_1_POR_RESET] = { 0x3a9c, 3 }, 2933 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 }, 2934 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 }, 2935 [PCIE_2_M_RESET] = { 0x3ad8, 1 }, 2936 [PCIE_2_S_RESET] = { 0x3ad8, 0 }, 2937 [PCIE_2_EXT_RESET] = { 0x3adc, 6 }, 2938 [PCIE_2_PHY_RESET] = { 0x3adc, 5 }, 2939 [PCIE_2_PCI_RESET] = { 0x3adc, 4 }, 2940 [PCIE_2_POR_RESET] = { 0x3adc, 3 }, 2941 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 }, 2942 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 }, 2943 [SFAB_USB30_S_RESET] = { 0x3b54, 1 }, 2944 [SFAB_USB30_M_RESET] = { 0x3b54, 0 }, 2945 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 }, 2946 [USB30_0_MASTER_RESET] = { 0x3b50, 4 }, 2947 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 }, 2948 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 }, 2949 [USB30_0_POWERON_RESET] = { 0x3b50, 1 }, 2950 [USB30_0_PHY_RESET] = { 0x3b50, 0 }, 2951 [USB30_1_MASTER_RESET] = { 0x3b58, 4 }, 2952 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 }, 2953 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 }, 2954 [USB30_1_POWERON_RESET] = { 0x3b58, 1 }, 2955 [USB30_1_PHY_RESET] = { 0x3b58, 0 }, 2956 [NSSFB0_RESET] = { 0x3b60, 6 }, 2957 [NSSFB1_RESET] = { 0x3b60, 7 }, 2958 [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3}, 2959 [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 }, 2960 [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 }, 2961 [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 }, 2962 [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 }, 2963 [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 }, 2964 [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 }, 2965 [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 }, 2966 [GMAC_CORE1_RESET] = { 0x3cbc, 0 }, 2967 [GMAC_CORE2_RESET] = { 0x3cdc, 0 }, 2968 [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, 2969 [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, 2970 [GMAC_AHB_RESET] = { 0x3e24, 0 }, 2971 [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, 2972 [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, 2973 [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, 2974 [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 }, 2975 [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 }, 2976 [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 }, 2977 [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 }, 2978 [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 }, 2979 [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 }, 2980 [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 }, 2981 [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 }, 2982 [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 }, 2983 [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 }, 2984 [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 }, 2985 [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 }, 2986 [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 }, 2987 [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 }, 2988 [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 }, 2989 [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 }, 2990 [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 }, 2991 [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 }, 2992 [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 }, 2993 [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 }, 2994 [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 }, 2995 [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 }, 2996 [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 }, 2997 [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 }, 2998 [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 }, 2999 [NSS_SRDS_N_RESET] = { 0x3b60, 28 }, 3000}; 3001 3002static const struct regmap_config gcc_ipq806x_regmap_config = { 3003 .reg_bits = 32, 3004 .reg_stride = 4, 3005 .val_bits = 32, 3006 .max_register = 0x3e40, 3007 .fast_io = true, 3008}; 3009 3010static const struct qcom_cc_desc gcc_ipq806x_desc = { 3011 .config = &gcc_ipq806x_regmap_config, 3012 .clks = gcc_ipq806x_clks, 3013 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks), 3014 .resets = gcc_ipq806x_resets, 3015 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets), 3016}; 3017 3018static const struct of_device_id gcc_ipq806x_match_table[] = { 3019 { .compatible = "qcom,gcc-ipq8064" }, 3020 { } 3021}; 3022MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table); 3023 3024static int gcc_ipq806x_probe(struct platform_device *pdev) 3025{ 3026 struct clk *clk; 3027 struct device *dev = &pdev->dev; 3028 struct regmap *regmap; 3029 int ret; 3030 3031 /* Temporary until RPM clocks supported */ 3032 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000); 3033 if (IS_ERR(clk)) 3034 return PTR_ERR(clk); 3035 3036 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000); 3037 if (IS_ERR(clk)) 3038 return PTR_ERR(clk); 3039 3040 ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); 3041 if (ret) 3042 return ret; 3043 3044 regmap = dev_get_regmap(dev, NULL); 3045 if (!regmap) 3046 return -ENODEV; 3047 3048 /* Setup PLL18 static bits */ 3049 regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400); 3050 regmap_write(regmap, 0x31b0, 0x3080); 3051 3052 /* Set GMAC footswitch sleep/wakeup values */ 3053 regmap_write(regmap, 0x3cb8, 8); 3054 regmap_write(regmap, 0x3cd8, 8); 3055 regmap_write(regmap, 0x3cf8, 8); 3056 regmap_write(regmap, 0x3d18, 8); 3057 3058 return 0; 3059} 3060 3061static struct platform_driver gcc_ipq806x_driver = { 3062 .probe = gcc_ipq806x_probe, 3063 .driver = { 3064 .name = "gcc-ipq806x", 3065 .of_match_table = gcc_ipq806x_match_table, 3066 }, 3067}; 3068 3069static int __init gcc_ipq806x_init(void) 3070{ 3071 return platform_driver_register(&gcc_ipq806x_driver); 3072} 3073core_initcall(gcc_ipq806x_init); 3074 3075static void __exit gcc_ipq806x_exit(void) 3076{ 3077 platform_driver_unregister(&gcc_ipq806x_driver); 3078} 3079module_exit(gcc_ipq806x_exit); 3080 3081MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver"); 3082MODULE_LICENSE("GPL v2"); 3083MODULE_ALIAS("platform:gcc-ipq806x"); 3084