1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * based on clk/samsung/clk-cpu.c
6 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
7 * Author: Thomas Abraham <thomas.ab@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * A CPU clock is defined as a clock supplied to a CPU or a group of CPUs.
14 * The CPU clock is typically derived from a hierarchy of clock
15 * blocks which includes mux and divider blocks. There are a number of other
16 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
17 * clock for CPU domain. The rates of these auxiliary clocks are related to the
18 * CPU clock rate and this relation is usually specified in the hardware manual
19 * of the SoC or supplied after the SoC characterization.
20 *
21 * The below implementation of the CPU clock allows the rate changes of the CPU
22 * clock and the corresponding rate changes of the auxillary clocks of the CPU
23 * domain. The platform clock driver provides a clock register configuration
24 * for each configurable rate which is then used to program the clock hardware
25 * registers to acheive a fast co-oridinated rate change for all the CPU domain
26 * clocks.
27 *
28 * On a rate change request for the CPU clock, the rate change is propagated
29 * upto the PLL supplying the clock to the CPU domain clock blocks. While the
30 * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
31 * alternate clock source. If required, the alternate clock source is divided
32 * down in order to keep the output clock rate within the previous OPP limits.
33 */
34
35#include <linux/of.h>
36#include <linux/slab.h>
37#include <linux/io.h>
38#include <linux/clk.h>
39#include <linux/clk-provider.h>
40#include "clk.h"
41
42/**
43 * struct rockchip_cpuclk: information about clock supplied to a CPU core.
44 * @hw:		handle between ccf and cpu clock.
45 * @alt_parent:	alternate parent clock to use when switching the speed
46 *		of the primary parent clock.
47 * @reg_base:	base register for cpu-clock values.
48 * @clk_nb:	clock notifier registered for changes in clock speed of the
49 *		primary parent clock.
50 * @rate_count:	number of rates in the rate_table
51 * @rate_table:	pll-rates and their associated dividers
52 * @reg_data:	cpu-specific register settings
53 * @lock:	clock lock
54 */
55struct rockchip_cpuclk {
56	struct clk_hw				hw;
57
58	struct clk_mux				cpu_mux;
59	const struct clk_ops			*cpu_mux_ops;
60
61	struct clk				*alt_parent;
62	void __iomem				*reg_base;
63	struct notifier_block			clk_nb;
64	unsigned int				rate_count;
65	struct rockchip_cpuclk_rate_table	*rate_table;
66	const struct rockchip_cpuclk_reg_data	*reg_data;
67	spinlock_t				*lock;
68};
69
70#define to_rockchip_cpuclk_hw(hw) container_of(hw, struct rockchip_cpuclk, hw)
71#define to_rockchip_cpuclk_nb(nb) \
72			container_of(nb, struct rockchip_cpuclk, clk_nb)
73
74static const struct rockchip_cpuclk_rate_table *rockchip_get_cpuclk_settings(
75			    struct rockchip_cpuclk *cpuclk, unsigned long rate)
76{
77	const struct rockchip_cpuclk_rate_table *rate_table =
78							cpuclk->rate_table;
79	int i;
80
81	for (i = 0; i < cpuclk->rate_count; i++) {
82		if (rate == rate_table[i].prate)
83			return &rate_table[i];
84	}
85
86	return NULL;
87}
88
89static unsigned long rockchip_cpuclk_recalc_rate(struct clk_hw *hw,
90					unsigned long parent_rate)
91{
92	struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw);
93	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
94	u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg);
95
96	clksel0 >>= reg_data->div_core_shift;
97	clksel0 &= reg_data->div_core_mask;
98	return parent_rate / (clksel0 + 1);
99}
100
101static const struct clk_ops rockchip_cpuclk_ops = {
102	.recalc_rate = rockchip_cpuclk_recalc_rate,
103};
104
105static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,
106				const struct rockchip_cpuclk_rate_table *rate)
107{
108	int i;
109
110	/* alternate parent is active now. set the dividers */
111	for (i = 0; i < ARRAY_SIZE(rate->divs); i++) {
112		const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i];
113
114		if (!clksel->reg)
115			continue;
116
117		pr_debug("%s: setting reg 0x%x to 0x%x\n",
118			 __func__, clksel->reg, clksel->val);
119		writel(clksel->val , cpuclk->reg_base + clksel->reg);
120	}
121}
122
123static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
124					   struct clk_notifier_data *ndata)
125{
126	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
127	unsigned long alt_prate, alt_div;
128	unsigned long flags;
129
130	alt_prate = clk_get_rate(cpuclk->alt_parent);
131
132	spin_lock_irqsave(cpuclk->lock, flags);
133
134	/*
135	 * If the old parent clock speed is less than the clock speed
136	 * of the alternate parent, then it should be ensured that at no point
137	 * the armclk speed is more than the old_rate until the dividers are
138	 * set.
139	 */
140	if (alt_prate > ndata->old_rate) {
141		/* calculate dividers */
142		alt_div =  DIV_ROUND_UP(alt_prate, ndata->old_rate) - 1;
143		if (alt_div > reg_data->div_core_mask) {
144			pr_warn("%s: limiting alt-divider %lu to %d\n",
145				__func__, alt_div, reg_data->div_core_mask);
146			alt_div = reg_data->div_core_mask;
147		}
148
149		/*
150		 * Change parents and add dividers in a single transaction.
151		 *
152		 * NOTE: we do this in a single transaction so we're never
153		 * dividing the primary parent by the extra dividers that were
154		 * needed for the alt.
155		 */
156		pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
157			 __func__, alt_div, alt_prate, ndata->old_rate);
158
159		writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
160					      reg_data->div_core_shift) |
161		       HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),
162		       cpuclk->reg_base + reg_data->core_reg);
163	} else {
164		/* select alternate parent */
165		writel(HIWORD_UPDATE(1, 1, reg_data->mux_core_shift),
166			cpuclk->reg_base + reg_data->core_reg);
167	}
168
169	spin_unlock_irqrestore(cpuclk->lock, flags);
170	return 0;
171}
172
173static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
174					    struct clk_notifier_data *ndata)
175{
176	const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
177	const struct rockchip_cpuclk_rate_table *rate;
178	unsigned long flags;
179
180	rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
181	if (!rate) {
182		pr_err("%s: Invalid rate : %lu for cpuclk\n",
183		       __func__, ndata->new_rate);
184		return -EINVAL;
185	}
186
187	spin_lock_irqsave(cpuclk->lock, flags);
188
189	if (ndata->old_rate < ndata->new_rate)
190		rockchip_cpuclk_set_dividers(cpuclk, rate);
191
192	/*
193	 * post-rate change event, re-mux to primary parent and remove dividers.
194	 *
195	 * NOTE: we do this in a single transaction so we're never dividing the
196	 * primary parent by the extra dividers that were needed for the alt.
197	 */
198
199	writel(HIWORD_UPDATE(0, reg_data->div_core_mask,
200				reg_data->div_core_shift) |
201	       HIWORD_UPDATE(0, 1, reg_data->mux_core_shift),
202	       cpuclk->reg_base + reg_data->core_reg);
203
204	if (ndata->old_rate > ndata->new_rate)
205		rockchip_cpuclk_set_dividers(cpuclk, rate);
206
207	spin_unlock_irqrestore(cpuclk->lock, flags);
208	return 0;
209}
210
211/*
212 * This clock notifier is called when the frequency of the parent clock
213 * of cpuclk is to be changed. This notifier handles the setting up all
214 * the divider clocks, remux to temporary parent and handling the safe
215 * frequency levels when using temporary parent.
216 */
217static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb,
218					unsigned long event, void *data)
219{
220	struct clk_notifier_data *ndata = data;
221	struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb);
222	int ret = 0;
223
224	pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
225		 __func__, event, ndata->old_rate, ndata->new_rate);
226	if (event == PRE_RATE_CHANGE)
227		ret = rockchip_cpuclk_pre_rate_change(cpuclk, ndata);
228	else if (event == POST_RATE_CHANGE)
229		ret = rockchip_cpuclk_post_rate_change(cpuclk, ndata);
230
231	return notifier_from_errno(ret);
232}
233
234struct clk *rockchip_clk_register_cpuclk(const char *name,
235			const char *const *parent_names, u8 num_parents,
236			const struct rockchip_cpuclk_reg_data *reg_data,
237			const struct rockchip_cpuclk_rate_table *rates,
238			int nrates, void __iomem *reg_base, spinlock_t *lock)
239{
240	struct rockchip_cpuclk *cpuclk;
241	struct clk_init_data init;
242	struct clk *clk, *cclk;
243	int ret;
244
245	if (num_parents != 2) {
246		pr_err("%s: needs two parent clocks\n", __func__);
247		return ERR_PTR(-EINVAL);
248	}
249
250	cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
251	if (!cpuclk)
252		return ERR_PTR(-ENOMEM);
253
254	init.name = name;
255	init.parent_names = &parent_names[0];
256	init.num_parents = 1;
257	init.ops = &rockchip_cpuclk_ops;
258
259	/* only allow rate changes when we have a rate table */
260	init.flags = (nrates > 0) ? CLK_SET_RATE_PARENT : 0;
261
262	/* disallow automatic parent changes by ccf */
263	init.flags |= CLK_SET_RATE_NO_REPARENT;
264
265	init.flags |= CLK_GET_RATE_NOCACHE;
266
267	cpuclk->reg_base = reg_base;
268	cpuclk->lock = lock;
269	cpuclk->reg_data = reg_data;
270	cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
271	cpuclk->hw.init = &init;
272
273	cpuclk->alt_parent = __clk_lookup(parent_names[1]);
274	if (!cpuclk->alt_parent) {
275		pr_err("%s: could not lookup alternate parent\n",
276		       __func__);
277		ret = -EINVAL;
278		goto free_cpuclk;
279	}
280
281	ret = clk_prepare_enable(cpuclk->alt_parent);
282	if (ret) {
283		pr_err("%s: could not enable alternate parent\n",
284		       __func__);
285		goto free_cpuclk;
286	}
287
288	clk = __clk_lookup(parent_names[0]);
289	if (!clk) {
290		pr_err("%s: could not lookup parent clock %s\n",
291		       __func__, parent_names[0]);
292		ret = -EINVAL;
293		goto free_cpuclk;
294	}
295
296	ret = clk_notifier_register(clk, &cpuclk->clk_nb);
297	if (ret) {
298		pr_err("%s: failed to register clock notifier for %s\n",
299				__func__, name);
300		goto free_cpuclk;
301	}
302
303	if (nrates > 0) {
304		cpuclk->rate_count = nrates;
305		cpuclk->rate_table = kmemdup(rates,
306					     sizeof(*rates) * nrates,
307					     GFP_KERNEL);
308		if (!cpuclk->rate_table) {
309			pr_err("%s: could not allocate memory for cpuclk rates\n",
310			       __func__);
311			ret = -ENOMEM;
312			goto unregister_notifier;
313		}
314	}
315
316	cclk = clk_register(NULL, &cpuclk->hw);
317	if (IS_ERR(clk)) {
318		pr_err("%s: could not register cpuclk %s\n", __func__,	name);
319		ret = PTR_ERR(clk);
320		goto free_rate_table;
321	}
322
323	return cclk;
324
325free_rate_table:
326	kfree(cpuclk->rate_table);
327unregister_notifier:
328	clk_notifier_unregister(clk, &cpuclk->clk_nb);
329free_cpuclk:
330	kfree(cpuclk);
331	return ERR_PTR(ret);
332}
333