Lines Matching refs:CLK_SET_RATE_PARENT
322 CLK_SET_RATE_PARENT, 0),
324 CLK_SET_RATE_PARENT, 0),
366 CLK_SET_RATE_PARENT, 0),
373 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
376 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
381 CLK_SET_RATE_PARENT, 0),
386 CLK_SET_RATE_PARENT, 0),
389 CLK_SET_RATE_PARENT, 0),
398 CLK_SET_RATE_PARENT, 0),
401 CLK_SET_RATE_PARENT, 0),
501 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
503 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
505 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
507 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
511 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
515 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
519 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
521 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
523 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
527 GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
529 GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
531 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
533 GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
538 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
540 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
542 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
544 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
548 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
550 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
552 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
554 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
556 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
558 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),