Lines Matching refs:CLK_SET_RATE_PARENT

297 					CLK_SET_RATE_PARENT, 0, "mout_apll"),
420 			DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
434 			DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
437 			DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
441 			DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
444 			DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
453 			DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
456 			DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
460 			DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
493 			SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
495 			SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
497 			SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
499 			SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
501 			SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
504 			SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
506 			SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
508 			SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
513 			SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
516 			SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
518 			SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
520 			SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
522 			SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
524 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
526 			SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
529 			SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
532 			SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
534 			SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
536 			SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
538 			SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
540 			SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
543 			SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
545 			SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
549 			SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
551 			SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
553 			SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
592 					CLK_SET_RATE_PARENT, 0),