Lines Matching refs:CLK_SET_RATE_PARENT

123 				CLK_SET_RATE_PARENT, 1, 2);  in mmp2_clk_init()
127 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
131 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
135 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
139 CLK_SET_RATE_PARENT, 1, 5); in mmp2_clk_init()
143 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
147 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
151 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
155 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
159 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
163 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
167 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
171 CLK_SET_RATE_PARENT, 1, 3); in mmp2_clk_init()
175 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
179 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
183 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
187 CLK_SET_RATE_PARENT, 1, 2); in mmp2_clk_init()
251 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
262 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
273 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
284 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
295 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
305 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
315 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
325 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
335 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
340 CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0, in mmp2_clk_init()
366 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
371 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0, in mmp2_clk_init()
389 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
394 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1, in mmp2_clk_init()
408 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
413 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
426 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
436 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in mmp2_clk_init()
441 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, in mmp2_clk_init()
454 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, in mmp2_clk_init()