1/* 2 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <linux/kernel.h> 15#include <linux/bitops.h> 16#include <linux/err.h> 17#include <linux/platform_device.h> 18#include <linux/module.h> 19#include <linux/of.h> 20#include <linux/of_device.h> 21#include <linux/clk-provider.h> 22#include <linux/regmap.h> 23#include <linux/reset-controller.h> 24 25#include <dt-bindings/clock/qcom,gcc-msm8660.h> 26#include <dt-bindings/reset/qcom,gcc-msm8660.h> 27 28#include "common.h" 29#include "clk-regmap.h" 30#include "clk-pll.h" 31#include "clk-rcg.h" 32#include "clk-branch.h" 33#include "reset.h" 34 35static struct clk_pll pll8 = { 36 .l_reg = 0x3144, 37 .m_reg = 0x3148, 38 .n_reg = 0x314c, 39 .config_reg = 0x3154, 40 .mode_reg = 0x3140, 41 .status_reg = 0x3158, 42 .status_bit = 16, 43 .clkr.hw.init = &(struct clk_init_data){ 44 .name = "pll8", 45 .parent_names = (const char *[]){ "pxo" }, 46 .num_parents = 1, 47 .ops = &clk_pll_ops, 48 }, 49}; 50 51static struct clk_regmap pll8_vote = { 52 .enable_reg = 0x34c0, 53 .enable_mask = BIT(8), 54 .hw.init = &(struct clk_init_data){ 55 .name = "pll8_vote", 56 .parent_names = (const char *[]){ "pll8" }, 57 .num_parents = 1, 58 .ops = &clk_pll_vote_ops, 59 }, 60}; 61 62enum { 63 P_PXO, 64 P_PLL8, 65 P_CXO, 66}; 67 68static const struct parent_map gcc_pxo_pll8_map[] = { 69 { P_PXO, 0 }, 70 { P_PLL8, 3 } 71}; 72 73static const char * const gcc_pxo_pll8[] = { 74 "pxo", 75 "pll8_vote", 76}; 77 78static const struct parent_map gcc_pxo_pll8_cxo_map[] = { 79 { P_PXO, 0 }, 80 { P_PLL8, 3 }, 81 { P_CXO, 5 } 82}; 83 84static const char * const gcc_pxo_pll8_cxo[] = { 85 "pxo", 86 "pll8_vote", 87 "cxo", 88}; 89 90static struct freq_tbl clk_tbl_gsbi_uart[] = { 91 { 1843200, P_PLL8, 2, 6, 625 }, 92 { 3686400, P_PLL8, 2, 12, 625 }, 93 { 7372800, P_PLL8, 2, 24, 625 }, 94 { 14745600, P_PLL8, 2, 48, 625 }, 95 { 16000000, P_PLL8, 4, 1, 6 }, 96 { 24000000, P_PLL8, 4, 1, 4 }, 97 { 32000000, P_PLL8, 4, 1, 3 }, 98 { 40000000, P_PLL8, 1, 5, 48 }, 99 { 46400000, P_PLL8, 1, 29, 240 }, 100 { 48000000, P_PLL8, 4, 1, 2 }, 101 { 51200000, P_PLL8, 1, 2, 15 }, 102 { 56000000, P_PLL8, 1, 7, 48 }, 103 { 58982400, P_PLL8, 1, 96, 625 }, 104 { 64000000, P_PLL8, 2, 1, 3 }, 105 { } 106}; 107 108static struct clk_rcg gsbi1_uart_src = { 109 .ns_reg = 0x29d4, 110 .md_reg = 0x29d0, 111 .mn = { 112 .mnctr_en_bit = 8, 113 .mnctr_reset_bit = 7, 114 .mnctr_mode_shift = 5, 115 .n_val_shift = 16, 116 .m_val_shift = 16, 117 .width = 16, 118 }, 119 .p = { 120 .pre_div_shift = 3, 121 .pre_div_width = 2, 122 }, 123 .s = { 124 .src_sel_shift = 0, 125 .parent_map = gcc_pxo_pll8_map, 126 }, 127 .freq_tbl = clk_tbl_gsbi_uart, 128 .clkr = { 129 .enable_reg = 0x29d4, 130 .enable_mask = BIT(11), 131 .hw.init = &(struct clk_init_data){ 132 .name = "gsbi1_uart_src", 133 .parent_names = gcc_pxo_pll8, 134 .num_parents = 2, 135 .ops = &clk_rcg_ops, 136 .flags = CLK_SET_PARENT_GATE, 137 }, 138 }, 139}; 140 141static struct clk_branch gsbi1_uart_clk = { 142 .halt_reg = 0x2fcc, 143 .halt_bit = 10, 144 .clkr = { 145 .enable_reg = 0x29d4, 146 .enable_mask = BIT(9), 147 .hw.init = &(struct clk_init_data){ 148 .name = "gsbi1_uart_clk", 149 .parent_names = (const char *[]){ 150 "gsbi1_uart_src", 151 }, 152 .num_parents = 1, 153 .ops = &clk_branch_ops, 154 .flags = CLK_SET_RATE_PARENT, 155 }, 156 }, 157}; 158 159static struct clk_rcg gsbi2_uart_src = { 160 .ns_reg = 0x29f4, 161 .md_reg = 0x29f0, 162 .mn = { 163 .mnctr_en_bit = 8, 164 .mnctr_reset_bit = 7, 165 .mnctr_mode_shift = 5, 166 .n_val_shift = 16, 167 .m_val_shift = 16, 168 .width = 16, 169 }, 170 .p = { 171 .pre_div_shift = 3, 172 .pre_div_width = 2, 173 }, 174 .s = { 175 .src_sel_shift = 0, 176 .parent_map = gcc_pxo_pll8_map, 177 }, 178 .freq_tbl = clk_tbl_gsbi_uart, 179 .clkr = { 180 .enable_reg = 0x29f4, 181 .enable_mask = BIT(11), 182 .hw.init = &(struct clk_init_data){ 183 .name = "gsbi2_uart_src", 184 .parent_names = gcc_pxo_pll8, 185 .num_parents = 2, 186 .ops = &clk_rcg_ops, 187 .flags = CLK_SET_PARENT_GATE, 188 }, 189 }, 190}; 191 192static struct clk_branch gsbi2_uart_clk = { 193 .halt_reg = 0x2fcc, 194 .halt_bit = 6, 195 .clkr = { 196 .enable_reg = 0x29f4, 197 .enable_mask = BIT(9), 198 .hw.init = &(struct clk_init_data){ 199 .name = "gsbi2_uart_clk", 200 .parent_names = (const char *[]){ 201 "gsbi2_uart_src", 202 }, 203 .num_parents = 1, 204 .ops = &clk_branch_ops, 205 .flags = CLK_SET_RATE_PARENT, 206 }, 207 }, 208}; 209 210static struct clk_rcg gsbi3_uart_src = { 211 .ns_reg = 0x2a14, 212 .md_reg = 0x2a10, 213 .mn = { 214 .mnctr_en_bit = 8, 215 .mnctr_reset_bit = 7, 216 .mnctr_mode_shift = 5, 217 .n_val_shift = 16, 218 .m_val_shift = 16, 219 .width = 16, 220 }, 221 .p = { 222 .pre_div_shift = 3, 223 .pre_div_width = 2, 224 }, 225 .s = { 226 .src_sel_shift = 0, 227 .parent_map = gcc_pxo_pll8_map, 228 }, 229 .freq_tbl = clk_tbl_gsbi_uart, 230 .clkr = { 231 .enable_reg = 0x2a14, 232 .enable_mask = BIT(11), 233 .hw.init = &(struct clk_init_data){ 234 .name = "gsbi3_uart_src", 235 .parent_names = gcc_pxo_pll8, 236 .num_parents = 2, 237 .ops = &clk_rcg_ops, 238 .flags = CLK_SET_PARENT_GATE, 239 }, 240 }, 241}; 242 243static struct clk_branch gsbi3_uart_clk = { 244 .halt_reg = 0x2fcc, 245 .halt_bit = 2, 246 .clkr = { 247 .enable_reg = 0x2a14, 248 .enable_mask = BIT(9), 249 .hw.init = &(struct clk_init_data){ 250 .name = "gsbi3_uart_clk", 251 .parent_names = (const char *[]){ 252 "gsbi3_uart_src", 253 }, 254 .num_parents = 1, 255 .ops = &clk_branch_ops, 256 .flags = CLK_SET_RATE_PARENT, 257 }, 258 }, 259}; 260 261static struct clk_rcg gsbi4_uart_src = { 262 .ns_reg = 0x2a34, 263 .md_reg = 0x2a30, 264 .mn = { 265 .mnctr_en_bit = 8, 266 .mnctr_reset_bit = 7, 267 .mnctr_mode_shift = 5, 268 .n_val_shift = 16, 269 .m_val_shift = 16, 270 .width = 16, 271 }, 272 .p = { 273 .pre_div_shift = 3, 274 .pre_div_width = 2, 275 }, 276 .s = { 277 .src_sel_shift = 0, 278 .parent_map = gcc_pxo_pll8_map, 279 }, 280 .freq_tbl = clk_tbl_gsbi_uart, 281 .clkr = { 282 .enable_reg = 0x2a34, 283 .enable_mask = BIT(11), 284 .hw.init = &(struct clk_init_data){ 285 .name = "gsbi4_uart_src", 286 .parent_names = gcc_pxo_pll8, 287 .num_parents = 2, 288 .ops = &clk_rcg_ops, 289 .flags = CLK_SET_PARENT_GATE, 290 }, 291 }, 292}; 293 294static struct clk_branch gsbi4_uart_clk = { 295 .halt_reg = 0x2fd0, 296 .halt_bit = 26, 297 .clkr = { 298 .enable_reg = 0x2a34, 299 .enable_mask = BIT(9), 300 .hw.init = &(struct clk_init_data){ 301 .name = "gsbi4_uart_clk", 302 .parent_names = (const char *[]){ 303 "gsbi4_uart_src", 304 }, 305 .num_parents = 1, 306 .ops = &clk_branch_ops, 307 .flags = CLK_SET_RATE_PARENT, 308 }, 309 }, 310}; 311 312static struct clk_rcg gsbi5_uart_src = { 313 .ns_reg = 0x2a54, 314 .md_reg = 0x2a50, 315 .mn = { 316 .mnctr_en_bit = 8, 317 .mnctr_reset_bit = 7, 318 .mnctr_mode_shift = 5, 319 .n_val_shift = 16, 320 .m_val_shift = 16, 321 .width = 16, 322 }, 323 .p = { 324 .pre_div_shift = 3, 325 .pre_div_width = 2, 326 }, 327 .s = { 328 .src_sel_shift = 0, 329 .parent_map = gcc_pxo_pll8_map, 330 }, 331 .freq_tbl = clk_tbl_gsbi_uart, 332 .clkr = { 333 .enable_reg = 0x2a54, 334 .enable_mask = BIT(11), 335 .hw.init = &(struct clk_init_data){ 336 .name = "gsbi5_uart_src", 337 .parent_names = gcc_pxo_pll8, 338 .num_parents = 2, 339 .ops = &clk_rcg_ops, 340 .flags = CLK_SET_PARENT_GATE, 341 }, 342 }, 343}; 344 345static struct clk_branch gsbi5_uart_clk = { 346 .halt_reg = 0x2fd0, 347 .halt_bit = 22, 348 .clkr = { 349 .enable_reg = 0x2a54, 350 .enable_mask = BIT(9), 351 .hw.init = &(struct clk_init_data){ 352 .name = "gsbi5_uart_clk", 353 .parent_names = (const char *[]){ 354 "gsbi5_uart_src", 355 }, 356 .num_parents = 1, 357 .ops = &clk_branch_ops, 358 .flags = CLK_SET_RATE_PARENT, 359 }, 360 }, 361}; 362 363static struct clk_rcg gsbi6_uart_src = { 364 .ns_reg = 0x2a74, 365 .md_reg = 0x2a70, 366 .mn = { 367 .mnctr_en_bit = 8, 368 .mnctr_reset_bit = 7, 369 .mnctr_mode_shift = 5, 370 .n_val_shift = 16, 371 .m_val_shift = 16, 372 .width = 16, 373 }, 374 .p = { 375 .pre_div_shift = 3, 376 .pre_div_width = 2, 377 }, 378 .s = { 379 .src_sel_shift = 0, 380 .parent_map = gcc_pxo_pll8_map, 381 }, 382 .freq_tbl = clk_tbl_gsbi_uart, 383 .clkr = { 384 .enable_reg = 0x2a74, 385 .enable_mask = BIT(11), 386 .hw.init = &(struct clk_init_data){ 387 .name = "gsbi6_uart_src", 388 .parent_names = gcc_pxo_pll8, 389 .num_parents = 2, 390 .ops = &clk_rcg_ops, 391 .flags = CLK_SET_PARENT_GATE, 392 }, 393 }, 394}; 395 396static struct clk_branch gsbi6_uart_clk = { 397 .halt_reg = 0x2fd0, 398 .halt_bit = 18, 399 .clkr = { 400 .enable_reg = 0x2a74, 401 .enable_mask = BIT(9), 402 .hw.init = &(struct clk_init_data){ 403 .name = "gsbi6_uart_clk", 404 .parent_names = (const char *[]){ 405 "gsbi6_uart_src", 406 }, 407 .num_parents = 1, 408 .ops = &clk_branch_ops, 409 .flags = CLK_SET_RATE_PARENT, 410 }, 411 }, 412}; 413 414static struct clk_rcg gsbi7_uart_src = { 415 .ns_reg = 0x2a94, 416 .md_reg = 0x2a90, 417 .mn = { 418 .mnctr_en_bit = 8, 419 .mnctr_reset_bit = 7, 420 .mnctr_mode_shift = 5, 421 .n_val_shift = 16, 422 .m_val_shift = 16, 423 .width = 16, 424 }, 425 .p = { 426 .pre_div_shift = 3, 427 .pre_div_width = 2, 428 }, 429 .s = { 430 .src_sel_shift = 0, 431 .parent_map = gcc_pxo_pll8_map, 432 }, 433 .freq_tbl = clk_tbl_gsbi_uart, 434 .clkr = { 435 .enable_reg = 0x2a94, 436 .enable_mask = BIT(11), 437 .hw.init = &(struct clk_init_data){ 438 .name = "gsbi7_uart_src", 439 .parent_names = gcc_pxo_pll8, 440 .num_parents = 2, 441 .ops = &clk_rcg_ops, 442 .flags = CLK_SET_PARENT_GATE, 443 }, 444 }, 445}; 446 447static struct clk_branch gsbi7_uart_clk = { 448 .halt_reg = 0x2fd0, 449 .halt_bit = 14, 450 .clkr = { 451 .enable_reg = 0x2a94, 452 .enable_mask = BIT(9), 453 .hw.init = &(struct clk_init_data){ 454 .name = "gsbi7_uart_clk", 455 .parent_names = (const char *[]){ 456 "gsbi7_uart_src", 457 }, 458 .num_parents = 1, 459 .ops = &clk_branch_ops, 460 .flags = CLK_SET_RATE_PARENT, 461 }, 462 }, 463}; 464 465static struct clk_rcg gsbi8_uart_src = { 466 .ns_reg = 0x2ab4, 467 .md_reg = 0x2ab0, 468 .mn = { 469 .mnctr_en_bit = 8, 470 .mnctr_reset_bit = 7, 471 .mnctr_mode_shift = 5, 472 .n_val_shift = 16, 473 .m_val_shift = 16, 474 .width = 16, 475 }, 476 .p = { 477 .pre_div_shift = 3, 478 .pre_div_width = 2, 479 }, 480 .s = { 481 .src_sel_shift = 0, 482 .parent_map = gcc_pxo_pll8_map, 483 }, 484 .freq_tbl = clk_tbl_gsbi_uart, 485 .clkr = { 486 .enable_reg = 0x2ab4, 487 .enable_mask = BIT(11), 488 .hw.init = &(struct clk_init_data){ 489 .name = "gsbi8_uart_src", 490 .parent_names = gcc_pxo_pll8, 491 .num_parents = 2, 492 .ops = &clk_rcg_ops, 493 .flags = CLK_SET_PARENT_GATE, 494 }, 495 }, 496}; 497 498static struct clk_branch gsbi8_uart_clk = { 499 .halt_reg = 0x2fd0, 500 .halt_bit = 10, 501 .clkr = { 502 .enable_reg = 0x2ab4, 503 .enable_mask = BIT(9), 504 .hw.init = &(struct clk_init_data){ 505 .name = "gsbi8_uart_clk", 506 .parent_names = (const char *[]){ "gsbi8_uart_src" }, 507 .num_parents = 1, 508 .ops = &clk_branch_ops, 509 .flags = CLK_SET_RATE_PARENT, 510 }, 511 }, 512}; 513 514static struct clk_rcg gsbi9_uart_src = { 515 .ns_reg = 0x2ad4, 516 .md_reg = 0x2ad0, 517 .mn = { 518 .mnctr_en_bit = 8, 519 .mnctr_reset_bit = 7, 520 .mnctr_mode_shift = 5, 521 .n_val_shift = 16, 522 .m_val_shift = 16, 523 .width = 16, 524 }, 525 .p = { 526 .pre_div_shift = 3, 527 .pre_div_width = 2, 528 }, 529 .s = { 530 .src_sel_shift = 0, 531 .parent_map = gcc_pxo_pll8_map, 532 }, 533 .freq_tbl = clk_tbl_gsbi_uart, 534 .clkr = { 535 .enable_reg = 0x2ad4, 536 .enable_mask = BIT(11), 537 .hw.init = &(struct clk_init_data){ 538 .name = "gsbi9_uart_src", 539 .parent_names = gcc_pxo_pll8, 540 .num_parents = 2, 541 .ops = &clk_rcg_ops, 542 .flags = CLK_SET_PARENT_GATE, 543 }, 544 }, 545}; 546 547static struct clk_branch gsbi9_uart_clk = { 548 .halt_reg = 0x2fd0, 549 .halt_bit = 6, 550 .clkr = { 551 .enable_reg = 0x2ad4, 552 .enable_mask = BIT(9), 553 .hw.init = &(struct clk_init_data){ 554 .name = "gsbi9_uart_clk", 555 .parent_names = (const char *[]){ "gsbi9_uart_src" }, 556 .num_parents = 1, 557 .ops = &clk_branch_ops, 558 .flags = CLK_SET_RATE_PARENT, 559 }, 560 }, 561}; 562 563static struct clk_rcg gsbi10_uart_src = { 564 .ns_reg = 0x2af4, 565 .md_reg = 0x2af0, 566 .mn = { 567 .mnctr_en_bit = 8, 568 .mnctr_reset_bit = 7, 569 .mnctr_mode_shift = 5, 570 .n_val_shift = 16, 571 .m_val_shift = 16, 572 .width = 16, 573 }, 574 .p = { 575 .pre_div_shift = 3, 576 .pre_div_width = 2, 577 }, 578 .s = { 579 .src_sel_shift = 0, 580 .parent_map = gcc_pxo_pll8_map, 581 }, 582 .freq_tbl = clk_tbl_gsbi_uart, 583 .clkr = { 584 .enable_reg = 0x2af4, 585 .enable_mask = BIT(11), 586 .hw.init = &(struct clk_init_data){ 587 .name = "gsbi10_uart_src", 588 .parent_names = gcc_pxo_pll8, 589 .num_parents = 2, 590 .ops = &clk_rcg_ops, 591 .flags = CLK_SET_PARENT_GATE, 592 }, 593 }, 594}; 595 596static struct clk_branch gsbi10_uart_clk = { 597 .halt_reg = 0x2fd0, 598 .halt_bit = 2, 599 .clkr = { 600 .enable_reg = 0x2af4, 601 .enable_mask = BIT(9), 602 .hw.init = &(struct clk_init_data){ 603 .name = "gsbi10_uart_clk", 604 .parent_names = (const char *[]){ "gsbi10_uart_src" }, 605 .num_parents = 1, 606 .ops = &clk_branch_ops, 607 .flags = CLK_SET_RATE_PARENT, 608 }, 609 }, 610}; 611 612static struct clk_rcg gsbi11_uart_src = { 613 .ns_reg = 0x2b14, 614 .md_reg = 0x2b10, 615 .mn = { 616 .mnctr_en_bit = 8, 617 .mnctr_reset_bit = 7, 618 .mnctr_mode_shift = 5, 619 .n_val_shift = 16, 620 .m_val_shift = 16, 621 .width = 16, 622 }, 623 .p = { 624 .pre_div_shift = 3, 625 .pre_div_width = 2, 626 }, 627 .s = { 628 .src_sel_shift = 0, 629 .parent_map = gcc_pxo_pll8_map, 630 }, 631 .freq_tbl = clk_tbl_gsbi_uart, 632 .clkr = { 633 .enable_reg = 0x2b14, 634 .enable_mask = BIT(11), 635 .hw.init = &(struct clk_init_data){ 636 .name = "gsbi11_uart_src", 637 .parent_names = gcc_pxo_pll8, 638 .num_parents = 2, 639 .ops = &clk_rcg_ops, 640 .flags = CLK_SET_PARENT_GATE, 641 }, 642 }, 643}; 644 645static struct clk_branch gsbi11_uart_clk = { 646 .halt_reg = 0x2fd4, 647 .halt_bit = 17, 648 .clkr = { 649 .enable_reg = 0x2b14, 650 .enable_mask = BIT(9), 651 .hw.init = &(struct clk_init_data){ 652 .name = "gsbi11_uart_clk", 653 .parent_names = (const char *[]){ "gsbi11_uart_src" }, 654 .num_parents = 1, 655 .ops = &clk_branch_ops, 656 .flags = CLK_SET_RATE_PARENT, 657 }, 658 }, 659}; 660 661static struct clk_rcg gsbi12_uart_src = { 662 .ns_reg = 0x2b34, 663 .md_reg = 0x2b30, 664 .mn = { 665 .mnctr_en_bit = 8, 666 .mnctr_reset_bit = 7, 667 .mnctr_mode_shift = 5, 668 .n_val_shift = 16, 669 .m_val_shift = 16, 670 .width = 16, 671 }, 672 .p = { 673 .pre_div_shift = 3, 674 .pre_div_width = 2, 675 }, 676 .s = { 677 .src_sel_shift = 0, 678 .parent_map = gcc_pxo_pll8_map, 679 }, 680 .freq_tbl = clk_tbl_gsbi_uart, 681 .clkr = { 682 .enable_reg = 0x2b34, 683 .enable_mask = BIT(11), 684 .hw.init = &(struct clk_init_data){ 685 .name = "gsbi12_uart_src", 686 .parent_names = gcc_pxo_pll8, 687 .num_parents = 2, 688 .ops = &clk_rcg_ops, 689 .flags = CLK_SET_PARENT_GATE, 690 }, 691 }, 692}; 693 694static struct clk_branch gsbi12_uart_clk = { 695 .halt_reg = 0x2fd4, 696 .halt_bit = 13, 697 .clkr = { 698 .enable_reg = 0x2b34, 699 .enable_mask = BIT(9), 700 .hw.init = &(struct clk_init_data){ 701 .name = "gsbi12_uart_clk", 702 .parent_names = (const char *[]){ "gsbi12_uart_src" }, 703 .num_parents = 1, 704 .ops = &clk_branch_ops, 705 .flags = CLK_SET_RATE_PARENT, 706 }, 707 }, 708}; 709 710static struct freq_tbl clk_tbl_gsbi_qup[] = { 711 { 1100000, P_PXO, 1, 2, 49 }, 712 { 5400000, P_PXO, 1, 1, 5 }, 713 { 10800000, P_PXO, 1, 2, 5 }, 714 { 15060000, P_PLL8, 1, 2, 51 }, 715 { 24000000, P_PLL8, 4, 1, 4 }, 716 { 25600000, P_PLL8, 1, 1, 15 }, 717 { 27000000, P_PXO, 1, 0, 0 }, 718 { 48000000, P_PLL8, 4, 1, 2 }, 719 { 51200000, P_PLL8, 1, 2, 15 }, 720 { } 721}; 722 723static struct clk_rcg gsbi1_qup_src = { 724 .ns_reg = 0x29cc, 725 .md_reg = 0x29c8, 726 .mn = { 727 .mnctr_en_bit = 8, 728 .mnctr_reset_bit = 7, 729 .mnctr_mode_shift = 5, 730 .n_val_shift = 16, 731 .m_val_shift = 16, 732 .width = 8, 733 }, 734 .p = { 735 .pre_div_shift = 3, 736 .pre_div_width = 2, 737 }, 738 .s = { 739 .src_sel_shift = 0, 740 .parent_map = gcc_pxo_pll8_map, 741 }, 742 .freq_tbl = clk_tbl_gsbi_qup, 743 .clkr = { 744 .enable_reg = 0x29cc, 745 .enable_mask = BIT(11), 746 .hw.init = &(struct clk_init_data){ 747 .name = "gsbi1_qup_src", 748 .parent_names = gcc_pxo_pll8, 749 .num_parents = 2, 750 .ops = &clk_rcg_ops, 751 .flags = CLK_SET_PARENT_GATE, 752 }, 753 }, 754}; 755 756static struct clk_branch gsbi1_qup_clk = { 757 .halt_reg = 0x2fcc, 758 .halt_bit = 9, 759 .clkr = { 760 .enable_reg = 0x29cc, 761 .enable_mask = BIT(9), 762 .hw.init = &(struct clk_init_data){ 763 .name = "gsbi1_qup_clk", 764 .parent_names = (const char *[]){ "gsbi1_qup_src" }, 765 .num_parents = 1, 766 .ops = &clk_branch_ops, 767 .flags = CLK_SET_RATE_PARENT, 768 }, 769 }, 770}; 771 772static struct clk_rcg gsbi2_qup_src = { 773 .ns_reg = 0x29ec, 774 .md_reg = 0x29e8, 775 .mn = { 776 .mnctr_en_bit = 8, 777 .mnctr_reset_bit = 7, 778 .mnctr_mode_shift = 5, 779 .n_val_shift = 16, 780 .m_val_shift = 16, 781 .width = 8, 782 }, 783 .p = { 784 .pre_div_shift = 3, 785 .pre_div_width = 2, 786 }, 787 .s = { 788 .src_sel_shift = 0, 789 .parent_map = gcc_pxo_pll8_map, 790 }, 791 .freq_tbl = clk_tbl_gsbi_qup, 792 .clkr = { 793 .enable_reg = 0x29ec, 794 .enable_mask = BIT(11), 795 .hw.init = &(struct clk_init_data){ 796 .name = "gsbi2_qup_src", 797 .parent_names = gcc_pxo_pll8, 798 .num_parents = 2, 799 .ops = &clk_rcg_ops, 800 .flags = CLK_SET_PARENT_GATE, 801 }, 802 }, 803}; 804 805static struct clk_branch gsbi2_qup_clk = { 806 .halt_reg = 0x2fcc, 807 .halt_bit = 4, 808 .clkr = { 809 .enable_reg = 0x29ec, 810 .enable_mask = BIT(9), 811 .hw.init = &(struct clk_init_data){ 812 .name = "gsbi2_qup_clk", 813 .parent_names = (const char *[]){ "gsbi2_qup_src" }, 814 .num_parents = 1, 815 .ops = &clk_branch_ops, 816 .flags = CLK_SET_RATE_PARENT, 817 }, 818 }, 819}; 820 821static struct clk_rcg gsbi3_qup_src = { 822 .ns_reg = 0x2a0c, 823 .md_reg = 0x2a08, 824 .mn = { 825 .mnctr_en_bit = 8, 826 .mnctr_reset_bit = 7, 827 .mnctr_mode_shift = 5, 828 .n_val_shift = 16, 829 .m_val_shift = 16, 830 .width = 8, 831 }, 832 .p = { 833 .pre_div_shift = 3, 834 .pre_div_width = 2, 835 }, 836 .s = { 837 .src_sel_shift = 0, 838 .parent_map = gcc_pxo_pll8_map, 839 }, 840 .freq_tbl = clk_tbl_gsbi_qup, 841 .clkr = { 842 .enable_reg = 0x2a0c, 843 .enable_mask = BIT(11), 844 .hw.init = &(struct clk_init_data){ 845 .name = "gsbi3_qup_src", 846 .parent_names = gcc_pxo_pll8, 847 .num_parents = 2, 848 .ops = &clk_rcg_ops, 849 .flags = CLK_SET_PARENT_GATE, 850 }, 851 }, 852}; 853 854static struct clk_branch gsbi3_qup_clk = { 855 .halt_reg = 0x2fcc, 856 .halt_bit = 0, 857 .clkr = { 858 .enable_reg = 0x2a0c, 859 .enable_mask = BIT(9), 860 .hw.init = &(struct clk_init_data){ 861 .name = "gsbi3_qup_clk", 862 .parent_names = (const char *[]){ "gsbi3_qup_src" }, 863 .num_parents = 1, 864 .ops = &clk_branch_ops, 865 .flags = CLK_SET_RATE_PARENT, 866 }, 867 }, 868}; 869 870static struct clk_rcg gsbi4_qup_src = { 871 .ns_reg = 0x2a2c, 872 .md_reg = 0x2a28, 873 .mn = { 874 .mnctr_en_bit = 8, 875 .mnctr_reset_bit = 7, 876 .mnctr_mode_shift = 5, 877 .n_val_shift = 16, 878 .m_val_shift = 16, 879 .width = 8, 880 }, 881 .p = { 882 .pre_div_shift = 3, 883 .pre_div_width = 2, 884 }, 885 .s = { 886 .src_sel_shift = 0, 887 .parent_map = gcc_pxo_pll8_map, 888 }, 889 .freq_tbl = clk_tbl_gsbi_qup, 890 .clkr = { 891 .enable_reg = 0x2a2c, 892 .enable_mask = BIT(11), 893 .hw.init = &(struct clk_init_data){ 894 .name = "gsbi4_qup_src", 895 .parent_names = gcc_pxo_pll8, 896 .num_parents = 2, 897 .ops = &clk_rcg_ops, 898 .flags = CLK_SET_PARENT_GATE, 899 }, 900 }, 901}; 902 903static struct clk_branch gsbi4_qup_clk = { 904 .halt_reg = 0x2fd0, 905 .halt_bit = 24, 906 .clkr = { 907 .enable_reg = 0x2a2c, 908 .enable_mask = BIT(9), 909 .hw.init = &(struct clk_init_data){ 910 .name = "gsbi4_qup_clk", 911 .parent_names = (const char *[]){ "gsbi4_qup_src" }, 912 .num_parents = 1, 913 .ops = &clk_branch_ops, 914 .flags = CLK_SET_RATE_PARENT, 915 }, 916 }, 917}; 918 919static struct clk_rcg gsbi5_qup_src = { 920 .ns_reg = 0x2a4c, 921 .md_reg = 0x2a48, 922 .mn = { 923 .mnctr_en_bit = 8, 924 .mnctr_reset_bit = 7, 925 .mnctr_mode_shift = 5, 926 .n_val_shift = 16, 927 .m_val_shift = 16, 928 .width = 8, 929 }, 930 .p = { 931 .pre_div_shift = 3, 932 .pre_div_width = 2, 933 }, 934 .s = { 935 .src_sel_shift = 0, 936 .parent_map = gcc_pxo_pll8_map, 937 }, 938 .freq_tbl = clk_tbl_gsbi_qup, 939 .clkr = { 940 .enable_reg = 0x2a4c, 941 .enable_mask = BIT(11), 942 .hw.init = &(struct clk_init_data){ 943 .name = "gsbi5_qup_src", 944 .parent_names = gcc_pxo_pll8, 945 .num_parents = 2, 946 .ops = &clk_rcg_ops, 947 .flags = CLK_SET_PARENT_GATE, 948 }, 949 }, 950}; 951 952static struct clk_branch gsbi5_qup_clk = { 953 .halt_reg = 0x2fd0, 954 .halt_bit = 20, 955 .clkr = { 956 .enable_reg = 0x2a4c, 957 .enable_mask = BIT(9), 958 .hw.init = &(struct clk_init_data){ 959 .name = "gsbi5_qup_clk", 960 .parent_names = (const char *[]){ "gsbi5_qup_src" }, 961 .num_parents = 1, 962 .ops = &clk_branch_ops, 963 .flags = CLK_SET_RATE_PARENT, 964 }, 965 }, 966}; 967 968static struct clk_rcg gsbi6_qup_src = { 969 .ns_reg = 0x2a6c, 970 .md_reg = 0x2a68, 971 .mn = { 972 .mnctr_en_bit = 8, 973 .mnctr_reset_bit = 7, 974 .mnctr_mode_shift = 5, 975 .n_val_shift = 16, 976 .m_val_shift = 16, 977 .width = 8, 978 }, 979 .p = { 980 .pre_div_shift = 3, 981 .pre_div_width = 2, 982 }, 983 .s = { 984 .src_sel_shift = 0, 985 .parent_map = gcc_pxo_pll8_map, 986 }, 987 .freq_tbl = clk_tbl_gsbi_qup, 988 .clkr = { 989 .enable_reg = 0x2a6c, 990 .enable_mask = BIT(11), 991 .hw.init = &(struct clk_init_data){ 992 .name = "gsbi6_qup_src", 993 .parent_names = gcc_pxo_pll8, 994 .num_parents = 2, 995 .ops = &clk_rcg_ops, 996 .flags = CLK_SET_PARENT_GATE, 997 }, 998 }, 999}; 1000 1001static struct clk_branch gsbi6_qup_clk = { 1002 .halt_reg = 0x2fd0, 1003 .halt_bit = 16, 1004 .clkr = { 1005 .enable_reg = 0x2a6c, 1006 .enable_mask = BIT(9), 1007 .hw.init = &(struct clk_init_data){ 1008 .name = "gsbi6_qup_clk", 1009 .parent_names = (const char *[]){ "gsbi6_qup_src" }, 1010 .num_parents = 1, 1011 .ops = &clk_branch_ops, 1012 .flags = CLK_SET_RATE_PARENT, 1013 }, 1014 }, 1015}; 1016 1017static struct clk_rcg gsbi7_qup_src = { 1018 .ns_reg = 0x2a8c, 1019 .md_reg = 0x2a88, 1020 .mn = { 1021 .mnctr_en_bit = 8, 1022 .mnctr_reset_bit = 7, 1023 .mnctr_mode_shift = 5, 1024 .n_val_shift = 16, 1025 .m_val_shift = 16, 1026 .width = 8, 1027 }, 1028 .p = { 1029 .pre_div_shift = 3, 1030 .pre_div_width = 2, 1031 }, 1032 .s = { 1033 .src_sel_shift = 0, 1034 .parent_map = gcc_pxo_pll8_map, 1035 }, 1036 .freq_tbl = clk_tbl_gsbi_qup, 1037 .clkr = { 1038 .enable_reg = 0x2a8c, 1039 .enable_mask = BIT(11), 1040 .hw.init = &(struct clk_init_data){ 1041 .name = "gsbi7_qup_src", 1042 .parent_names = gcc_pxo_pll8, 1043 .num_parents = 2, 1044 .ops = &clk_rcg_ops, 1045 .flags = CLK_SET_PARENT_GATE, 1046 }, 1047 }, 1048}; 1049 1050static struct clk_branch gsbi7_qup_clk = { 1051 .halt_reg = 0x2fd0, 1052 .halt_bit = 12, 1053 .clkr = { 1054 .enable_reg = 0x2a8c, 1055 .enable_mask = BIT(9), 1056 .hw.init = &(struct clk_init_data){ 1057 .name = "gsbi7_qup_clk", 1058 .parent_names = (const char *[]){ "gsbi7_qup_src" }, 1059 .num_parents = 1, 1060 .ops = &clk_branch_ops, 1061 .flags = CLK_SET_RATE_PARENT, 1062 }, 1063 }, 1064}; 1065 1066static struct clk_rcg gsbi8_qup_src = { 1067 .ns_reg = 0x2aac, 1068 .md_reg = 0x2aa8, 1069 .mn = { 1070 .mnctr_en_bit = 8, 1071 .mnctr_reset_bit = 7, 1072 .mnctr_mode_shift = 5, 1073 .n_val_shift = 16, 1074 .m_val_shift = 16, 1075 .width = 8, 1076 }, 1077 .p = { 1078 .pre_div_shift = 3, 1079 .pre_div_width = 2, 1080 }, 1081 .s = { 1082 .src_sel_shift = 0, 1083 .parent_map = gcc_pxo_pll8_map, 1084 }, 1085 .freq_tbl = clk_tbl_gsbi_qup, 1086 .clkr = { 1087 .enable_reg = 0x2aac, 1088 .enable_mask = BIT(11), 1089 .hw.init = &(struct clk_init_data){ 1090 .name = "gsbi8_qup_src", 1091 .parent_names = gcc_pxo_pll8, 1092 .num_parents = 2, 1093 .ops = &clk_rcg_ops, 1094 .flags = CLK_SET_PARENT_GATE, 1095 }, 1096 }, 1097}; 1098 1099static struct clk_branch gsbi8_qup_clk = { 1100 .halt_reg = 0x2fd0, 1101 .halt_bit = 8, 1102 .clkr = { 1103 .enable_reg = 0x2aac, 1104 .enable_mask = BIT(9), 1105 .hw.init = &(struct clk_init_data){ 1106 .name = "gsbi8_qup_clk", 1107 .parent_names = (const char *[]){ "gsbi8_qup_src" }, 1108 .num_parents = 1, 1109 .ops = &clk_branch_ops, 1110 .flags = CLK_SET_RATE_PARENT, 1111 }, 1112 }, 1113}; 1114 1115static struct clk_rcg gsbi9_qup_src = { 1116 .ns_reg = 0x2acc, 1117 .md_reg = 0x2ac8, 1118 .mn = { 1119 .mnctr_en_bit = 8, 1120 .mnctr_reset_bit = 7, 1121 .mnctr_mode_shift = 5, 1122 .n_val_shift = 16, 1123 .m_val_shift = 16, 1124 .width = 8, 1125 }, 1126 .p = { 1127 .pre_div_shift = 3, 1128 .pre_div_width = 2, 1129 }, 1130 .s = { 1131 .src_sel_shift = 0, 1132 .parent_map = gcc_pxo_pll8_map, 1133 }, 1134 .freq_tbl = clk_tbl_gsbi_qup, 1135 .clkr = { 1136 .enable_reg = 0x2acc, 1137 .enable_mask = BIT(11), 1138 .hw.init = &(struct clk_init_data){ 1139 .name = "gsbi9_qup_src", 1140 .parent_names = gcc_pxo_pll8, 1141 .num_parents = 2, 1142 .ops = &clk_rcg_ops, 1143 .flags = CLK_SET_PARENT_GATE, 1144 }, 1145 }, 1146}; 1147 1148static struct clk_branch gsbi9_qup_clk = { 1149 .halt_reg = 0x2fd0, 1150 .halt_bit = 4, 1151 .clkr = { 1152 .enable_reg = 0x2acc, 1153 .enable_mask = BIT(9), 1154 .hw.init = &(struct clk_init_data){ 1155 .name = "gsbi9_qup_clk", 1156 .parent_names = (const char *[]){ "gsbi9_qup_src" }, 1157 .num_parents = 1, 1158 .ops = &clk_branch_ops, 1159 .flags = CLK_SET_RATE_PARENT, 1160 }, 1161 }, 1162}; 1163 1164static struct clk_rcg gsbi10_qup_src = { 1165 .ns_reg = 0x2aec, 1166 .md_reg = 0x2ae8, 1167 .mn = { 1168 .mnctr_en_bit = 8, 1169 .mnctr_reset_bit = 7, 1170 .mnctr_mode_shift = 5, 1171 .n_val_shift = 16, 1172 .m_val_shift = 16, 1173 .width = 8, 1174 }, 1175 .p = { 1176 .pre_div_shift = 3, 1177 .pre_div_width = 2, 1178 }, 1179 .s = { 1180 .src_sel_shift = 0, 1181 .parent_map = gcc_pxo_pll8_map, 1182 }, 1183 .freq_tbl = clk_tbl_gsbi_qup, 1184 .clkr = { 1185 .enable_reg = 0x2aec, 1186 .enable_mask = BIT(11), 1187 .hw.init = &(struct clk_init_data){ 1188 .name = "gsbi10_qup_src", 1189 .parent_names = gcc_pxo_pll8, 1190 .num_parents = 2, 1191 .ops = &clk_rcg_ops, 1192 .flags = CLK_SET_PARENT_GATE, 1193 }, 1194 }, 1195}; 1196 1197static struct clk_branch gsbi10_qup_clk = { 1198 .halt_reg = 0x2fd0, 1199 .halt_bit = 0, 1200 .clkr = { 1201 .enable_reg = 0x2aec, 1202 .enable_mask = BIT(9), 1203 .hw.init = &(struct clk_init_data){ 1204 .name = "gsbi10_qup_clk", 1205 .parent_names = (const char *[]){ "gsbi10_qup_src" }, 1206 .num_parents = 1, 1207 .ops = &clk_branch_ops, 1208 .flags = CLK_SET_RATE_PARENT, 1209 }, 1210 }, 1211}; 1212 1213static struct clk_rcg gsbi11_qup_src = { 1214 .ns_reg = 0x2b0c, 1215 .md_reg = 0x2b08, 1216 .mn = { 1217 .mnctr_en_bit = 8, 1218 .mnctr_reset_bit = 7, 1219 .mnctr_mode_shift = 5, 1220 .n_val_shift = 16, 1221 .m_val_shift = 16, 1222 .width = 8, 1223 }, 1224 .p = { 1225 .pre_div_shift = 3, 1226 .pre_div_width = 2, 1227 }, 1228 .s = { 1229 .src_sel_shift = 0, 1230 .parent_map = gcc_pxo_pll8_map, 1231 }, 1232 .freq_tbl = clk_tbl_gsbi_qup, 1233 .clkr = { 1234 .enable_reg = 0x2b0c, 1235 .enable_mask = BIT(11), 1236 .hw.init = &(struct clk_init_data){ 1237 .name = "gsbi11_qup_src", 1238 .parent_names = gcc_pxo_pll8, 1239 .num_parents = 2, 1240 .ops = &clk_rcg_ops, 1241 .flags = CLK_SET_PARENT_GATE, 1242 }, 1243 }, 1244}; 1245 1246static struct clk_branch gsbi11_qup_clk = { 1247 .halt_reg = 0x2fd4, 1248 .halt_bit = 15, 1249 .clkr = { 1250 .enable_reg = 0x2b0c, 1251 .enable_mask = BIT(9), 1252 .hw.init = &(struct clk_init_data){ 1253 .name = "gsbi11_qup_clk", 1254 .parent_names = (const char *[]){ "gsbi11_qup_src" }, 1255 .num_parents = 1, 1256 .ops = &clk_branch_ops, 1257 .flags = CLK_SET_RATE_PARENT, 1258 }, 1259 }, 1260}; 1261 1262static struct clk_rcg gsbi12_qup_src = { 1263 .ns_reg = 0x2b2c, 1264 .md_reg = 0x2b28, 1265 .mn = { 1266 .mnctr_en_bit = 8, 1267 .mnctr_reset_bit = 7, 1268 .mnctr_mode_shift = 5, 1269 .n_val_shift = 16, 1270 .m_val_shift = 16, 1271 .width = 8, 1272 }, 1273 .p = { 1274 .pre_div_shift = 3, 1275 .pre_div_width = 2, 1276 }, 1277 .s = { 1278 .src_sel_shift = 0, 1279 .parent_map = gcc_pxo_pll8_map, 1280 }, 1281 .freq_tbl = clk_tbl_gsbi_qup, 1282 .clkr = { 1283 .enable_reg = 0x2b2c, 1284 .enable_mask = BIT(11), 1285 .hw.init = &(struct clk_init_data){ 1286 .name = "gsbi12_qup_src", 1287 .parent_names = gcc_pxo_pll8, 1288 .num_parents = 2, 1289 .ops = &clk_rcg_ops, 1290 .flags = CLK_SET_PARENT_GATE, 1291 }, 1292 }, 1293}; 1294 1295static struct clk_branch gsbi12_qup_clk = { 1296 .halt_reg = 0x2fd4, 1297 .halt_bit = 11, 1298 .clkr = { 1299 .enable_reg = 0x2b2c, 1300 .enable_mask = BIT(9), 1301 .hw.init = &(struct clk_init_data){ 1302 .name = "gsbi12_qup_clk", 1303 .parent_names = (const char *[]){ "gsbi12_qup_src" }, 1304 .num_parents = 1, 1305 .ops = &clk_branch_ops, 1306 .flags = CLK_SET_RATE_PARENT, 1307 }, 1308 }, 1309}; 1310 1311static const struct freq_tbl clk_tbl_gp[] = { 1312 { 9600000, P_CXO, 2, 0, 0 }, 1313 { 13500000, P_PXO, 2, 0, 0 }, 1314 { 19200000, P_CXO, 1, 0, 0 }, 1315 { 27000000, P_PXO, 1, 0, 0 }, 1316 { 64000000, P_PLL8, 2, 1, 3 }, 1317 { 76800000, P_PLL8, 1, 1, 5 }, 1318 { 96000000, P_PLL8, 4, 0, 0 }, 1319 { 128000000, P_PLL8, 3, 0, 0 }, 1320 { 192000000, P_PLL8, 2, 0, 0 }, 1321 { } 1322}; 1323 1324static struct clk_rcg gp0_src = { 1325 .ns_reg = 0x2d24, 1326 .md_reg = 0x2d00, 1327 .mn = { 1328 .mnctr_en_bit = 8, 1329 .mnctr_reset_bit = 7, 1330 .mnctr_mode_shift = 5, 1331 .n_val_shift = 16, 1332 .m_val_shift = 16, 1333 .width = 8, 1334 }, 1335 .p = { 1336 .pre_div_shift = 3, 1337 .pre_div_width = 2, 1338 }, 1339 .s = { 1340 .src_sel_shift = 0, 1341 .parent_map = gcc_pxo_pll8_cxo_map, 1342 }, 1343 .freq_tbl = clk_tbl_gp, 1344 .clkr = { 1345 .enable_reg = 0x2d24, 1346 .enable_mask = BIT(11), 1347 .hw.init = &(struct clk_init_data){ 1348 .name = "gp0_src", 1349 .parent_names = gcc_pxo_pll8_cxo, 1350 .num_parents = 3, 1351 .ops = &clk_rcg_ops, 1352 .flags = CLK_SET_PARENT_GATE, 1353 }, 1354 } 1355}; 1356 1357static struct clk_branch gp0_clk = { 1358 .halt_reg = 0x2fd8, 1359 .halt_bit = 7, 1360 .clkr = { 1361 .enable_reg = 0x2d24, 1362 .enable_mask = BIT(9), 1363 .hw.init = &(struct clk_init_data){ 1364 .name = "gp0_clk", 1365 .parent_names = (const char *[]){ "gp0_src" }, 1366 .num_parents = 1, 1367 .ops = &clk_branch_ops, 1368 .flags = CLK_SET_RATE_PARENT, 1369 }, 1370 }, 1371}; 1372 1373static struct clk_rcg gp1_src = { 1374 .ns_reg = 0x2d44, 1375 .md_reg = 0x2d40, 1376 .mn = { 1377 .mnctr_en_bit = 8, 1378 .mnctr_reset_bit = 7, 1379 .mnctr_mode_shift = 5, 1380 .n_val_shift = 16, 1381 .m_val_shift = 16, 1382 .width = 8, 1383 }, 1384 .p = { 1385 .pre_div_shift = 3, 1386 .pre_div_width = 2, 1387 }, 1388 .s = { 1389 .src_sel_shift = 0, 1390 .parent_map = gcc_pxo_pll8_cxo_map, 1391 }, 1392 .freq_tbl = clk_tbl_gp, 1393 .clkr = { 1394 .enable_reg = 0x2d44, 1395 .enable_mask = BIT(11), 1396 .hw.init = &(struct clk_init_data){ 1397 .name = "gp1_src", 1398 .parent_names = gcc_pxo_pll8_cxo, 1399 .num_parents = 3, 1400 .ops = &clk_rcg_ops, 1401 .flags = CLK_SET_RATE_GATE, 1402 }, 1403 } 1404}; 1405 1406static struct clk_branch gp1_clk = { 1407 .halt_reg = 0x2fd8, 1408 .halt_bit = 6, 1409 .clkr = { 1410 .enable_reg = 0x2d44, 1411 .enable_mask = BIT(9), 1412 .hw.init = &(struct clk_init_data){ 1413 .name = "gp1_clk", 1414 .parent_names = (const char *[]){ "gp1_src" }, 1415 .num_parents = 1, 1416 .ops = &clk_branch_ops, 1417 .flags = CLK_SET_RATE_PARENT, 1418 }, 1419 }, 1420}; 1421 1422static struct clk_rcg gp2_src = { 1423 .ns_reg = 0x2d64, 1424 .md_reg = 0x2d60, 1425 .mn = { 1426 .mnctr_en_bit = 8, 1427 .mnctr_reset_bit = 7, 1428 .mnctr_mode_shift = 5, 1429 .n_val_shift = 16, 1430 .m_val_shift = 16, 1431 .width = 8, 1432 }, 1433 .p = { 1434 .pre_div_shift = 3, 1435 .pre_div_width = 2, 1436 }, 1437 .s = { 1438 .src_sel_shift = 0, 1439 .parent_map = gcc_pxo_pll8_cxo_map, 1440 }, 1441 .freq_tbl = clk_tbl_gp, 1442 .clkr = { 1443 .enable_reg = 0x2d64, 1444 .enable_mask = BIT(11), 1445 .hw.init = &(struct clk_init_data){ 1446 .name = "gp2_src", 1447 .parent_names = gcc_pxo_pll8_cxo, 1448 .num_parents = 3, 1449 .ops = &clk_rcg_ops, 1450 .flags = CLK_SET_RATE_GATE, 1451 }, 1452 } 1453}; 1454 1455static struct clk_branch gp2_clk = { 1456 .halt_reg = 0x2fd8, 1457 .halt_bit = 5, 1458 .clkr = { 1459 .enable_reg = 0x2d64, 1460 .enable_mask = BIT(9), 1461 .hw.init = &(struct clk_init_data){ 1462 .name = "gp2_clk", 1463 .parent_names = (const char *[]){ "gp2_src" }, 1464 .num_parents = 1, 1465 .ops = &clk_branch_ops, 1466 .flags = CLK_SET_RATE_PARENT, 1467 }, 1468 }, 1469}; 1470 1471static struct clk_branch pmem_clk = { 1472 .hwcg_reg = 0x25a0, 1473 .hwcg_bit = 6, 1474 .halt_reg = 0x2fc8, 1475 .halt_bit = 20, 1476 .clkr = { 1477 .enable_reg = 0x25a0, 1478 .enable_mask = BIT(4), 1479 .hw.init = &(struct clk_init_data){ 1480 .name = "pmem_clk", 1481 .ops = &clk_branch_ops, 1482 .flags = CLK_IS_ROOT, 1483 }, 1484 }, 1485}; 1486 1487static struct clk_rcg prng_src = { 1488 .ns_reg = 0x2e80, 1489 .p = { 1490 .pre_div_shift = 3, 1491 .pre_div_width = 4, 1492 }, 1493 .s = { 1494 .src_sel_shift = 0, 1495 .parent_map = gcc_pxo_pll8_map, 1496 }, 1497 .clkr.hw = { 1498 .init = &(struct clk_init_data){ 1499 .name = "prng_src", 1500 .parent_names = gcc_pxo_pll8, 1501 .num_parents = 2, 1502 .ops = &clk_rcg_ops, 1503 }, 1504 }, 1505}; 1506 1507static struct clk_branch prng_clk = { 1508 .halt_reg = 0x2fd8, 1509 .halt_check = BRANCH_HALT_VOTED, 1510 .halt_bit = 10, 1511 .clkr = { 1512 .enable_reg = 0x3080, 1513 .enable_mask = BIT(10), 1514 .hw.init = &(struct clk_init_data){ 1515 .name = "prng_clk", 1516 .parent_names = (const char *[]){ "prng_src" }, 1517 .num_parents = 1, 1518 .ops = &clk_branch_ops, 1519 }, 1520 }, 1521}; 1522 1523static const struct freq_tbl clk_tbl_sdc[] = { 1524 { 144000, P_PXO, 3, 2, 125 }, 1525 { 400000, P_PLL8, 4, 1, 240 }, 1526 { 16000000, P_PLL8, 4, 1, 6 }, 1527 { 17070000, P_PLL8, 1, 2, 45 }, 1528 { 20210000, P_PLL8, 1, 1, 19 }, 1529 { 24000000, P_PLL8, 4, 1, 4 }, 1530 { 48000000, P_PLL8, 4, 1, 2 }, 1531 { } 1532}; 1533 1534static struct clk_rcg sdc1_src = { 1535 .ns_reg = 0x282c, 1536 .md_reg = 0x2828, 1537 .mn = { 1538 .mnctr_en_bit = 8, 1539 .mnctr_reset_bit = 7, 1540 .mnctr_mode_shift = 5, 1541 .n_val_shift = 16, 1542 .m_val_shift = 16, 1543 .width = 8, 1544 }, 1545 .p = { 1546 .pre_div_shift = 3, 1547 .pre_div_width = 2, 1548 }, 1549 .s = { 1550 .src_sel_shift = 0, 1551 .parent_map = gcc_pxo_pll8_map, 1552 }, 1553 .freq_tbl = clk_tbl_sdc, 1554 .clkr = { 1555 .enable_reg = 0x282c, 1556 .enable_mask = BIT(11), 1557 .hw.init = &(struct clk_init_data){ 1558 .name = "sdc1_src", 1559 .parent_names = gcc_pxo_pll8, 1560 .num_parents = 2, 1561 .ops = &clk_rcg_ops, 1562 .flags = CLK_SET_RATE_GATE, 1563 }, 1564 } 1565}; 1566 1567static struct clk_branch sdc1_clk = { 1568 .halt_reg = 0x2fc8, 1569 .halt_bit = 6, 1570 .clkr = { 1571 .enable_reg = 0x282c, 1572 .enable_mask = BIT(9), 1573 .hw.init = &(struct clk_init_data){ 1574 .name = "sdc1_clk", 1575 .parent_names = (const char *[]){ "sdc1_src" }, 1576 .num_parents = 1, 1577 .ops = &clk_branch_ops, 1578 .flags = CLK_SET_RATE_PARENT, 1579 }, 1580 }, 1581}; 1582 1583static struct clk_rcg sdc2_src = { 1584 .ns_reg = 0x284c, 1585 .md_reg = 0x2848, 1586 .mn = { 1587 .mnctr_en_bit = 8, 1588 .mnctr_reset_bit = 7, 1589 .mnctr_mode_shift = 5, 1590 .n_val_shift = 16, 1591 .m_val_shift = 16, 1592 .width = 8, 1593 }, 1594 .p = { 1595 .pre_div_shift = 3, 1596 .pre_div_width = 2, 1597 }, 1598 .s = { 1599 .src_sel_shift = 0, 1600 .parent_map = gcc_pxo_pll8_map, 1601 }, 1602 .freq_tbl = clk_tbl_sdc, 1603 .clkr = { 1604 .enable_reg = 0x284c, 1605 .enable_mask = BIT(11), 1606 .hw.init = &(struct clk_init_data){ 1607 .name = "sdc2_src", 1608 .parent_names = gcc_pxo_pll8, 1609 .num_parents = 2, 1610 .ops = &clk_rcg_ops, 1611 .flags = CLK_SET_RATE_GATE, 1612 }, 1613 } 1614}; 1615 1616static struct clk_branch sdc2_clk = { 1617 .halt_reg = 0x2fc8, 1618 .halt_bit = 5, 1619 .clkr = { 1620 .enable_reg = 0x284c, 1621 .enable_mask = BIT(9), 1622 .hw.init = &(struct clk_init_data){ 1623 .name = "sdc2_clk", 1624 .parent_names = (const char *[]){ "sdc2_src" }, 1625 .num_parents = 1, 1626 .ops = &clk_branch_ops, 1627 .flags = CLK_SET_RATE_PARENT, 1628 }, 1629 }, 1630}; 1631 1632static struct clk_rcg sdc3_src = { 1633 .ns_reg = 0x286c, 1634 .md_reg = 0x2868, 1635 .mn = { 1636 .mnctr_en_bit = 8, 1637 .mnctr_reset_bit = 7, 1638 .mnctr_mode_shift = 5, 1639 .n_val_shift = 16, 1640 .m_val_shift = 16, 1641 .width = 8, 1642 }, 1643 .p = { 1644 .pre_div_shift = 3, 1645 .pre_div_width = 2, 1646 }, 1647 .s = { 1648 .src_sel_shift = 0, 1649 .parent_map = gcc_pxo_pll8_map, 1650 }, 1651 .freq_tbl = clk_tbl_sdc, 1652 .clkr = { 1653 .enable_reg = 0x286c, 1654 .enable_mask = BIT(11), 1655 .hw.init = &(struct clk_init_data){ 1656 .name = "sdc3_src", 1657 .parent_names = gcc_pxo_pll8, 1658 .num_parents = 2, 1659 .ops = &clk_rcg_ops, 1660 .flags = CLK_SET_RATE_GATE, 1661 }, 1662 } 1663}; 1664 1665static struct clk_branch sdc3_clk = { 1666 .halt_reg = 0x2fc8, 1667 .halt_bit = 4, 1668 .clkr = { 1669 .enable_reg = 0x286c, 1670 .enable_mask = BIT(9), 1671 .hw.init = &(struct clk_init_data){ 1672 .name = "sdc3_clk", 1673 .parent_names = (const char *[]){ "sdc3_src" }, 1674 .num_parents = 1, 1675 .ops = &clk_branch_ops, 1676 .flags = CLK_SET_RATE_PARENT, 1677 }, 1678 }, 1679}; 1680 1681static struct clk_rcg sdc4_src = { 1682 .ns_reg = 0x288c, 1683 .md_reg = 0x2888, 1684 .mn = { 1685 .mnctr_en_bit = 8, 1686 .mnctr_reset_bit = 7, 1687 .mnctr_mode_shift = 5, 1688 .n_val_shift = 16, 1689 .m_val_shift = 16, 1690 .width = 8, 1691 }, 1692 .p = { 1693 .pre_div_shift = 3, 1694 .pre_div_width = 2, 1695 }, 1696 .s = { 1697 .src_sel_shift = 0, 1698 .parent_map = gcc_pxo_pll8_map, 1699 }, 1700 .freq_tbl = clk_tbl_sdc, 1701 .clkr = { 1702 .enable_reg = 0x288c, 1703 .enable_mask = BIT(11), 1704 .hw.init = &(struct clk_init_data){ 1705 .name = "sdc4_src", 1706 .parent_names = gcc_pxo_pll8, 1707 .num_parents = 2, 1708 .ops = &clk_rcg_ops, 1709 .flags = CLK_SET_RATE_GATE, 1710 }, 1711 } 1712}; 1713 1714static struct clk_branch sdc4_clk = { 1715 .halt_reg = 0x2fc8, 1716 .halt_bit = 3, 1717 .clkr = { 1718 .enable_reg = 0x288c, 1719 .enable_mask = BIT(9), 1720 .hw.init = &(struct clk_init_data){ 1721 .name = "sdc4_clk", 1722 .parent_names = (const char *[]){ "sdc4_src" }, 1723 .num_parents = 1, 1724 .ops = &clk_branch_ops, 1725 .flags = CLK_SET_RATE_PARENT, 1726 }, 1727 }, 1728}; 1729 1730static struct clk_rcg sdc5_src = { 1731 .ns_reg = 0x28ac, 1732 .md_reg = 0x28a8, 1733 .mn = { 1734 .mnctr_en_bit = 8, 1735 .mnctr_reset_bit = 7, 1736 .mnctr_mode_shift = 5, 1737 .n_val_shift = 16, 1738 .m_val_shift = 16, 1739 .width = 8, 1740 }, 1741 .p = { 1742 .pre_div_shift = 3, 1743 .pre_div_width = 2, 1744 }, 1745 .s = { 1746 .src_sel_shift = 0, 1747 .parent_map = gcc_pxo_pll8_map, 1748 }, 1749 .freq_tbl = clk_tbl_sdc, 1750 .clkr = { 1751 .enable_reg = 0x28ac, 1752 .enable_mask = BIT(11), 1753 .hw.init = &(struct clk_init_data){ 1754 .name = "sdc5_src", 1755 .parent_names = gcc_pxo_pll8, 1756 .num_parents = 2, 1757 .ops = &clk_rcg_ops, 1758 .flags = CLK_SET_RATE_GATE, 1759 }, 1760 } 1761}; 1762 1763static struct clk_branch sdc5_clk = { 1764 .halt_reg = 0x2fc8, 1765 .halt_bit = 2, 1766 .clkr = { 1767 .enable_reg = 0x28ac, 1768 .enable_mask = BIT(9), 1769 .hw.init = &(struct clk_init_data){ 1770 .name = "sdc5_clk", 1771 .parent_names = (const char *[]){ "sdc5_src" }, 1772 .num_parents = 1, 1773 .ops = &clk_branch_ops, 1774 .flags = CLK_SET_RATE_PARENT, 1775 }, 1776 }, 1777}; 1778 1779static const struct freq_tbl clk_tbl_tsif_ref[] = { 1780 { 105000, P_PXO, 1, 1, 256 }, 1781 { } 1782}; 1783 1784static struct clk_rcg tsif_ref_src = { 1785 .ns_reg = 0x2710, 1786 .md_reg = 0x270c, 1787 .mn = { 1788 .mnctr_en_bit = 8, 1789 .mnctr_reset_bit = 7, 1790 .mnctr_mode_shift = 5, 1791 .n_val_shift = 16, 1792 .m_val_shift = 16, 1793 .width = 16, 1794 }, 1795 .p = { 1796 .pre_div_shift = 3, 1797 .pre_div_width = 2, 1798 }, 1799 .s = { 1800 .src_sel_shift = 0, 1801 .parent_map = gcc_pxo_pll8_map, 1802 }, 1803 .freq_tbl = clk_tbl_tsif_ref, 1804 .clkr = { 1805 .enable_reg = 0x2710, 1806 .enable_mask = BIT(11), 1807 .hw.init = &(struct clk_init_data){ 1808 .name = "tsif_ref_src", 1809 .parent_names = gcc_pxo_pll8, 1810 .num_parents = 2, 1811 .ops = &clk_rcg_ops, 1812 .flags = CLK_SET_RATE_GATE, 1813 }, 1814 } 1815}; 1816 1817static struct clk_branch tsif_ref_clk = { 1818 .halt_reg = 0x2fd4, 1819 .halt_bit = 5, 1820 .clkr = { 1821 .enable_reg = 0x2710, 1822 .enable_mask = BIT(9), 1823 .hw.init = &(struct clk_init_data){ 1824 .name = "tsif_ref_clk", 1825 .parent_names = (const char *[]){ "tsif_ref_src" }, 1826 .num_parents = 1, 1827 .ops = &clk_branch_ops, 1828 .flags = CLK_SET_RATE_PARENT, 1829 }, 1830 }, 1831}; 1832 1833static const struct freq_tbl clk_tbl_usb[] = { 1834 { 60000000, P_PLL8, 1, 5, 32 }, 1835 { } 1836}; 1837 1838static struct clk_rcg usb_hs1_xcvr_src = { 1839 .ns_reg = 0x290c, 1840 .md_reg = 0x2908, 1841 .mn = { 1842 .mnctr_en_bit = 8, 1843 .mnctr_reset_bit = 7, 1844 .mnctr_mode_shift = 5, 1845 .n_val_shift = 16, 1846 .m_val_shift = 16, 1847 .width = 8, 1848 }, 1849 .p = { 1850 .pre_div_shift = 3, 1851 .pre_div_width = 2, 1852 }, 1853 .s = { 1854 .src_sel_shift = 0, 1855 .parent_map = gcc_pxo_pll8_map, 1856 }, 1857 .freq_tbl = clk_tbl_usb, 1858 .clkr = { 1859 .enable_reg = 0x290c, 1860 .enable_mask = BIT(11), 1861 .hw.init = &(struct clk_init_data){ 1862 .name = "usb_hs1_xcvr_src", 1863 .parent_names = gcc_pxo_pll8, 1864 .num_parents = 2, 1865 .ops = &clk_rcg_ops, 1866 .flags = CLK_SET_RATE_GATE, 1867 }, 1868 } 1869}; 1870 1871static struct clk_branch usb_hs1_xcvr_clk = { 1872 .halt_reg = 0x2fc8, 1873 .halt_bit = 0, 1874 .clkr = { 1875 .enable_reg = 0x290c, 1876 .enable_mask = BIT(9), 1877 .hw.init = &(struct clk_init_data){ 1878 .name = "usb_hs1_xcvr_clk", 1879 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, 1880 .num_parents = 1, 1881 .ops = &clk_branch_ops, 1882 .flags = CLK_SET_RATE_PARENT, 1883 }, 1884 }, 1885}; 1886 1887static struct clk_rcg usb_fs1_xcvr_fs_src = { 1888 .ns_reg = 0x2968, 1889 .md_reg = 0x2964, 1890 .mn = { 1891 .mnctr_en_bit = 8, 1892 .mnctr_reset_bit = 7, 1893 .mnctr_mode_shift = 5, 1894 .n_val_shift = 16, 1895 .m_val_shift = 16, 1896 .width = 8, 1897 }, 1898 .p = { 1899 .pre_div_shift = 3, 1900 .pre_div_width = 2, 1901 }, 1902 .s = { 1903 .src_sel_shift = 0, 1904 .parent_map = gcc_pxo_pll8_map, 1905 }, 1906 .freq_tbl = clk_tbl_usb, 1907 .clkr = { 1908 .enable_reg = 0x2968, 1909 .enable_mask = BIT(11), 1910 .hw.init = &(struct clk_init_data){ 1911 .name = "usb_fs1_xcvr_fs_src", 1912 .parent_names = gcc_pxo_pll8, 1913 .num_parents = 2, 1914 .ops = &clk_rcg_ops, 1915 .flags = CLK_SET_RATE_GATE, 1916 }, 1917 } 1918}; 1919 1920static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" }; 1921 1922static struct clk_branch usb_fs1_xcvr_fs_clk = { 1923 .halt_reg = 0x2fcc, 1924 .halt_bit = 15, 1925 .clkr = { 1926 .enable_reg = 0x2968, 1927 .enable_mask = BIT(9), 1928 .hw.init = &(struct clk_init_data){ 1929 .name = "usb_fs1_xcvr_fs_clk", 1930 .parent_names = usb_fs1_xcvr_fs_src_p, 1931 .num_parents = 1, 1932 .ops = &clk_branch_ops, 1933 .flags = CLK_SET_RATE_PARENT, 1934 }, 1935 }, 1936}; 1937 1938static struct clk_branch usb_fs1_system_clk = { 1939 .halt_reg = 0x2fcc, 1940 .halt_bit = 16, 1941 .clkr = { 1942 .enable_reg = 0x296c, 1943 .enable_mask = BIT(4), 1944 .hw.init = &(struct clk_init_data){ 1945 .parent_names = usb_fs1_xcvr_fs_src_p, 1946 .num_parents = 1, 1947 .name = "usb_fs1_system_clk", 1948 .ops = &clk_branch_ops, 1949 .flags = CLK_SET_RATE_PARENT, 1950 }, 1951 }, 1952}; 1953 1954static struct clk_rcg usb_fs2_xcvr_fs_src = { 1955 .ns_reg = 0x2988, 1956 .md_reg = 0x2984, 1957 .mn = { 1958 .mnctr_en_bit = 8, 1959 .mnctr_reset_bit = 7, 1960 .mnctr_mode_shift = 5, 1961 .n_val_shift = 16, 1962 .m_val_shift = 16, 1963 .width = 8, 1964 }, 1965 .p = { 1966 .pre_div_shift = 3, 1967 .pre_div_width = 2, 1968 }, 1969 .s = { 1970 .src_sel_shift = 0, 1971 .parent_map = gcc_pxo_pll8_map, 1972 }, 1973 .freq_tbl = clk_tbl_usb, 1974 .clkr = { 1975 .enable_reg = 0x2988, 1976 .enable_mask = BIT(11), 1977 .hw.init = &(struct clk_init_data){ 1978 .name = "usb_fs2_xcvr_fs_src", 1979 .parent_names = gcc_pxo_pll8, 1980 .num_parents = 2, 1981 .ops = &clk_rcg_ops, 1982 .flags = CLK_SET_RATE_GATE, 1983 }, 1984 } 1985}; 1986 1987static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" }; 1988 1989static struct clk_branch usb_fs2_xcvr_fs_clk = { 1990 .halt_reg = 0x2fcc, 1991 .halt_bit = 12, 1992 .clkr = { 1993 .enable_reg = 0x2988, 1994 .enable_mask = BIT(9), 1995 .hw.init = &(struct clk_init_data){ 1996 .name = "usb_fs2_xcvr_fs_clk", 1997 .parent_names = usb_fs2_xcvr_fs_src_p, 1998 .num_parents = 1, 1999 .ops = &clk_branch_ops, 2000 .flags = CLK_SET_RATE_PARENT, 2001 }, 2002 }, 2003}; 2004 2005static struct clk_branch usb_fs2_system_clk = { 2006 .halt_reg = 0x2fcc, 2007 .halt_bit = 13, 2008 .clkr = { 2009 .enable_reg = 0x298c, 2010 .enable_mask = BIT(4), 2011 .hw.init = &(struct clk_init_data){ 2012 .name = "usb_fs2_system_clk", 2013 .parent_names = usb_fs2_xcvr_fs_src_p, 2014 .num_parents = 1, 2015 .ops = &clk_branch_ops, 2016 .flags = CLK_SET_RATE_PARENT, 2017 }, 2018 }, 2019}; 2020 2021static struct clk_branch gsbi1_h_clk = { 2022 .halt_reg = 0x2fcc, 2023 .halt_bit = 11, 2024 .clkr = { 2025 .enable_reg = 0x29c0, 2026 .enable_mask = BIT(4), 2027 .hw.init = &(struct clk_init_data){ 2028 .name = "gsbi1_h_clk", 2029 .ops = &clk_branch_ops, 2030 .flags = CLK_IS_ROOT, 2031 }, 2032 }, 2033}; 2034 2035static struct clk_branch gsbi2_h_clk = { 2036 .halt_reg = 0x2fcc, 2037 .halt_bit = 7, 2038 .clkr = { 2039 .enable_reg = 0x29e0, 2040 .enable_mask = BIT(4), 2041 .hw.init = &(struct clk_init_data){ 2042 .name = "gsbi2_h_clk", 2043 .ops = &clk_branch_ops, 2044 .flags = CLK_IS_ROOT, 2045 }, 2046 }, 2047}; 2048 2049static struct clk_branch gsbi3_h_clk = { 2050 .halt_reg = 0x2fcc, 2051 .halt_bit = 3, 2052 .clkr = { 2053 .enable_reg = 0x2a00, 2054 .enable_mask = BIT(4), 2055 .hw.init = &(struct clk_init_data){ 2056 .name = "gsbi3_h_clk", 2057 .ops = &clk_branch_ops, 2058 .flags = CLK_IS_ROOT, 2059 }, 2060 }, 2061}; 2062 2063static struct clk_branch gsbi4_h_clk = { 2064 .halt_reg = 0x2fd0, 2065 .halt_bit = 27, 2066 .clkr = { 2067 .enable_reg = 0x2a20, 2068 .enable_mask = BIT(4), 2069 .hw.init = &(struct clk_init_data){ 2070 .name = "gsbi4_h_clk", 2071 .ops = &clk_branch_ops, 2072 .flags = CLK_IS_ROOT, 2073 }, 2074 }, 2075}; 2076 2077static struct clk_branch gsbi5_h_clk = { 2078 .halt_reg = 0x2fd0, 2079 .halt_bit = 23, 2080 .clkr = { 2081 .enable_reg = 0x2a40, 2082 .enable_mask = BIT(4), 2083 .hw.init = &(struct clk_init_data){ 2084 .name = "gsbi5_h_clk", 2085 .ops = &clk_branch_ops, 2086 .flags = CLK_IS_ROOT, 2087 }, 2088 }, 2089}; 2090 2091static struct clk_branch gsbi6_h_clk = { 2092 .halt_reg = 0x2fd0, 2093 .halt_bit = 19, 2094 .clkr = { 2095 .enable_reg = 0x2a60, 2096 .enable_mask = BIT(4), 2097 .hw.init = &(struct clk_init_data){ 2098 .name = "gsbi6_h_clk", 2099 .ops = &clk_branch_ops, 2100 .flags = CLK_IS_ROOT, 2101 }, 2102 }, 2103}; 2104 2105static struct clk_branch gsbi7_h_clk = { 2106 .halt_reg = 0x2fd0, 2107 .halt_bit = 15, 2108 .clkr = { 2109 .enable_reg = 0x2a80, 2110 .enable_mask = BIT(4), 2111 .hw.init = &(struct clk_init_data){ 2112 .name = "gsbi7_h_clk", 2113 .ops = &clk_branch_ops, 2114 .flags = CLK_IS_ROOT, 2115 }, 2116 }, 2117}; 2118 2119static struct clk_branch gsbi8_h_clk = { 2120 .halt_reg = 0x2fd0, 2121 .halt_bit = 11, 2122 .clkr = { 2123 .enable_reg = 0x2aa0, 2124 .enable_mask = BIT(4), 2125 .hw.init = &(struct clk_init_data){ 2126 .name = "gsbi8_h_clk", 2127 .ops = &clk_branch_ops, 2128 .flags = CLK_IS_ROOT, 2129 }, 2130 }, 2131}; 2132 2133static struct clk_branch gsbi9_h_clk = { 2134 .halt_reg = 0x2fd0, 2135 .halt_bit = 7, 2136 .clkr = { 2137 .enable_reg = 0x2ac0, 2138 .enable_mask = BIT(4), 2139 .hw.init = &(struct clk_init_data){ 2140 .name = "gsbi9_h_clk", 2141 .ops = &clk_branch_ops, 2142 .flags = CLK_IS_ROOT, 2143 }, 2144 }, 2145}; 2146 2147static struct clk_branch gsbi10_h_clk = { 2148 .halt_reg = 0x2fd0, 2149 .halt_bit = 3, 2150 .clkr = { 2151 .enable_reg = 0x2ae0, 2152 .enable_mask = BIT(4), 2153 .hw.init = &(struct clk_init_data){ 2154 .name = "gsbi10_h_clk", 2155 .ops = &clk_branch_ops, 2156 .flags = CLK_IS_ROOT, 2157 }, 2158 }, 2159}; 2160 2161static struct clk_branch gsbi11_h_clk = { 2162 .halt_reg = 0x2fd4, 2163 .halt_bit = 18, 2164 .clkr = { 2165 .enable_reg = 0x2b00, 2166 .enable_mask = BIT(4), 2167 .hw.init = &(struct clk_init_data){ 2168 .name = "gsbi11_h_clk", 2169 .ops = &clk_branch_ops, 2170 .flags = CLK_IS_ROOT, 2171 }, 2172 }, 2173}; 2174 2175static struct clk_branch gsbi12_h_clk = { 2176 .halt_reg = 0x2fd4, 2177 .halt_bit = 14, 2178 .clkr = { 2179 .enable_reg = 0x2b20, 2180 .enable_mask = BIT(4), 2181 .hw.init = &(struct clk_init_data){ 2182 .name = "gsbi12_h_clk", 2183 .ops = &clk_branch_ops, 2184 .flags = CLK_IS_ROOT, 2185 }, 2186 }, 2187}; 2188 2189static struct clk_branch tsif_h_clk = { 2190 .halt_reg = 0x2fd4, 2191 .halt_bit = 7, 2192 .clkr = { 2193 .enable_reg = 0x2700, 2194 .enable_mask = BIT(4), 2195 .hw.init = &(struct clk_init_data){ 2196 .name = "tsif_h_clk", 2197 .ops = &clk_branch_ops, 2198 .flags = CLK_IS_ROOT, 2199 }, 2200 }, 2201}; 2202 2203static struct clk_branch usb_fs1_h_clk = { 2204 .halt_reg = 0x2fcc, 2205 .halt_bit = 17, 2206 .clkr = { 2207 .enable_reg = 0x2960, 2208 .enable_mask = BIT(4), 2209 .hw.init = &(struct clk_init_data){ 2210 .name = "usb_fs1_h_clk", 2211 .ops = &clk_branch_ops, 2212 .flags = CLK_IS_ROOT, 2213 }, 2214 }, 2215}; 2216 2217static struct clk_branch usb_fs2_h_clk = { 2218 .halt_reg = 0x2fcc, 2219 .halt_bit = 14, 2220 .clkr = { 2221 .enable_reg = 0x2980, 2222 .enable_mask = BIT(4), 2223 .hw.init = &(struct clk_init_data){ 2224 .name = "usb_fs2_h_clk", 2225 .ops = &clk_branch_ops, 2226 .flags = CLK_IS_ROOT, 2227 }, 2228 }, 2229}; 2230 2231static struct clk_branch usb_hs1_h_clk = { 2232 .halt_reg = 0x2fc8, 2233 .halt_bit = 1, 2234 .clkr = { 2235 .enable_reg = 0x2900, 2236 .enable_mask = BIT(4), 2237 .hw.init = &(struct clk_init_data){ 2238 .name = "usb_hs1_h_clk", 2239 .ops = &clk_branch_ops, 2240 .flags = CLK_IS_ROOT, 2241 }, 2242 }, 2243}; 2244 2245static struct clk_branch sdc1_h_clk = { 2246 .halt_reg = 0x2fc8, 2247 .halt_bit = 11, 2248 .clkr = { 2249 .enable_reg = 0x2820, 2250 .enable_mask = BIT(4), 2251 .hw.init = &(struct clk_init_data){ 2252 .name = "sdc1_h_clk", 2253 .ops = &clk_branch_ops, 2254 .flags = CLK_IS_ROOT, 2255 }, 2256 }, 2257}; 2258 2259static struct clk_branch sdc2_h_clk = { 2260 .halt_reg = 0x2fc8, 2261 .halt_bit = 10, 2262 .clkr = { 2263 .enable_reg = 0x2840, 2264 .enable_mask = BIT(4), 2265 .hw.init = &(struct clk_init_data){ 2266 .name = "sdc2_h_clk", 2267 .ops = &clk_branch_ops, 2268 .flags = CLK_IS_ROOT, 2269 }, 2270 }, 2271}; 2272 2273static struct clk_branch sdc3_h_clk = { 2274 .halt_reg = 0x2fc8, 2275 .halt_bit = 9, 2276 .clkr = { 2277 .enable_reg = 0x2860, 2278 .enable_mask = BIT(4), 2279 .hw.init = &(struct clk_init_data){ 2280 .name = "sdc3_h_clk", 2281 .ops = &clk_branch_ops, 2282 .flags = CLK_IS_ROOT, 2283 }, 2284 }, 2285}; 2286 2287static struct clk_branch sdc4_h_clk = { 2288 .halt_reg = 0x2fc8, 2289 .halt_bit = 8, 2290 .clkr = { 2291 .enable_reg = 0x2880, 2292 .enable_mask = BIT(4), 2293 .hw.init = &(struct clk_init_data){ 2294 .name = "sdc4_h_clk", 2295 .ops = &clk_branch_ops, 2296 .flags = CLK_IS_ROOT, 2297 }, 2298 }, 2299}; 2300 2301static struct clk_branch sdc5_h_clk = { 2302 .halt_reg = 0x2fc8, 2303 .halt_bit = 7, 2304 .clkr = { 2305 .enable_reg = 0x28a0, 2306 .enable_mask = BIT(4), 2307 .hw.init = &(struct clk_init_data){ 2308 .name = "sdc5_h_clk", 2309 .ops = &clk_branch_ops, 2310 .flags = CLK_IS_ROOT, 2311 }, 2312 }, 2313}; 2314 2315static struct clk_branch adm0_clk = { 2316 .halt_reg = 0x2fdc, 2317 .halt_check = BRANCH_HALT_VOTED, 2318 .halt_bit = 14, 2319 .clkr = { 2320 .enable_reg = 0x3080, 2321 .enable_mask = BIT(2), 2322 .hw.init = &(struct clk_init_data){ 2323 .name = "adm0_clk", 2324 .ops = &clk_branch_ops, 2325 .flags = CLK_IS_ROOT, 2326 }, 2327 }, 2328}; 2329 2330static struct clk_branch adm0_pbus_clk = { 2331 .halt_reg = 0x2fdc, 2332 .halt_check = BRANCH_HALT_VOTED, 2333 .halt_bit = 13, 2334 .clkr = { 2335 .enable_reg = 0x3080, 2336 .enable_mask = BIT(3), 2337 .hw.init = &(struct clk_init_data){ 2338 .name = "adm0_pbus_clk", 2339 .ops = &clk_branch_ops, 2340 .flags = CLK_IS_ROOT, 2341 }, 2342 }, 2343}; 2344 2345static struct clk_branch adm1_clk = { 2346 .halt_reg = 0x2fdc, 2347 .halt_bit = 12, 2348 .halt_check = BRANCH_HALT_VOTED, 2349 .clkr = { 2350 .enable_reg = 0x3080, 2351 .enable_mask = BIT(4), 2352 .hw.init = &(struct clk_init_data){ 2353 .name = "adm1_clk", 2354 .ops = &clk_branch_ops, 2355 .flags = CLK_IS_ROOT, 2356 }, 2357 }, 2358}; 2359 2360static struct clk_branch adm1_pbus_clk = { 2361 .halt_reg = 0x2fdc, 2362 .halt_bit = 11, 2363 .halt_check = BRANCH_HALT_VOTED, 2364 .clkr = { 2365 .enable_reg = 0x3080, 2366 .enable_mask = BIT(5), 2367 .hw.init = &(struct clk_init_data){ 2368 .name = "adm1_pbus_clk", 2369 .ops = &clk_branch_ops, 2370 .flags = CLK_IS_ROOT, 2371 }, 2372 }, 2373}; 2374 2375static struct clk_branch modem_ahb1_h_clk = { 2376 .halt_reg = 0x2fdc, 2377 .halt_bit = 8, 2378 .halt_check = BRANCH_HALT_VOTED, 2379 .clkr = { 2380 .enable_reg = 0x3080, 2381 .enable_mask = BIT(0), 2382 .hw.init = &(struct clk_init_data){ 2383 .name = "modem_ahb1_h_clk", 2384 .ops = &clk_branch_ops, 2385 .flags = CLK_IS_ROOT, 2386 }, 2387 }, 2388}; 2389 2390static struct clk_branch modem_ahb2_h_clk = { 2391 .halt_reg = 0x2fdc, 2392 .halt_bit = 7, 2393 .halt_check = BRANCH_HALT_VOTED, 2394 .clkr = { 2395 .enable_reg = 0x3080, 2396 .enable_mask = BIT(1), 2397 .hw.init = &(struct clk_init_data){ 2398 .name = "modem_ahb2_h_clk", 2399 .ops = &clk_branch_ops, 2400 .flags = CLK_IS_ROOT, 2401 }, 2402 }, 2403}; 2404 2405static struct clk_branch pmic_arb0_h_clk = { 2406 .halt_reg = 0x2fd8, 2407 .halt_check = BRANCH_HALT_VOTED, 2408 .halt_bit = 22, 2409 .clkr = { 2410 .enable_reg = 0x3080, 2411 .enable_mask = BIT(8), 2412 .hw.init = &(struct clk_init_data){ 2413 .name = "pmic_arb0_h_clk", 2414 .ops = &clk_branch_ops, 2415 .flags = CLK_IS_ROOT, 2416 }, 2417 }, 2418}; 2419 2420static struct clk_branch pmic_arb1_h_clk = { 2421 .halt_reg = 0x2fd8, 2422 .halt_check = BRANCH_HALT_VOTED, 2423 .halt_bit = 21, 2424 .clkr = { 2425 .enable_reg = 0x3080, 2426 .enable_mask = BIT(9), 2427 .hw.init = &(struct clk_init_data){ 2428 .name = "pmic_arb1_h_clk", 2429 .ops = &clk_branch_ops, 2430 .flags = CLK_IS_ROOT, 2431 }, 2432 }, 2433}; 2434 2435static struct clk_branch pmic_ssbi2_clk = { 2436 .halt_reg = 0x2fd8, 2437 .halt_check = BRANCH_HALT_VOTED, 2438 .halt_bit = 23, 2439 .clkr = { 2440 .enable_reg = 0x3080, 2441 .enable_mask = BIT(7), 2442 .hw.init = &(struct clk_init_data){ 2443 .name = "pmic_ssbi2_clk", 2444 .ops = &clk_branch_ops, 2445 .flags = CLK_IS_ROOT, 2446 }, 2447 }, 2448}; 2449 2450static struct clk_branch rpm_msg_ram_h_clk = { 2451 .hwcg_reg = 0x27e0, 2452 .hwcg_bit = 6, 2453 .halt_reg = 0x2fd8, 2454 .halt_check = BRANCH_HALT_VOTED, 2455 .halt_bit = 12, 2456 .clkr = { 2457 .enable_reg = 0x3080, 2458 .enable_mask = BIT(6), 2459 .hw.init = &(struct clk_init_data){ 2460 .name = "rpm_msg_ram_h_clk", 2461 .ops = &clk_branch_ops, 2462 .flags = CLK_IS_ROOT, 2463 }, 2464 }, 2465}; 2466 2467static struct clk_regmap *gcc_msm8660_clks[] = { 2468 [PLL8] = &pll8.clkr, 2469 [PLL8_VOTE] = &pll8_vote, 2470 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, 2471 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, 2472 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, 2473 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, 2474 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr, 2475 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr, 2476 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, 2477 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, 2478 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, 2479 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, 2480 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, 2481 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, 2482 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 2483 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 2484 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr, 2485 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr, 2486 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr, 2487 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr, 2488 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr, 2489 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr, 2490 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr, 2491 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr, 2492 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr, 2493 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr, 2494 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, 2495 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, 2496 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, 2497 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, 2498 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr, 2499 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr, 2500 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, 2501 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, 2502 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, 2503 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, 2504 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, 2505 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, 2506 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 2507 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 2508 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr, 2509 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr, 2510 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr, 2511 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr, 2512 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr, 2513 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr, 2514 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr, 2515 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr, 2516 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr, 2517 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr, 2518 [GP0_SRC] = &gp0_src.clkr, 2519 [GP0_CLK] = &gp0_clk.clkr, 2520 [GP1_SRC] = &gp1_src.clkr, 2521 [GP1_CLK] = &gp1_clk.clkr, 2522 [GP2_SRC] = &gp2_src.clkr, 2523 [GP2_CLK] = &gp2_clk.clkr, 2524 [PMEM_CLK] = &pmem_clk.clkr, 2525 [PRNG_SRC] = &prng_src.clkr, 2526 [PRNG_CLK] = &prng_clk.clkr, 2527 [SDC1_SRC] = &sdc1_src.clkr, 2528 [SDC1_CLK] = &sdc1_clk.clkr, 2529 [SDC2_SRC] = &sdc2_src.clkr, 2530 [SDC2_CLK] = &sdc2_clk.clkr, 2531 [SDC3_SRC] = &sdc3_src.clkr, 2532 [SDC3_CLK] = &sdc3_clk.clkr, 2533 [SDC4_SRC] = &sdc4_src.clkr, 2534 [SDC4_CLK] = &sdc4_clk.clkr, 2535 [SDC5_SRC] = &sdc5_src.clkr, 2536 [SDC5_CLK] = &sdc5_clk.clkr, 2537 [TSIF_REF_SRC] = &tsif_ref_src.clkr, 2538 [TSIF_REF_CLK] = &tsif_ref_clk.clkr, 2539 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr, 2540 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, 2541 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr, 2542 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr, 2543 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr, 2544 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr, 2545 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr, 2546 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr, 2547 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, 2548 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, 2549 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr, 2550 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, 2551 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, 2552 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, 2553 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 2554 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr, 2555 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr, 2556 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr, 2557 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr, 2558 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr, 2559 [TSIF_H_CLK] = &tsif_h_clk.clkr, 2560 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, 2561 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr, 2562 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, 2563 [SDC1_H_CLK] = &sdc1_h_clk.clkr, 2564 [SDC2_H_CLK] = &sdc2_h_clk.clkr, 2565 [SDC3_H_CLK] = &sdc3_h_clk.clkr, 2566 [SDC4_H_CLK] = &sdc4_h_clk.clkr, 2567 [SDC5_H_CLK] = &sdc5_h_clk.clkr, 2568 [ADM0_CLK] = &adm0_clk.clkr, 2569 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, 2570 [ADM1_CLK] = &adm1_clk.clkr, 2571 [ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr, 2572 [MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr, 2573 [MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr, 2574 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, 2575 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, 2576 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, 2577 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, 2578}; 2579 2580static const struct qcom_reset_map gcc_msm8660_resets[] = { 2581 [AFAB_CORE_RESET] = { 0x2080, 7 }, 2582 [SCSS_SYS_RESET] = { 0x20b4, 1 }, 2583 [SCSS_SYS_POR_RESET] = { 0x20b4 }, 2584 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, 2585 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, 2586 [AFAB_SMPSS_M0_RESET] = { 0x20b8 }, 2587 [AFAB_EBI1_S_RESET] = { 0x20c0, 7 }, 2588 [SFAB_CORE_RESET] = { 0x2120, 7 }, 2589 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, 2590 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, 2591 [SFAB_ADM0_M2_RESET] = { 0x21e4, 7 }, 2592 [ADM0_C2_RESET] = { 0x220c, 4 }, 2593 [ADM0_C1_RESET] = { 0x220c, 3 }, 2594 [ADM0_C0_RESET] = { 0x220c, 2 }, 2595 [ADM0_PBUS_RESET] = { 0x220c, 1 }, 2596 [ADM0_RESET] = { 0x220c }, 2597 [SFAB_ADM1_M0_RESET] = { 0x2220, 7 }, 2598 [SFAB_ADM1_M1_RESET] = { 0x2224, 7 }, 2599 [SFAB_ADM1_M2_RESET] = { 0x2228, 7 }, 2600 [MMFAB_ADM1_M3_RESET] = { 0x2240, 7 }, 2601 [ADM1_C3_RESET] = { 0x226c, 5 }, 2602 [ADM1_C2_RESET] = { 0x226c, 4 }, 2603 [ADM1_C1_RESET] = { 0x226c, 3 }, 2604 [ADM1_C0_RESET] = { 0x226c, 2 }, 2605 [ADM1_PBUS_RESET] = { 0x226c, 1 }, 2606 [ADM1_RESET] = { 0x226c }, 2607 [IMEM0_RESET] = { 0x2280, 7 }, 2608 [SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 }, 2609 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, 2610 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, 2611 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, 2612 [DFAB_CORE_RESET] = { 0x24ac, 7 }, 2613 [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, 2614 [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, 2615 [DFAB_SWAY0_RESET] = { 0x2540, 7 }, 2616 [DFAB_SWAY1_RESET] = { 0x2544, 7 }, 2617 [DFAB_ARB0_RESET] = { 0x2560, 7 }, 2618 [DFAB_ARB1_RESET] = { 0x2564, 7 }, 2619 [PPSS_PROC_RESET] = { 0x2594, 1 }, 2620 [PPSS_RESET] = { 0x2594 }, 2621 [PMEM_RESET] = { 0x25a0, 7 }, 2622 [DMA_BAM_RESET] = { 0x25c0, 7 }, 2623 [SIC_RESET] = { 0x25e0, 7 }, 2624 [SPS_TIC_RESET] = { 0x2600, 7 }, 2625 [CFBP0_RESET] = { 0x2650, 7 }, 2626 [CFBP1_RESET] = { 0x2654, 7 }, 2627 [CFBP2_RESET] = { 0x2658, 7 }, 2628 [EBI2_RESET] = { 0x2664, 7 }, 2629 [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, 2630 [CFPB_MASTER_RESET] = { 0x26a0, 7 }, 2631 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, 2632 [CFPB_SPLITTER_RESET] = { 0x26e0, 7 }, 2633 [TSIF_RESET] = { 0x2700, 7 }, 2634 [CE1_RESET] = { 0x2720, 7 }, 2635 [CE2_RESET] = { 0x2740, 7 }, 2636 [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, 2637 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, 2638 [RPM_PROC_RESET] = { 0x27c0, 7 }, 2639 [RPM_BUS_RESET] = { 0x27c4, 7 }, 2640 [RPM_MSG_RAM_RESET] = { 0x27e0, 7 }, 2641 [PMIC_ARB0_RESET] = { 0x2800, 7 }, 2642 [PMIC_ARB1_RESET] = { 0x2804, 7 }, 2643 [PMIC_SSBI2_RESET] = { 0x280c, 12 }, 2644 [SDC1_RESET] = { 0x2830 }, 2645 [SDC2_RESET] = { 0x2850 }, 2646 [SDC3_RESET] = { 0x2870 }, 2647 [SDC4_RESET] = { 0x2890 }, 2648 [SDC5_RESET] = { 0x28b0 }, 2649 [USB_HS1_RESET] = { 0x2910 }, 2650 [USB_HS2_XCVR_RESET] = { 0x2934, 1 }, 2651 [USB_HS2_RESET] = { 0x2934 }, 2652 [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, 2653 [USB_FS1_RESET] = { 0x2974 }, 2654 [USB_FS2_XCVR_RESET] = { 0x2994, 1 }, 2655 [USB_FS2_RESET] = { 0x2994 }, 2656 [GSBI1_RESET] = { 0x29dc }, 2657 [GSBI2_RESET] = { 0x29fc }, 2658 [GSBI3_RESET] = { 0x2a1c }, 2659 [GSBI4_RESET] = { 0x2a3c }, 2660 [GSBI5_RESET] = { 0x2a5c }, 2661 [GSBI6_RESET] = { 0x2a7c }, 2662 [GSBI7_RESET] = { 0x2a9c }, 2663 [GSBI8_RESET] = { 0x2abc }, 2664 [GSBI9_RESET] = { 0x2adc }, 2665 [GSBI10_RESET] = { 0x2afc }, 2666 [GSBI11_RESET] = { 0x2b1c }, 2667 [GSBI12_RESET] = { 0x2b3c }, 2668 [SPDM_RESET] = { 0x2b6c }, 2669 [SEC_CTRL_RESET] = { 0x2b80, 7 }, 2670 [TLMM_H_RESET] = { 0x2ba0, 7 }, 2671 [TLMM_RESET] = { 0x2ba4, 7 }, 2672 [MARRM_PWRON_RESET] = { 0x2bd4, 1 }, 2673 [MARM_RESET] = { 0x2bd4 }, 2674 [MAHB1_RESET] = { 0x2be4, 7 }, 2675 [SFAB_MSS_S_RESET] = { 0x2c00, 7 }, 2676 [MAHB2_RESET] = { 0x2c20, 7 }, 2677 [MODEM_SW_AHB_RESET] = { 0x2c48, 1 }, 2678 [MODEM_RESET] = { 0x2c48 }, 2679 [SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 }, 2680 [SFAB_MSS_MDM0_RESET] = { 0x2c4c }, 2681 [MSS_SLP_RESET] = { 0x2c60, 7 }, 2682 [MSS_MARM_SAW_RESET] = { 0x2c68, 1 }, 2683 [MSS_WDOG_RESET] = { 0x2c68 }, 2684 [TSSC_RESET] = { 0x2ca0, 7 }, 2685 [PDM_RESET] = { 0x2cc0, 12 }, 2686 [SCSS_CORE0_RESET] = { 0x2d60, 1 }, 2687 [SCSS_CORE0_POR_RESET] = { 0x2d60 }, 2688 [SCSS_CORE1_RESET] = { 0x2d80, 1 }, 2689 [SCSS_CORE1_POR_RESET] = { 0x2d80 }, 2690 [MPM_RESET] = { 0x2da4, 1 }, 2691 [EBI1_1X_DIV_RESET] = { 0x2dec, 9 }, 2692 [EBI1_RESET] = { 0x2dec, 7 }, 2693 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, 2694 [USB_PHY0_RESET] = { 0x2e20 }, 2695 [USB_PHY1_RESET] = { 0x2e40 }, 2696 [PRNG_RESET] = { 0x2e80, 12 }, 2697}; 2698 2699static const struct regmap_config gcc_msm8660_regmap_config = { 2700 .reg_bits = 32, 2701 .reg_stride = 4, 2702 .val_bits = 32, 2703 .max_register = 0x363c, 2704 .fast_io = true, 2705}; 2706 2707static const struct qcom_cc_desc gcc_msm8660_desc = { 2708 .config = &gcc_msm8660_regmap_config, 2709 .clks = gcc_msm8660_clks, 2710 .num_clks = ARRAY_SIZE(gcc_msm8660_clks), 2711 .resets = gcc_msm8660_resets, 2712 .num_resets = ARRAY_SIZE(gcc_msm8660_resets), 2713}; 2714 2715static const struct of_device_id gcc_msm8660_match_table[] = { 2716 { .compatible = "qcom,gcc-msm8660" }, 2717 { } 2718}; 2719MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table); 2720 2721static int gcc_msm8660_probe(struct platform_device *pdev) 2722{ 2723 struct clk *clk; 2724 struct device *dev = &pdev->dev; 2725 2726 /* Temporary until RPM clocks supported */ 2727 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 19200000); 2728 if (IS_ERR(clk)) 2729 return PTR_ERR(clk); 2730 2731 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 27000000); 2732 if (IS_ERR(clk)) 2733 return PTR_ERR(clk); 2734 2735 return qcom_cc_probe(pdev, &gcc_msm8660_desc); 2736} 2737 2738static struct platform_driver gcc_msm8660_driver = { 2739 .probe = gcc_msm8660_probe, 2740 .driver = { 2741 .name = "gcc-msm8660", 2742 .of_match_table = gcc_msm8660_match_table, 2743 }, 2744}; 2745 2746static int __init gcc_msm8660_init(void) 2747{ 2748 return platform_driver_register(&gcc_msm8660_driver); 2749} 2750core_initcall(gcc_msm8660_init); 2751 2752static void __exit gcc_msm8660_exit(void) 2753{ 2754 platform_driver_unregister(&gcc_msm8660_driver); 2755} 2756module_exit(gcc_msm8660_exit); 2757 2758MODULE_DESCRIPTION("GCC MSM 8660 Driver"); 2759MODULE_LICENSE("GPL v2"); 2760MODULE_ALIAS("platform:gcc-msm8660"); 2761