Lines Matching refs:CLK_SET_RATE_PARENT
299 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
305 CLK_SET_RATE_PARENT, 1, in spear320_clk_init()
319 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
326 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
342 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
351 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
360 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
367 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
374 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
381 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear320_clk_init()
430 CLK_SET_RATE_PARENT, 1, 1); in spear3xx_clk_init()
434 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, in spear3xx_clk_init()
446 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear3xx_clk_init()
452 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0, in spear3xx_clk_init()
464 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear3xx_clk_init()
470 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, in spear3xx_clk_init()
479 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear3xx_clk_init()
487 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear3xx_clk_init()
491 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, in spear3xx_clk_init()
499 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, in spear3xx_clk_init()
503 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, in spear3xx_clk_init()
568 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, in spear3xx_clk_init()
644 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, in spear3xx_clk_init()
649 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, in spear3xx_clk_init()
654 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, in spear3xx_clk_init()
659 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, in spear3xx_clk_init()