Lines Matching refs:CLK_SET_RATE_PARENT

889 			CLK_SET_RATE_PARENT, 0),
891 			CLK_SET_RATE_PARENT, 0),
950 		GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
952 		GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
954 		GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
956 		GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
958 		GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
960 		GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
962 		GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
964 		GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
966 		GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
968 		GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
970 		GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
972 		GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
974 		GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
977 		GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
979 		GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
981 		GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
983 		GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
985 		GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
987 		GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
989 		GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
993 			GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
995 			GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
999 			GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
1001 			GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1005 		GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1007 		GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1024 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1181 			GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1183 			GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1185 			GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1187 			GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1189 			GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1191 			GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1193 			GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),