1/* 2 * Copyright 2015 Linaro Limited 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <linux/kernel.h> 15#include <linux/bitops.h> 16#include <linux/err.h> 17#include <linux/platform_device.h> 18#include <linux/module.h> 19#include <linux/of.h> 20#include <linux/of_device.h> 21#include <linux/clk-provider.h> 22#include <linux/regmap.h> 23#include <linux/reset-controller.h> 24 25#include <dt-bindings/clock/qcom,gcc-msm8916.h> 26#include <dt-bindings/reset/qcom,gcc-msm8916.h> 27 28#include "common.h" 29#include "clk-regmap.h" 30#include "clk-pll.h" 31#include "clk-rcg.h" 32#include "clk-branch.h" 33#include "reset.h" 34#include "gdsc.h" 35 36enum { 37 P_XO, 38 P_GPLL0, 39 P_GPLL0_AUX, 40 P_BIMC, 41 P_GPLL1, 42 P_GPLL1_AUX, 43 P_GPLL2, 44 P_GPLL2_AUX, 45 P_SLEEP_CLK, 46 P_DSI0_PHYPLL_BYTE, 47 P_DSI0_PHYPLL_DSI, 48 P_EXT_PRI_I2S, 49 P_EXT_SEC_I2S, 50 P_EXT_MCLK, 51}; 52 53static const struct parent_map gcc_xo_gpll0_map[] = { 54 { P_XO, 0 }, 55 { P_GPLL0, 1 }, 56}; 57 58static const char * const gcc_xo_gpll0[] = { 59 "xo", 60 "gpll0_vote", 61}; 62 63static const struct parent_map gcc_xo_gpll0_bimc_map[] = { 64 { P_XO, 0 }, 65 { P_GPLL0, 1 }, 66 { P_BIMC, 2 }, 67}; 68 69static const char * const gcc_xo_gpll0_bimc[] = { 70 "xo", 71 "gpll0_vote", 72 "bimc_pll_vote", 73}; 74 75static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = { 76 { P_XO, 0 }, 77 { P_GPLL0_AUX, 3 }, 78 { P_GPLL1, 1 }, 79 { P_GPLL2_AUX, 2 }, 80}; 81 82static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = { 83 "xo", 84 "gpll0_vote", 85 "gpll1_vote", 86 "gpll2_vote", 87}; 88 89static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { 90 { P_XO, 0 }, 91 { P_GPLL0, 1 }, 92 { P_GPLL2, 2 }, 93}; 94 95static const char * const gcc_xo_gpll0_gpll2[] = { 96 "xo", 97 "gpll0_vote", 98 "gpll2_vote", 99}; 100 101static const struct parent_map gcc_xo_gpll0a_map[] = { 102 { P_XO, 0 }, 103 { P_GPLL0_AUX, 2 }, 104}; 105 106static const char * const gcc_xo_gpll0a[] = { 107 "xo", 108 "gpll0_vote", 109}; 110 111static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = { 112 { P_XO, 0 }, 113 { P_GPLL0, 1 }, 114 { P_GPLL1_AUX, 2 }, 115 { P_SLEEP_CLK, 6 }, 116}; 117 118static const char * const gcc_xo_gpll0_gpll1a_sleep[] = { 119 "xo", 120 "gpll0_vote", 121 "gpll1_vote", 122 "sleep_clk", 123}; 124 125static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = { 126 { P_XO, 0 }, 127 { P_GPLL0, 1 }, 128 { P_GPLL1_AUX, 2 }, 129}; 130 131static const char * const gcc_xo_gpll0_gpll1a[] = { 132 "xo", 133 "gpll0_vote", 134 "gpll1_vote", 135}; 136 137static const struct parent_map gcc_xo_dsibyte_map[] = { 138 { P_XO, 0, }, 139 { P_DSI0_PHYPLL_BYTE, 2 }, 140}; 141 142static const char * const gcc_xo_dsibyte[] = { 143 "xo", 144 "dsi0pllbyte", 145}; 146 147static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = { 148 { P_XO, 0 }, 149 { P_GPLL0_AUX, 2 }, 150 { P_DSI0_PHYPLL_BYTE, 1 }, 151}; 152 153static const char * const gcc_xo_gpll0a_dsibyte[] = { 154 "xo", 155 "gpll0_vote", 156 "dsi0pllbyte", 157}; 158 159static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = { 160 { P_XO, 0 }, 161 { P_GPLL0, 1 }, 162 { P_DSI0_PHYPLL_DSI, 2 }, 163}; 164 165static const char * const gcc_xo_gpll0_dsiphy[] = { 166 "xo", 167 "gpll0_vote", 168 "dsi0pll", 169}; 170 171static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = { 172 { P_XO, 0 }, 173 { P_GPLL0_AUX, 2 }, 174 { P_DSI0_PHYPLL_DSI, 1 }, 175}; 176 177static const char * const gcc_xo_gpll0a_dsiphy[] = { 178 "xo", 179 "gpll0_vote", 180 "dsi0pll", 181}; 182 183static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = { 184 { P_XO, 0 }, 185 { P_GPLL0_AUX, 1 }, 186 { P_GPLL1, 3 }, 187 { P_GPLL2, 2 }, 188}; 189 190static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = { 191 "xo", 192 "gpll0_vote", 193 "gpll1_vote", 194 "gpll2_vote", 195}; 196 197static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = { 198 { P_XO, 0 }, 199 { P_GPLL0, 1 }, 200 { P_GPLL1, 2 }, 201 { P_SLEEP_CLK, 6 } 202}; 203 204static const char * const gcc_xo_gpll0_gpll1_sleep[] = { 205 "xo", 206 "gpll0_vote", 207 "gpll1_vote", 208 "sleep_clk", 209}; 210 211static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = { 212 { P_XO, 0 }, 213 { P_GPLL1, 1 }, 214 { P_EXT_PRI_I2S, 2 }, 215 { P_EXT_MCLK, 3 }, 216 { P_SLEEP_CLK, 6 } 217}; 218 219static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = { 220 "xo", 221 "gpll1_vote", 222 "ext_pri_i2s", 223 "ext_mclk", 224 "sleep_clk", 225}; 226 227static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = { 228 { P_XO, 0 }, 229 { P_GPLL1, 1 }, 230 { P_EXT_SEC_I2S, 2 }, 231 { P_EXT_MCLK, 3 }, 232 { P_SLEEP_CLK, 6 } 233}; 234 235static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = { 236 "xo", 237 "gpll1_vote", 238 "ext_sec_i2s", 239 "ext_mclk", 240 "sleep_clk", 241}; 242 243static const struct parent_map gcc_xo_sleep_map[] = { 244 { P_XO, 0 }, 245 { P_SLEEP_CLK, 6 } 246}; 247 248static const char * const gcc_xo_sleep[] = { 249 "xo", 250 "sleep_clk", 251}; 252 253static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = { 254 { P_XO, 0 }, 255 { P_GPLL1, 1 }, 256 { P_EXT_MCLK, 2 }, 257 { P_SLEEP_CLK, 6 } 258}; 259 260static const char * const gcc_xo_gpll1_emclk_sleep[] = { 261 "xo", 262 "gpll1_vote", 263 "ext_mclk", 264 "sleep_clk", 265}; 266 267#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 268 269static struct clk_pll gpll0 = { 270 .l_reg = 0x21004, 271 .m_reg = 0x21008, 272 .n_reg = 0x2100c, 273 .config_reg = 0x21014, 274 .mode_reg = 0x21000, 275 .status_reg = 0x2101c, 276 .status_bit = 17, 277 .clkr.hw.init = &(struct clk_init_data){ 278 .name = "gpll0", 279 .parent_names = (const char *[]){ "xo" }, 280 .num_parents = 1, 281 .ops = &clk_pll_ops, 282 }, 283}; 284 285static struct clk_regmap gpll0_vote = { 286 .enable_reg = 0x45000, 287 .enable_mask = BIT(0), 288 .hw.init = &(struct clk_init_data){ 289 .name = "gpll0_vote", 290 .parent_names = (const char *[]){ "gpll0" }, 291 .num_parents = 1, 292 .ops = &clk_pll_vote_ops, 293 }, 294}; 295 296static struct clk_pll gpll1 = { 297 .l_reg = 0x20004, 298 .m_reg = 0x20008, 299 .n_reg = 0x2000c, 300 .config_reg = 0x20014, 301 .mode_reg = 0x20000, 302 .status_reg = 0x2001c, 303 .status_bit = 17, 304 .clkr.hw.init = &(struct clk_init_data){ 305 .name = "gpll1", 306 .parent_names = (const char *[]){ "xo" }, 307 .num_parents = 1, 308 .ops = &clk_pll_ops, 309 }, 310}; 311 312static struct clk_regmap gpll1_vote = { 313 .enable_reg = 0x45000, 314 .enable_mask = BIT(1), 315 .hw.init = &(struct clk_init_data){ 316 .name = "gpll1_vote", 317 .parent_names = (const char *[]){ "gpll1" }, 318 .num_parents = 1, 319 .ops = &clk_pll_vote_ops, 320 }, 321}; 322 323static struct clk_pll gpll2 = { 324 .l_reg = 0x4a004, 325 .m_reg = 0x4a008, 326 .n_reg = 0x4a00c, 327 .config_reg = 0x4a014, 328 .mode_reg = 0x4a000, 329 .status_reg = 0x4a01c, 330 .status_bit = 17, 331 .clkr.hw.init = &(struct clk_init_data){ 332 .name = "gpll2", 333 .parent_names = (const char *[]){ "xo" }, 334 .num_parents = 1, 335 .ops = &clk_pll_ops, 336 }, 337}; 338 339static struct clk_regmap gpll2_vote = { 340 .enable_reg = 0x45000, 341 .enable_mask = BIT(2), 342 .hw.init = &(struct clk_init_data){ 343 .name = "gpll2_vote", 344 .parent_names = (const char *[]){ "gpll2" }, 345 .num_parents = 1, 346 .ops = &clk_pll_vote_ops, 347 }, 348}; 349 350static struct clk_pll bimc_pll = { 351 .l_reg = 0x23004, 352 .m_reg = 0x23008, 353 .n_reg = 0x2300c, 354 .config_reg = 0x23014, 355 .mode_reg = 0x23000, 356 .status_reg = 0x2301c, 357 .status_bit = 17, 358 .clkr.hw.init = &(struct clk_init_data){ 359 .name = "bimc_pll", 360 .parent_names = (const char *[]){ "xo" }, 361 .num_parents = 1, 362 .ops = &clk_pll_ops, 363 }, 364}; 365 366static struct clk_regmap bimc_pll_vote = { 367 .enable_reg = 0x45000, 368 .enable_mask = BIT(3), 369 .hw.init = &(struct clk_init_data){ 370 .name = "bimc_pll_vote", 371 .parent_names = (const char *[]){ "bimc_pll" }, 372 .num_parents = 1, 373 .ops = &clk_pll_vote_ops, 374 }, 375}; 376 377static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 378 .cmd_rcgr = 0x27000, 379 .hid_width = 5, 380 .parent_map = gcc_xo_gpll0_bimc_map, 381 .clkr.hw.init = &(struct clk_init_data){ 382 .name = "pcnoc_bfdcd_clk_src", 383 .parent_names = gcc_xo_gpll0_bimc, 384 .num_parents = 3, 385 .ops = &clk_rcg2_ops, 386 }, 387}; 388 389static struct clk_rcg2 system_noc_bfdcd_clk_src = { 390 .cmd_rcgr = 0x26004, 391 .hid_width = 5, 392 .parent_map = gcc_xo_gpll0_bimc_map, 393 .clkr.hw.init = &(struct clk_init_data){ 394 .name = "system_noc_bfdcd_clk_src", 395 .parent_names = gcc_xo_gpll0_bimc, 396 .num_parents = 3, 397 .ops = &clk_rcg2_ops, 398 }, 399}; 400 401static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = { 402 F(40000000, P_GPLL0, 10, 1, 2), 403 F(80000000, P_GPLL0, 10, 0, 0), 404 { } 405}; 406 407static struct clk_rcg2 camss_ahb_clk_src = { 408 .cmd_rcgr = 0x5a000, 409 .mnd_width = 8, 410 .hid_width = 5, 411 .parent_map = gcc_xo_gpll0_map, 412 .freq_tbl = ftbl_gcc_camss_ahb_clk, 413 .clkr.hw.init = &(struct clk_init_data){ 414 .name = "camss_ahb_clk_src", 415 .parent_names = gcc_xo_gpll0, 416 .num_parents = 2, 417 .ops = &clk_rcg2_ops, 418 }, 419}; 420 421static const struct freq_tbl ftbl_apss_ahb_clk[] = { 422 F(19200000, P_XO, 1, 0, 0), 423 F(50000000, P_GPLL0, 16, 0, 0), 424 F(100000000, P_GPLL0, 8, 0, 0), 425 F(133330000, P_GPLL0, 6, 0, 0), 426 { } 427}; 428 429static struct clk_rcg2 apss_ahb_clk_src = { 430 .cmd_rcgr = 0x46000, 431 .hid_width = 5, 432 .parent_map = gcc_xo_gpll0_map, 433 .freq_tbl = ftbl_apss_ahb_clk, 434 .clkr.hw.init = &(struct clk_init_data){ 435 .name = "apss_ahb_clk_src", 436 .parent_names = gcc_xo_gpll0, 437 .num_parents = 2, 438 .ops = &clk_rcg2_ops, 439 }, 440}; 441 442static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = { 443 F(100000000, P_GPLL0, 8, 0, 0), 444 F(200000000, P_GPLL0, 4, 0, 0), 445 { } 446}; 447 448static struct clk_rcg2 csi0_clk_src = { 449 .cmd_rcgr = 0x4e020, 450 .hid_width = 5, 451 .parent_map = gcc_xo_gpll0_map, 452 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 453 .clkr.hw.init = &(struct clk_init_data){ 454 .name = "csi0_clk_src", 455 .parent_names = gcc_xo_gpll0, 456 .num_parents = 2, 457 .ops = &clk_rcg2_ops, 458 }, 459}; 460 461static struct clk_rcg2 csi1_clk_src = { 462 .cmd_rcgr = 0x4f020, 463 .hid_width = 5, 464 .parent_map = gcc_xo_gpll0_map, 465 .freq_tbl = ftbl_gcc_camss_csi0_1_clk, 466 .clkr.hw.init = &(struct clk_init_data){ 467 .name = "csi1_clk_src", 468 .parent_names = gcc_xo_gpll0, 469 .num_parents = 2, 470 .ops = &clk_rcg2_ops, 471 }, 472}; 473 474static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = { 475 F(19200000, P_XO, 1, 0, 0), 476 F(50000000, P_GPLL0_AUX, 16, 0, 0), 477 F(80000000, P_GPLL0_AUX, 10, 0, 0), 478 F(100000000, P_GPLL0_AUX, 8, 0, 0), 479 F(160000000, P_GPLL0_AUX, 5, 0, 0), 480 F(177780000, P_GPLL0_AUX, 4.5, 0, 0), 481 F(200000000, P_GPLL0_AUX, 4, 0, 0), 482 F(266670000, P_GPLL0_AUX, 3, 0, 0), 483 F(294912000, P_GPLL1, 3, 0, 0), 484 F(310000000, P_GPLL2, 3, 0, 0), 485 F(400000000, P_GPLL0_AUX, 2, 0, 0), 486 { } 487}; 488 489static struct clk_rcg2 gfx3d_clk_src = { 490 .cmd_rcgr = 0x59000, 491 .hid_width = 5, 492 .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map, 493 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk, 494 .clkr.hw.init = &(struct clk_init_data){ 495 .name = "gfx3d_clk_src", 496 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a, 497 .num_parents = 4, 498 .ops = &clk_rcg2_ops, 499 }, 500}; 501 502static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = { 503 F(50000000, P_GPLL0, 16, 0, 0), 504 F(80000000, P_GPLL0, 10, 0, 0), 505 F(100000000, P_GPLL0, 8, 0, 0), 506 F(160000000, P_GPLL0, 5, 0, 0), 507 F(177780000, P_GPLL0, 4.5, 0, 0), 508 F(200000000, P_GPLL0, 4, 0, 0), 509 F(266670000, P_GPLL0, 3, 0, 0), 510 F(320000000, P_GPLL0, 2.5, 0, 0), 511 F(400000000, P_GPLL0, 2, 0, 0), 512 F(465000000, P_GPLL2, 2, 0, 0), 513 { } 514}; 515 516static struct clk_rcg2 vfe0_clk_src = { 517 .cmd_rcgr = 0x58000, 518 .hid_width = 5, 519 .parent_map = gcc_xo_gpll0_gpll2_map, 520 .freq_tbl = ftbl_gcc_camss_vfe0_clk, 521 .clkr.hw.init = &(struct clk_init_data){ 522 .name = "vfe0_clk_src", 523 .parent_names = gcc_xo_gpll0_gpll2, 524 .num_parents = 3, 525 .ops = &clk_rcg2_ops, 526 }, 527}; 528 529static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { 530 F(19200000, P_XO, 1, 0, 0), 531 F(50000000, P_GPLL0, 16, 0, 0), 532 { } 533}; 534 535static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 536 .cmd_rcgr = 0x0200c, 537 .hid_width = 5, 538 .parent_map = gcc_xo_gpll0_map, 539 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 540 .clkr.hw.init = &(struct clk_init_data){ 541 .name = "blsp1_qup1_i2c_apps_clk_src", 542 .parent_names = gcc_xo_gpll0, 543 .num_parents = 2, 544 .ops = &clk_rcg2_ops, 545 }, 546}; 547 548static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { 549 F(960000, P_XO, 10, 1, 2), 550 F(4800000, P_XO, 4, 0, 0), 551 F(9600000, P_XO, 2, 0, 0), 552 F(16000000, P_GPLL0, 10, 1, 5), 553 F(19200000, P_XO, 1, 0, 0), 554 F(25000000, P_GPLL0, 16, 1, 2), 555 F(50000000, P_GPLL0, 16, 0, 0), 556 { } 557}; 558 559static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 560 .cmd_rcgr = 0x02024, 561 .mnd_width = 8, 562 .hid_width = 5, 563 .parent_map = gcc_xo_gpll0_map, 564 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 565 .clkr.hw.init = &(struct clk_init_data){ 566 .name = "blsp1_qup1_spi_apps_clk_src", 567 .parent_names = gcc_xo_gpll0, 568 .num_parents = 2, 569 .ops = &clk_rcg2_ops, 570 }, 571}; 572 573static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 574 .cmd_rcgr = 0x03000, 575 .hid_width = 5, 576 .parent_map = gcc_xo_gpll0_map, 577 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 578 .clkr.hw.init = &(struct clk_init_data){ 579 .name = "blsp1_qup2_i2c_apps_clk_src", 580 .parent_names = gcc_xo_gpll0, 581 .num_parents = 2, 582 .ops = &clk_rcg2_ops, 583 }, 584}; 585 586static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 587 .cmd_rcgr = 0x03014, 588 .mnd_width = 8, 589 .hid_width = 5, 590 .parent_map = gcc_xo_gpll0_map, 591 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 592 .clkr.hw.init = &(struct clk_init_data){ 593 .name = "blsp1_qup2_spi_apps_clk_src", 594 .parent_names = gcc_xo_gpll0, 595 .num_parents = 2, 596 .ops = &clk_rcg2_ops, 597 }, 598}; 599 600static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 601 .cmd_rcgr = 0x04000, 602 .hid_width = 5, 603 .parent_map = gcc_xo_gpll0_map, 604 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 605 .clkr.hw.init = &(struct clk_init_data){ 606 .name = "blsp1_qup3_i2c_apps_clk_src", 607 .parent_names = gcc_xo_gpll0, 608 .num_parents = 2, 609 .ops = &clk_rcg2_ops, 610 }, 611}; 612 613static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 614 .cmd_rcgr = 0x04024, 615 .mnd_width = 8, 616 .hid_width = 5, 617 .parent_map = gcc_xo_gpll0_map, 618 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 619 .clkr.hw.init = &(struct clk_init_data){ 620 .name = "blsp1_qup3_spi_apps_clk_src", 621 .parent_names = gcc_xo_gpll0, 622 .num_parents = 2, 623 .ops = &clk_rcg2_ops, 624 }, 625}; 626 627static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 628 .cmd_rcgr = 0x05000, 629 .hid_width = 5, 630 .parent_map = gcc_xo_gpll0_map, 631 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 632 .clkr.hw.init = &(struct clk_init_data){ 633 .name = "blsp1_qup4_i2c_apps_clk_src", 634 .parent_names = gcc_xo_gpll0, 635 .num_parents = 2, 636 .ops = &clk_rcg2_ops, 637 }, 638}; 639 640static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 641 .cmd_rcgr = 0x05024, 642 .mnd_width = 8, 643 .hid_width = 5, 644 .parent_map = gcc_xo_gpll0_map, 645 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 646 .clkr.hw.init = &(struct clk_init_data){ 647 .name = "blsp1_qup4_spi_apps_clk_src", 648 .parent_names = gcc_xo_gpll0, 649 .num_parents = 2, 650 .ops = &clk_rcg2_ops, 651 }, 652}; 653 654static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 655 .cmd_rcgr = 0x06000, 656 .hid_width = 5, 657 .parent_map = gcc_xo_gpll0_map, 658 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 659 .clkr.hw.init = &(struct clk_init_data){ 660 .name = "blsp1_qup5_i2c_apps_clk_src", 661 .parent_names = gcc_xo_gpll0, 662 .num_parents = 2, 663 .ops = &clk_rcg2_ops, 664 }, 665}; 666 667static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 668 .cmd_rcgr = 0x06024, 669 .mnd_width = 8, 670 .hid_width = 5, 671 .parent_map = gcc_xo_gpll0_map, 672 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 673 .clkr.hw.init = &(struct clk_init_data){ 674 .name = "blsp1_qup5_spi_apps_clk_src", 675 .parent_names = gcc_xo_gpll0, 676 .num_parents = 2, 677 .ops = &clk_rcg2_ops, 678 }, 679}; 680 681static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 682 .cmd_rcgr = 0x07000, 683 .hid_width = 5, 684 .parent_map = gcc_xo_gpll0_map, 685 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, 686 .clkr.hw.init = &(struct clk_init_data){ 687 .name = "blsp1_qup6_i2c_apps_clk_src", 688 .parent_names = gcc_xo_gpll0, 689 .num_parents = 2, 690 .ops = &clk_rcg2_ops, 691 }, 692}; 693 694static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 695 .cmd_rcgr = 0x07024, 696 .mnd_width = 8, 697 .hid_width = 5, 698 .parent_map = gcc_xo_gpll0_map, 699 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, 700 .clkr.hw.init = &(struct clk_init_data){ 701 .name = "blsp1_qup6_spi_apps_clk_src", 702 .parent_names = gcc_xo_gpll0, 703 .num_parents = 2, 704 .ops = &clk_rcg2_ops, 705 }, 706}; 707 708static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { 709 F(3686400, P_GPLL0, 1, 72, 15625), 710 F(7372800, P_GPLL0, 1, 144, 15625), 711 F(14745600, P_GPLL0, 1, 288, 15625), 712 F(16000000, P_GPLL0, 10, 1, 5), 713 F(19200000, P_XO, 1, 0, 0), 714 F(24000000, P_GPLL0, 1, 3, 100), 715 F(25000000, P_GPLL0, 16, 1, 2), 716 F(32000000, P_GPLL0, 1, 1, 25), 717 F(40000000, P_GPLL0, 1, 1, 20), 718 F(46400000, P_GPLL0, 1, 29, 500), 719 F(48000000, P_GPLL0, 1, 3, 50), 720 F(51200000, P_GPLL0, 1, 8, 125), 721 F(56000000, P_GPLL0, 1, 7, 100), 722 F(58982400, P_GPLL0, 1, 1152, 15625), 723 F(60000000, P_GPLL0, 1, 3, 40), 724 { } 725}; 726 727static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 728 .cmd_rcgr = 0x02044, 729 .mnd_width = 16, 730 .hid_width = 5, 731 .parent_map = gcc_xo_gpll0_map, 732 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 733 .clkr.hw.init = &(struct clk_init_data){ 734 .name = "blsp1_uart1_apps_clk_src", 735 .parent_names = gcc_xo_gpll0, 736 .num_parents = 2, 737 .ops = &clk_rcg2_ops, 738 }, 739}; 740 741static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 742 .cmd_rcgr = 0x03034, 743 .mnd_width = 16, 744 .hid_width = 5, 745 .parent_map = gcc_xo_gpll0_map, 746 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, 747 .clkr.hw.init = &(struct clk_init_data){ 748 .name = "blsp1_uart2_apps_clk_src", 749 .parent_names = gcc_xo_gpll0, 750 .num_parents = 2, 751 .ops = &clk_rcg2_ops, 752 }, 753}; 754 755static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = { 756 F(19200000, P_XO, 1, 0, 0), 757 { } 758}; 759 760static struct clk_rcg2 cci_clk_src = { 761 .cmd_rcgr = 0x51000, 762 .mnd_width = 8, 763 .hid_width = 5, 764 .parent_map = gcc_xo_gpll0a_map, 765 .freq_tbl = ftbl_gcc_camss_cci_clk, 766 .clkr.hw.init = &(struct clk_init_data){ 767 .name = "cci_clk_src", 768 .parent_names = gcc_xo_gpll0a, 769 .num_parents = 2, 770 .ops = &clk_rcg2_ops, 771 }, 772}; 773 774static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = { 775 F(100000000, P_GPLL0, 8, 0, 0), 776 F(200000000, P_GPLL0, 4, 0, 0), 777 { } 778}; 779 780static struct clk_rcg2 camss_gp0_clk_src = { 781 .cmd_rcgr = 0x54000, 782 .mnd_width = 8, 783 .hid_width = 5, 784 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 785 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 786 .clkr.hw.init = &(struct clk_init_data){ 787 .name = "camss_gp0_clk_src", 788 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 789 .num_parents = 4, 790 .ops = &clk_rcg2_ops, 791 }, 792}; 793 794static struct clk_rcg2 camss_gp1_clk_src = { 795 .cmd_rcgr = 0x55000, 796 .mnd_width = 8, 797 .hid_width = 5, 798 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 799 .freq_tbl = ftbl_gcc_camss_gp0_1_clk, 800 .clkr.hw.init = &(struct clk_init_data){ 801 .name = "camss_gp1_clk_src", 802 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 803 .num_parents = 4, 804 .ops = &clk_rcg2_ops, 805 }, 806}; 807 808static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = { 809 F(133330000, P_GPLL0, 6, 0, 0), 810 F(266670000, P_GPLL0, 3, 0, 0), 811 F(320000000, P_GPLL0, 2.5, 0, 0), 812 { } 813}; 814 815static struct clk_rcg2 jpeg0_clk_src = { 816 .cmd_rcgr = 0x57000, 817 .hid_width = 5, 818 .parent_map = gcc_xo_gpll0_map, 819 .freq_tbl = ftbl_gcc_camss_jpeg0_clk, 820 .clkr.hw.init = &(struct clk_init_data){ 821 .name = "jpeg0_clk_src", 822 .parent_names = gcc_xo_gpll0, 823 .num_parents = 2, 824 .ops = &clk_rcg2_ops, 825 }, 826}; 827 828static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = { 829 F(9600000, P_XO, 2, 0, 0), 830 F(23880000, P_GPLL0, 1, 2, 67), 831 F(66670000, P_GPLL0, 12, 0, 0), 832 { } 833}; 834 835static struct clk_rcg2 mclk0_clk_src = { 836 .cmd_rcgr = 0x52000, 837 .mnd_width = 8, 838 .hid_width = 5, 839 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 840 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 841 .clkr.hw.init = &(struct clk_init_data){ 842 .name = "mclk0_clk_src", 843 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 844 .num_parents = 4, 845 .ops = &clk_rcg2_ops, 846 }, 847}; 848 849static struct clk_rcg2 mclk1_clk_src = { 850 .cmd_rcgr = 0x53000, 851 .mnd_width = 8, 852 .hid_width = 5, 853 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 854 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk, 855 .clkr.hw.init = &(struct clk_init_data){ 856 .name = "mclk1_clk_src", 857 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 858 .num_parents = 4, 859 .ops = &clk_rcg2_ops, 860 }, 861}; 862 863static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = { 864 F(100000000, P_GPLL0, 8, 0, 0), 865 F(200000000, P_GPLL0, 4, 0, 0), 866 { } 867}; 868 869static struct clk_rcg2 csi0phytimer_clk_src = { 870 .cmd_rcgr = 0x4e000, 871 .hid_width = 5, 872 .parent_map = gcc_xo_gpll0_gpll1a_map, 873 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 874 .clkr.hw.init = &(struct clk_init_data){ 875 .name = "csi0phytimer_clk_src", 876 .parent_names = gcc_xo_gpll0_gpll1a, 877 .num_parents = 3, 878 .ops = &clk_rcg2_ops, 879 }, 880}; 881 882static struct clk_rcg2 csi1phytimer_clk_src = { 883 .cmd_rcgr = 0x4f000, 884 .hid_width = 5, 885 .parent_map = gcc_xo_gpll0_gpll1a_map, 886 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk, 887 .clkr.hw.init = &(struct clk_init_data){ 888 .name = "csi1phytimer_clk_src", 889 .parent_names = gcc_xo_gpll0_gpll1a, 890 .num_parents = 3, 891 .ops = &clk_rcg2_ops, 892 }, 893}; 894 895static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = { 896 F(160000000, P_GPLL0, 5, 0, 0), 897 F(320000000, P_GPLL0, 2.5, 0, 0), 898 F(465000000, P_GPLL2, 2, 0, 0), 899 { } 900}; 901 902static struct clk_rcg2 cpp_clk_src = { 903 .cmd_rcgr = 0x58018, 904 .hid_width = 5, 905 .parent_map = gcc_xo_gpll0_gpll2_map, 906 .freq_tbl = ftbl_gcc_camss_cpp_clk, 907 .clkr.hw.init = &(struct clk_init_data){ 908 .name = "cpp_clk_src", 909 .parent_names = gcc_xo_gpll0_gpll2, 910 .num_parents = 3, 911 .ops = &clk_rcg2_ops, 912 }, 913}; 914 915static const struct freq_tbl ftbl_gcc_crypto_clk[] = { 916 F(50000000, P_GPLL0, 16, 0, 0), 917 F(80000000, P_GPLL0, 10, 0, 0), 918 F(100000000, P_GPLL0, 8, 0, 0), 919 F(160000000, P_GPLL0, 5, 0, 0), 920 { } 921}; 922 923static struct clk_rcg2 crypto_clk_src = { 924 .cmd_rcgr = 0x16004, 925 .hid_width = 5, 926 .parent_map = gcc_xo_gpll0_map, 927 .freq_tbl = ftbl_gcc_crypto_clk, 928 .clkr.hw.init = &(struct clk_init_data){ 929 .name = "crypto_clk_src", 930 .parent_names = gcc_xo_gpll0, 931 .num_parents = 2, 932 .ops = &clk_rcg2_ops, 933 }, 934}; 935 936static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = { 937 F(19200000, P_XO, 1, 0, 0), 938 { } 939}; 940 941static struct clk_rcg2 gp1_clk_src = { 942 .cmd_rcgr = 0x08004, 943 .mnd_width = 8, 944 .hid_width = 5, 945 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 946 .freq_tbl = ftbl_gcc_gp1_3_clk, 947 .clkr.hw.init = &(struct clk_init_data){ 948 .name = "gp1_clk_src", 949 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 950 .num_parents = 3, 951 .ops = &clk_rcg2_ops, 952 }, 953}; 954 955static struct clk_rcg2 gp2_clk_src = { 956 .cmd_rcgr = 0x09004, 957 .mnd_width = 8, 958 .hid_width = 5, 959 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 960 .freq_tbl = ftbl_gcc_gp1_3_clk, 961 .clkr.hw.init = &(struct clk_init_data){ 962 .name = "gp2_clk_src", 963 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 964 .num_parents = 3, 965 .ops = &clk_rcg2_ops, 966 }, 967}; 968 969static struct clk_rcg2 gp3_clk_src = { 970 .cmd_rcgr = 0x0a004, 971 .mnd_width = 8, 972 .hid_width = 5, 973 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map, 974 .freq_tbl = ftbl_gcc_gp1_3_clk, 975 .clkr.hw.init = &(struct clk_init_data){ 976 .name = "gp3_clk_src", 977 .parent_names = gcc_xo_gpll0_gpll1a_sleep, 978 .num_parents = 3, 979 .ops = &clk_rcg2_ops, 980 }, 981}; 982 983static struct clk_rcg2 byte0_clk_src = { 984 .cmd_rcgr = 0x4d044, 985 .hid_width = 5, 986 .parent_map = gcc_xo_gpll0a_dsibyte_map, 987 .clkr.hw.init = &(struct clk_init_data){ 988 .name = "byte0_clk_src", 989 .parent_names = gcc_xo_gpll0a_dsibyte, 990 .num_parents = 3, 991 .ops = &clk_byte2_ops, 992 .flags = CLK_SET_RATE_PARENT, 993 }, 994}; 995 996static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = { 997 F(19200000, P_XO, 1, 0, 0), 998 { } 999}; 1000 1001static struct clk_rcg2 esc0_clk_src = { 1002 .cmd_rcgr = 0x4d05c, 1003 .hid_width = 5, 1004 .parent_map = gcc_xo_dsibyte_map, 1005 .freq_tbl = ftbl_gcc_mdss_esc0_clk, 1006 .clkr.hw.init = &(struct clk_init_data){ 1007 .name = "esc0_clk_src", 1008 .parent_names = gcc_xo_dsibyte, 1009 .num_parents = 2, 1010 .ops = &clk_rcg2_ops, 1011 }, 1012}; 1013 1014static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = { 1015 F(50000000, P_GPLL0, 16, 0, 0), 1016 F(80000000, P_GPLL0, 10, 0, 0), 1017 F(100000000, P_GPLL0, 8, 0, 0), 1018 F(160000000, P_GPLL0, 5, 0, 0), 1019 F(177780000, P_GPLL0, 4.5, 0, 0), 1020 F(200000000, P_GPLL0, 4, 0, 0), 1021 F(266670000, P_GPLL0, 3, 0, 0), 1022 F(320000000, P_GPLL0, 2.5, 0, 0), 1023 { } 1024}; 1025 1026static struct clk_rcg2 mdp_clk_src = { 1027 .cmd_rcgr = 0x4d014, 1028 .hid_width = 5, 1029 .parent_map = gcc_xo_gpll0_dsiphy_map, 1030 .freq_tbl = ftbl_gcc_mdss_mdp_clk, 1031 .clkr.hw.init = &(struct clk_init_data){ 1032 .name = "mdp_clk_src", 1033 .parent_names = gcc_xo_gpll0_dsiphy, 1034 .num_parents = 3, 1035 .ops = &clk_rcg2_ops, 1036 }, 1037}; 1038 1039static struct clk_rcg2 pclk0_clk_src = { 1040 .cmd_rcgr = 0x4d000, 1041 .mnd_width = 8, 1042 .hid_width = 5, 1043 .parent_map = gcc_xo_gpll0a_dsiphy_map, 1044 .clkr.hw.init = &(struct clk_init_data){ 1045 .name = "pclk0_clk_src", 1046 .parent_names = gcc_xo_gpll0a_dsiphy, 1047 .num_parents = 3, 1048 .ops = &clk_pixel_ops, 1049 .flags = CLK_SET_RATE_PARENT, 1050 }, 1051}; 1052 1053static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = { 1054 F(19200000, P_XO, 1, 0, 0), 1055 { } 1056}; 1057 1058static struct clk_rcg2 vsync_clk_src = { 1059 .cmd_rcgr = 0x4d02c, 1060 .hid_width = 5, 1061 .parent_map = gcc_xo_gpll0a_map, 1062 .freq_tbl = ftbl_gcc_mdss_vsync_clk, 1063 .clkr.hw.init = &(struct clk_init_data){ 1064 .name = "vsync_clk_src", 1065 .parent_names = gcc_xo_gpll0a, 1066 .num_parents = 2, 1067 .ops = &clk_rcg2_ops, 1068 }, 1069}; 1070 1071static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { 1072 F(64000000, P_GPLL0, 12.5, 0, 0), 1073 { } 1074}; 1075 1076static struct clk_rcg2 pdm2_clk_src = { 1077 .cmd_rcgr = 0x44010, 1078 .hid_width = 5, 1079 .parent_map = gcc_xo_gpll0_map, 1080 .freq_tbl = ftbl_gcc_pdm2_clk, 1081 .clkr.hw.init = &(struct clk_init_data){ 1082 .name = "pdm2_clk_src", 1083 .parent_names = gcc_xo_gpll0, 1084 .num_parents = 2, 1085 .ops = &clk_rcg2_ops, 1086 }, 1087}; 1088 1089static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = { 1090 F(144000, P_XO, 16, 3, 25), 1091 F(400000, P_XO, 12, 1, 4), 1092 F(20000000, P_GPLL0, 10, 1, 4), 1093 F(25000000, P_GPLL0, 16, 1, 2), 1094 F(50000000, P_GPLL0, 16, 0, 0), 1095 F(100000000, P_GPLL0, 8, 0, 0), 1096 F(177770000, P_GPLL0, 4.5, 0, 0), 1097 { } 1098}; 1099 1100static struct clk_rcg2 sdcc1_apps_clk_src = { 1101 .cmd_rcgr = 0x42004, 1102 .mnd_width = 8, 1103 .hid_width = 5, 1104 .parent_map = gcc_xo_gpll0_map, 1105 .freq_tbl = ftbl_gcc_sdcc1_apps_clk, 1106 .clkr.hw.init = &(struct clk_init_data){ 1107 .name = "sdcc1_apps_clk_src", 1108 .parent_names = gcc_xo_gpll0, 1109 .num_parents = 2, 1110 .ops = &clk_rcg2_ops, 1111 }, 1112}; 1113 1114static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = { 1115 F(144000, P_XO, 16, 3, 25), 1116 F(400000, P_XO, 12, 1, 4), 1117 F(20000000, P_GPLL0, 10, 1, 4), 1118 F(25000000, P_GPLL0, 16, 1, 2), 1119 F(50000000, P_GPLL0, 16, 0, 0), 1120 F(100000000, P_GPLL0, 8, 0, 0), 1121 F(200000000, P_GPLL0, 4, 0, 0), 1122 { } 1123}; 1124 1125static struct clk_rcg2 sdcc2_apps_clk_src = { 1126 .cmd_rcgr = 0x43004, 1127 .mnd_width = 8, 1128 .hid_width = 5, 1129 .parent_map = gcc_xo_gpll0_map, 1130 .freq_tbl = ftbl_gcc_sdcc2_apps_clk, 1131 .clkr.hw.init = &(struct clk_init_data){ 1132 .name = "sdcc2_apps_clk_src", 1133 .parent_names = gcc_xo_gpll0, 1134 .num_parents = 2, 1135 .ops = &clk_rcg2_ops, 1136 }, 1137}; 1138 1139static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = { 1140 F(155000000, P_GPLL2, 6, 0, 0), 1141 F(310000000, P_GPLL2, 3, 0, 0), 1142 F(400000000, P_GPLL0, 2, 0, 0), 1143 { } 1144}; 1145 1146static struct clk_rcg2 apss_tcu_clk_src = { 1147 .cmd_rcgr = 0x1207c, 1148 .hid_width = 5, 1149 .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map, 1150 .freq_tbl = ftbl_gcc_apss_tcu_clk, 1151 .clkr.hw.init = &(struct clk_init_data){ 1152 .name = "apss_tcu_clk_src", 1153 .parent_names = gcc_xo_gpll0a_gpll1_gpll2, 1154 .num_parents = 4, 1155 .ops = &clk_rcg2_ops, 1156 }, 1157}; 1158 1159static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = { 1160 F(19200000, P_XO, 1, 0, 0), 1161 F(100000000, P_GPLL0, 8, 0, 0), 1162 F(200000000, P_GPLL0, 4, 0, 0), 1163 F(266500000, P_BIMC, 4, 0, 0), 1164 F(400000000, P_GPLL0, 2, 0, 0), 1165 F(533000000, P_BIMC, 2, 0, 0), 1166 { } 1167}; 1168 1169static struct clk_rcg2 bimc_gpu_clk_src = { 1170 .cmd_rcgr = 0x31028, 1171 .hid_width = 5, 1172 .parent_map = gcc_xo_gpll0_bimc_map, 1173 .freq_tbl = ftbl_gcc_bimc_gpu_clk, 1174 .clkr.hw.init = &(struct clk_init_data){ 1175 .name = "bimc_gpu_clk_src", 1176 .parent_names = gcc_xo_gpll0_bimc, 1177 .num_parents = 3, 1178 .flags = CLK_GET_RATE_NOCACHE, 1179 .ops = &clk_rcg2_shared_ops, 1180 }, 1181}; 1182 1183static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 1184 F(80000000, P_GPLL0, 10, 0, 0), 1185 { } 1186}; 1187 1188static struct clk_rcg2 usb_hs_system_clk_src = { 1189 .cmd_rcgr = 0x41010, 1190 .hid_width = 5, 1191 .parent_map = gcc_xo_gpll0_map, 1192 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 1193 .clkr.hw.init = &(struct clk_init_data){ 1194 .name = "usb_hs_system_clk_src", 1195 .parent_names = gcc_xo_gpll0, 1196 .num_parents = 2, 1197 .ops = &clk_rcg2_ops, 1198 }, 1199}; 1200 1201static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = { 1202 F(3200000, P_XO, 6, 0, 0), 1203 F(6400000, P_XO, 3, 0, 0), 1204 F(9600000, P_XO, 2, 0, 0), 1205 F(19200000, P_XO, 1, 0, 0), 1206 F(40000000, P_GPLL0, 10, 1, 2), 1207 F(66670000, P_GPLL0, 12, 0, 0), 1208 F(80000000, P_GPLL0, 10, 0, 0), 1209 F(100000000, P_GPLL0, 8, 0, 0), 1210 { } 1211}; 1212 1213static struct clk_rcg2 ultaudio_ahbfabric_clk_src = { 1214 .cmd_rcgr = 0x1c010, 1215 .hid_width = 5, 1216 .mnd_width = 8, 1217 .parent_map = gcc_xo_gpll0_gpll1_sleep_map, 1218 .freq_tbl = ftbl_gcc_ultaudio_ahb_clk, 1219 .clkr.hw.init = &(struct clk_init_data){ 1220 .name = "ultaudio_ahbfabric_clk_src", 1221 .parent_names = gcc_xo_gpll0_gpll1_sleep, 1222 .num_parents = 4, 1223 .ops = &clk_rcg2_ops, 1224 }, 1225}; 1226 1227static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = { 1228 .halt_reg = 0x1c028, 1229 .clkr = { 1230 .enable_reg = 0x1c028, 1231 .enable_mask = BIT(0), 1232 .hw.init = &(struct clk_init_data){ 1233 .name = "gcc_ultaudio_ahbfabric_ixfabric_clk", 1234 .parent_names = (const char *[]){ 1235 "ultaudio_ahbfabric_clk_src", 1236 }, 1237 .num_parents = 1, 1238 .flags = CLK_SET_RATE_PARENT, 1239 .ops = &clk_branch2_ops, 1240 }, 1241 }, 1242}; 1243 1244static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = { 1245 .halt_reg = 0x1c024, 1246 .clkr = { 1247 .enable_reg = 0x1c024, 1248 .enable_mask = BIT(0), 1249 .hw.init = &(struct clk_init_data){ 1250 .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk", 1251 .parent_names = (const char *[]){ 1252 "ultaudio_ahbfabric_clk_src", 1253 }, 1254 .num_parents = 1, 1255 .flags = CLK_SET_RATE_PARENT, 1256 .ops = &clk_branch2_ops, 1257 }, 1258 }, 1259}; 1260 1261static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = { 1262 F(256000, P_XO, 5, 1, 15), 1263 F(512000, P_XO, 5, 2, 15), 1264 F(705600, P_GPLL1, 16, 1, 80), 1265 F(768000, P_XO, 5, 1, 5), 1266 F(800000, P_XO, 5, 5, 24), 1267 F(1024000, P_GPLL1, 14, 1, 63), 1268 F(1152000, P_XO, 1, 3, 50), 1269 F(1411200, P_GPLL1, 16, 1, 40), 1270 F(1536000, P_XO, 1, 2, 25), 1271 F(1600000, P_XO, 12, 0, 0), 1272 F(2048000, P_GPLL1, 9, 1, 49), 1273 F(2400000, P_XO, 8, 0, 0), 1274 F(2822400, P_GPLL1, 16, 1, 20), 1275 F(3072000, P_GPLL1, 14, 1, 21), 1276 F(4096000, P_GPLL1, 9, 2, 49), 1277 F(4800000, P_XO, 4, 0, 0), 1278 F(5644800, P_GPLL1, 16, 1, 10), 1279 F(6144000, P_GPLL1, 7, 1, 21), 1280 F(8192000, P_GPLL1, 9, 4, 49), 1281 F(9600000, P_XO, 2, 0, 0), 1282 F(11289600, P_GPLL1, 16, 1, 5), 1283 F(12288000, P_GPLL1, 7, 2, 21), 1284 { } 1285}; 1286 1287static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = { 1288 .cmd_rcgr = 0x1c054, 1289 .hid_width = 5, 1290 .mnd_width = 8, 1291 .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map, 1292 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1293 .clkr.hw.init = &(struct clk_init_data){ 1294 .name = "ultaudio_lpaif_pri_i2s_clk_src", 1295 .parent_names = gcc_xo_gpll1_epi2s_emclk_sleep, 1296 .num_parents = 5, 1297 .ops = &clk_rcg2_ops, 1298 }, 1299}; 1300 1301static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = { 1302 .halt_reg = 0x1c068, 1303 .clkr = { 1304 .enable_reg = 0x1c068, 1305 .enable_mask = BIT(0), 1306 .hw.init = &(struct clk_init_data){ 1307 .name = "gcc_ultaudio_lpaif_pri_i2s_clk", 1308 .parent_names = (const char *[]){ 1309 "ultaudio_lpaif_pri_i2s_clk_src", 1310 }, 1311 .num_parents = 1, 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316}; 1317 1318static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = { 1319 .cmd_rcgr = 0x1c06c, 1320 .hid_width = 5, 1321 .mnd_width = 8, 1322 .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map, 1323 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1324 .clkr.hw.init = &(struct clk_init_data){ 1325 .name = "ultaudio_lpaif_sec_i2s_clk_src", 1326 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1327 .num_parents = 5, 1328 .ops = &clk_rcg2_ops, 1329 }, 1330}; 1331 1332static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = { 1333 .halt_reg = 0x1c080, 1334 .clkr = { 1335 .enable_reg = 0x1c080, 1336 .enable_mask = BIT(0), 1337 .hw.init = &(struct clk_init_data){ 1338 .name = "gcc_ultaudio_lpaif_sec_i2s_clk", 1339 .parent_names = (const char *[]){ 1340 "ultaudio_lpaif_sec_i2s_clk_src", 1341 }, 1342 .num_parents = 1, 1343 .flags = CLK_SET_RATE_PARENT, 1344 .ops = &clk_branch2_ops, 1345 }, 1346 }, 1347}; 1348 1349static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = { 1350 .cmd_rcgr = 0x1c084, 1351 .hid_width = 5, 1352 .mnd_width = 8, 1353 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1354 .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk, 1355 .clkr.hw.init = &(struct clk_init_data){ 1356 .name = "ultaudio_lpaif_aux_i2s_clk_src", 1357 .parent_names = gcc_xo_gpll1_esi2s_emclk_sleep, 1358 .num_parents = 5, 1359 .ops = &clk_rcg2_ops, 1360 }, 1361}; 1362 1363static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = { 1364 .halt_reg = 0x1c098, 1365 .clkr = { 1366 .enable_reg = 0x1c098, 1367 .enable_mask = BIT(0), 1368 .hw.init = &(struct clk_init_data){ 1369 .name = "gcc_ultaudio_lpaif_aux_i2s_clk", 1370 .parent_names = (const char *[]){ 1371 "ultaudio_lpaif_aux_i2s_clk_src", 1372 }, 1373 .num_parents = 1, 1374 .flags = CLK_SET_RATE_PARENT, 1375 .ops = &clk_branch2_ops, 1376 }, 1377 }, 1378}; 1379 1380static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = { 1381 F(19200000, P_XO, 1, 0, 0), 1382 { } 1383}; 1384 1385static struct clk_rcg2 ultaudio_xo_clk_src = { 1386 .cmd_rcgr = 0x1c034, 1387 .hid_width = 5, 1388 .parent_map = gcc_xo_sleep_map, 1389 .freq_tbl = ftbl_gcc_ultaudio_xo_clk, 1390 .clkr.hw.init = &(struct clk_init_data){ 1391 .name = "ultaudio_xo_clk_src", 1392 .parent_names = gcc_xo_sleep, 1393 .num_parents = 2, 1394 .ops = &clk_rcg2_ops, 1395 }, 1396}; 1397 1398static struct clk_branch gcc_ultaudio_avsync_xo_clk = { 1399 .halt_reg = 0x1c04c, 1400 .clkr = { 1401 .enable_reg = 0x1c04c, 1402 .enable_mask = BIT(0), 1403 .hw.init = &(struct clk_init_data){ 1404 .name = "gcc_ultaudio_avsync_xo_clk", 1405 .parent_names = (const char *[]){ 1406 "ultaudio_xo_clk_src", 1407 }, 1408 .num_parents = 1, 1409 .flags = CLK_SET_RATE_PARENT, 1410 .ops = &clk_branch2_ops, 1411 }, 1412 }, 1413}; 1414 1415static struct clk_branch gcc_ultaudio_stc_xo_clk = { 1416 .halt_reg = 0x1c050, 1417 .clkr = { 1418 .enable_reg = 0x1c050, 1419 .enable_mask = BIT(0), 1420 .hw.init = &(struct clk_init_data){ 1421 .name = "gcc_ultaudio_stc_xo_clk", 1422 .parent_names = (const char *[]){ 1423 "ultaudio_xo_clk_src", 1424 }, 1425 .num_parents = 1, 1426 .flags = CLK_SET_RATE_PARENT, 1427 .ops = &clk_branch2_ops, 1428 }, 1429 }, 1430}; 1431 1432static const struct freq_tbl ftbl_codec_clk[] = { 1433 F(19200000, P_XO, 1, 0, 0), 1434 F(11289600, P_EXT_MCLK, 1, 0, 0), 1435 { } 1436}; 1437 1438static struct clk_rcg2 codec_digcodec_clk_src = { 1439 .cmd_rcgr = 0x1c09c, 1440 .hid_width = 5, 1441 .parent_map = gcc_xo_gpll1_emclk_sleep_map, 1442 .freq_tbl = ftbl_codec_clk, 1443 .clkr.hw.init = &(struct clk_init_data){ 1444 .name = "codec_digcodec_clk_src", 1445 .parent_names = gcc_xo_gpll1_emclk_sleep, 1446 .num_parents = 4, 1447 .ops = &clk_rcg2_ops, 1448 }, 1449}; 1450 1451static struct clk_branch gcc_codec_digcodec_clk = { 1452 .halt_reg = 0x1c0b0, 1453 .clkr = { 1454 .enable_reg = 0x1c0b0, 1455 .enable_mask = BIT(0), 1456 .hw.init = &(struct clk_init_data){ 1457 .name = "gcc_ultaudio_codec_digcodec_clk", 1458 .parent_names = (const char *[]){ 1459 "codec_digcodec_clk_src", 1460 }, 1461 .num_parents = 1, 1462 .flags = CLK_SET_RATE_PARENT, 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466}; 1467 1468static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = { 1469 .halt_reg = 0x1c000, 1470 .clkr = { 1471 .enable_reg = 0x1c000, 1472 .enable_mask = BIT(0), 1473 .hw.init = &(struct clk_init_data){ 1474 .name = "gcc_ultaudio_pcnoc_mport_clk", 1475 .parent_names = (const char *[]){ 1476 "pcnoc_bfdcd_clk_src", 1477 }, 1478 .num_parents = 1, 1479 .ops = &clk_branch2_ops, 1480 }, 1481 }, 1482}; 1483 1484static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = { 1485 .halt_reg = 0x1c004, 1486 .clkr = { 1487 .enable_reg = 0x1c004, 1488 .enable_mask = BIT(0), 1489 .hw.init = &(struct clk_init_data){ 1490 .name = "gcc_ultaudio_pcnoc_sway_clk", 1491 .parent_names = (const char *[]){ 1492 "pcnoc_bfdcd_clk_src", 1493 }, 1494 .num_parents = 1, 1495 .ops = &clk_branch2_ops, 1496 }, 1497 }, 1498}; 1499 1500static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { 1501 F(100000000, P_GPLL0, 8, 0, 0), 1502 F(160000000, P_GPLL0, 5, 0, 0), 1503 F(228570000, P_GPLL0, 3.5, 0, 0), 1504 { } 1505}; 1506 1507static struct clk_rcg2 vcodec0_clk_src = { 1508 .cmd_rcgr = 0x4C000, 1509 .mnd_width = 8, 1510 .hid_width = 5, 1511 .parent_map = gcc_xo_gpll0_map, 1512 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk, 1513 .clkr.hw.init = &(struct clk_init_data){ 1514 .name = "vcodec0_clk_src", 1515 .parent_names = gcc_xo_gpll0, 1516 .num_parents = 2, 1517 .ops = &clk_rcg2_ops, 1518 }, 1519}; 1520 1521static struct clk_branch gcc_blsp1_ahb_clk = { 1522 .halt_reg = 0x01008, 1523 .halt_check = BRANCH_HALT_VOTED, 1524 .clkr = { 1525 .enable_reg = 0x45004, 1526 .enable_mask = BIT(10), 1527 .hw.init = &(struct clk_init_data){ 1528 .name = "gcc_blsp1_ahb_clk", 1529 .parent_names = (const char *[]){ 1530 "pcnoc_bfdcd_clk_src", 1531 }, 1532 .num_parents = 1, 1533 .ops = &clk_branch2_ops, 1534 }, 1535 }, 1536}; 1537 1538static struct clk_branch gcc_blsp1_sleep_clk = { 1539 .halt_reg = 0x01004, 1540 .clkr = { 1541 .enable_reg = 0x01004, 1542 .enable_mask = BIT(0), 1543 .hw.init = &(struct clk_init_data){ 1544 .name = "gcc_blsp1_sleep_clk", 1545 .parent_names = (const char *[]){ 1546 "sleep_clk_src", 1547 }, 1548 .num_parents = 1, 1549 .flags = CLK_SET_RATE_PARENT, 1550 .ops = &clk_branch2_ops, 1551 }, 1552 }, 1553}; 1554 1555static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1556 .halt_reg = 0x02008, 1557 .clkr = { 1558 .enable_reg = 0x02008, 1559 .enable_mask = BIT(0), 1560 .hw.init = &(struct clk_init_data){ 1561 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1562 .parent_names = (const char *[]){ 1563 "blsp1_qup1_i2c_apps_clk_src", 1564 }, 1565 .num_parents = 1, 1566 .flags = CLK_SET_RATE_PARENT, 1567 .ops = &clk_branch2_ops, 1568 }, 1569 }, 1570}; 1571 1572static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1573 .halt_reg = 0x02004, 1574 .clkr = { 1575 .enable_reg = 0x02004, 1576 .enable_mask = BIT(0), 1577 .hw.init = &(struct clk_init_data){ 1578 .name = "gcc_blsp1_qup1_spi_apps_clk", 1579 .parent_names = (const char *[]){ 1580 "blsp1_qup1_spi_apps_clk_src", 1581 }, 1582 .num_parents = 1, 1583 .flags = CLK_SET_RATE_PARENT, 1584 .ops = &clk_branch2_ops, 1585 }, 1586 }, 1587}; 1588 1589static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1590 .halt_reg = 0x03010, 1591 .clkr = { 1592 .enable_reg = 0x03010, 1593 .enable_mask = BIT(0), 1594 .hw.init = &(struct clk_init_data){ 1595 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1596 .parent_names = (const char *[]){ 1597 "blsp1_qup2_i2c_apps_clk_src", 1598 }, 1599 .num_parents = 1, 1600 .flags = CLK_SET_RATE_PARENT, 1601 .ops = &clk_branch2_ops, 1602 }, 1603 }, 1604}; 1605 1606static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1607 .halt_reg = 0x0300c, 1608 .clkr = { 1609 .enable_reg = 0x0300c, 1610 .enable_mask = BIT(0), 1611 .hw.init = &(struct clk_init_data){ 1612 .name = "gcc_blsp1_qup2_spi_apps_clk", 1613 .parent_names = (const char *[]){ 1614 "blsp1_qup2_spi_apps_clk_src", 1615 }, 1616 .num_parents = 1, 1617 .flags = CLK_SET_RATE_PARENT, 1618 .ops = &clk_branch2_ops, 1619 }, 1620 }, 1621}; 1622 1623static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1624 .halt_reg = 0x04020, 1625 .clkr = { 1626 .enable_reg = 0x04020, 1627 .enable_mask = BIT(0), 1628 .hw.init = &(struct clk_init_data){ 1629 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1630 .parent_names = (const char *[]){ 1631 "blsp1_qup3_i2c_apps_clk_src", 1632 }, 1633 .num_parents = 1, 1634 .flags = CLK_SET_RATE_PARENT, 1635 .ops = &clk_branch2_ops, 1636 }, 1637 }, 1638}; 1639 1640static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1641 .halt_reg = 0x0401c, 1642 .clkr = { 1643 .enable_reg = 0x0401c, 1644 .enable_mask = BIT(0), 1645 .hw.init = &(struct clk_init_data){ 1646 .name = "gcc_blsp1_qup3_spi_apps_clk", 1647 .parent_names = (const char *[]){ 1648 "blsp1_qup3_spi_apps_clk_src", 1649 }, 1650 .num_parents = 1, 1651 .flags = CLK_SET_RATE_PARENT, 1652 .ops = &clk_branch2_ops, 1653 }, 1654 }, 1655}; 1656 1657static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1658 .halt_reg = 0x05020, 1659 .clkr = { 1660 .enable_reg = 0x05020, 1661 .enable_mask = BIT(0), 1662 .hw.init = &(struct clk_init_data){ 1663 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1664 .parent_names = (const char *[]){ 1665 "blsp1_qup4_i2c_apps_clk_src", 1666 }, 1667 .num_parents = 1, 1668 .flags = CLK_SET_RATE_PARENT, 1669 .ops = &clk_branch2_ops, 1670 }, 1671 }, 1672}; 1673 1674static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1675 .halt_reg = 0x0501c, 1676 .clkr = { 1677 .enable_reg = 0x0501c, 1678 .enable_mask = BIT(0), 1679 .hw.init = &(struct clk_init_data){ 1680 .name = "gcc_blsp1_qup4_spi_apps_clk", 1681 .parent_names = (const char *[]){ 1682 "blsp1_qup4_spi_apps_clk_src", 1683 }, 1684 .num_parents = 1, 1685 .flags = CLK_SET_RATE_PARENT, 1686 .ops = &clk_branch2_ops, 1687 }, 1688 }, 1689}; 1690 1691static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1692 .halt_reg = 0x06020, 1693 .clkr = { 1694 .enable_reg = 0x06020, 1695 .enable_mask = BIT(0), 1696 .hw.init = &(struct clk_init_data){ 1697 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1698 .parent_names = (const char *[]){ 1699 "blsp1_qup5_i2c_apps_clk_src", 1700 }, 1701 .num_parents = 1, 1702 .flags = CLK_SET_RATE_PARENT, 1703 .ops = &clk_branch2_ops, 1704 }, 1705 }, 1706}; 1707 1708static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1709 .halt_reg = 0x0601c, 1710 .clkr = { 1711 .enable_reg = 0x0601c, 1712 .enable_mask = BIT(0), 1713 .hw.init = &(struct clk_init_data){ 1714 .name = "gcc_blsp1_qup5_spi_apps_clk", 1715 .parent_names = (const char *[]){ 1716 "blsp1_qup5_spi_apps_clk_src", 1717 }, 1718 .num_parents = 1, 1719 .flags = CLK_SET_RATE_PARENT, 1720 .ops = &clk_branch2_ops, 1721 }, 1722 }, 1723}; 1724 1725static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1726 .halt_reg = 0x07020, 1727 .clkr = { 1728 .enable_reg = 0x07020, 1729 .enable_mask = BIT(0), 1730 .hw.init = &(struct clk_init_data){ 1731 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1732 .parent_names = (const char *[]){ 1733 "blsp1_qup6_i2c_apps_clk_src", 1734 }, 1735 .num_parents = 1, 1736 .flags = CLK_SET_RATE_PARENT, 1737 .ops = &clk_branch2_ops, 1738 }, 1739 }, 1740}; 1741 1742static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1743 .halt_reg = 0x0701c, 1744 .clkr = { 1745 .enable_reg = 0x0701c, 1746 .enable_mask = BIT(0), 1747 .hw.init = &(struct clk_init_data){ 1748 .name = "gcc_blsp1_qup6_spi_apps_clk", 1749 .parent_names = (const char *[]){ 1750 "blsp1_qup6_spi_apps_clk_src", 1751 }, 1752 .num_parents = 1, 1753 .flags = CLK_SET_RATE_PARENT, 1754 .ops = &clk_branch2_ops, 1755 }, 1756 }, 1757}; 1758 1759static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1760 .halt_reg = 0x0203c, 1761 .clkr = { 1762 .enable_reg = 0x0203c, 1763 .enable_mask = BIT(0), 1764 .hw.init = &(struct clk_init_data){ 1765 .name = "gcc_blsp1_uart1_apps_clk", 1766 .parent_names = (const char *[]){ 1767 "blsp1_uart1_apps_clk_src", 1768 }, 1769 .num_parents = 1, 1770 .flags = CLK_SET_RATE_PARENT, 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774}; 1775 1776static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1777 .halt_reg = 0x0302c, 1778 .clkr = { 1779 .enable_reg = 0x0302c, 1780 .enable_mask = BIT(0), 1781 .hw.init = &(struct clk_init_data){ 1782 .name = "gcc_blsp1_uart2_apps_clk", 1783 .parent_names = (const char *[]){ 1784 "blsp1_uart2_apps_clk_src", 1785 }, 1786 .num_parents = 1, 1787 .flags = CLK_SET_RATE_PARENT, 1788 .ops = &clk_branch2_ops, 1789 }, 1790 }, 1791}; 1792 1793static struct clk_branch gcc_boot_rom_ahb_clk = { 1794 .halt_reg = 0x1300c, 1795 .halt_check = BRANCH_HALT_VOTED, 1796 .clkr = { 1797 .enable_reg = 0x45004, 1798 .enable_mask = BIT(7), 1799 .hw.init = &(struct clk_init_data){ 1800 .name = "gcc_boot_rom_ahb_clk", 1801 .parent_names = (const char *[]){ 1802 "pcnoc_bfdcd_clk_src", 1803 }, 1804 .num_parents = 1, 1805 .ops = &clk_branch2_ops, 1806 }, 1807 }, 1808}; 1809 1810static struct clk_branch gcc_camss_cci_ahb_clk = { 1811 .halt_reg = 0x5101c, 1812 .clkr = { 1813 .enable_reg = 0x5101c, 1814 .enable_mask = BIT(0), 1815 .hw.init = &(struct clk_init_data){ 1816 .name = "gcc_camss_cci_ahb_clk", 1817 .parent_names = (const char *[]){ 1818 "camss_ahb_clk_src", 1819 }, 1820 .num_parents = 1, 1821 .flags = CLK_SET_RATE_PARENT, 1822 .ops = &clk_branch2_ops, 1823 }, 1824 }, 1825}; 1826 1827static struct clk_branch gcc_camss_cci_clk = { 1828 .halt_reg = 0x51018, 1829 .clkr = { 1830 .enable_reg = 0x51018, 1831 .enable_mask = BIT(0), 1832 .hw.init = &(struct clk_init_data){ 1833 .name = "gcc_camss_cci_clk", 1834 .parent_names = (const char *[]){ 1835 "cci_clk_src", 1836 }, 1837 .num_parents = 1, 1838 .flags = CLK_SET_RATE_PARENT, 1839 .ops = &clk_branch2_ops, 1840 }, 1841 }, 1842}; 1843 1844static struct clk_branch gcc_camss_csi0_ahb_clk = { 1845 .halt_reg = 0x4e040, 1846 .clkr = { 1847 .enable_reg = 0x4e040, 1848 .enable_mask = BIT(0), 1849 .hw.init = &(struct clk_init_data){ 1850 .name = "gcc_camss_csi0_ahb_clk", 1851 .parent_names = (const char *[]){ 1852 "camss_ahb_clk_src", 1853 }, 1854 .num_parents = 1, 1855 .flags = CLK_SET_RATE_PARENT, 1856 .ops = &clk_branch2_ops, 1857 }, 1858 }, 1859}; 1860 1861static struct clk_branch gcc_camss_csi0_clk = { 1862 .halt_reg = 0x4e03c, 1863 .clkr = { 1864 .enable_reg = 0x4e03c, 1865 .enable_mask = BIT(0), 1866 .hw.init = &(struct clk_init_data){ 1867 .name = "gcc_camss_csi0_clk", 1868 .parent_names = (const char *[]){ 1869 "csi0_clk_src", 1870 }, 1871 .num_parents = 1, 1872 .flags = CLK_SET_RATE_PARENT, 1873 .ops = &clk_branch2_ops, 1874 }, 1875 }, 1876}; 1877 1878static struct clk_branch gcc_camss_csi0phy_clk = { 1879 .halt_reg = 0x4e048, 1880 .clkr = { 1881 .enable_reg = 0x4e048, 1882 .enable_mask = BIT(0), 1883 .hw.init = &(struct clk_init_data){ 1884 .name = "gcc_camss_csi0phy_clk", 1885 .parent_names = (const char *[]){ 1886 "csi0_clk_src", 1887 }, 1888 .num_parents = 1, 1889 .flags = CLK_SET_RATE_PARENT, 1890 .ops = &clk_branch2_ops, 1891 }, 1892 }, 1893}; 1894 1895static struct clk_branch gcc_camss_csi0pix_clk = { 1896 .halt_reg = 0x4e058, 1897 .clkr = { 1898 .enable_reg = 0x4e058, 1899 .enable_mask = BIT(0), 1900 .hw.init = &(struct clk_init_data){ 1901 .name = "gcc_camss_csi0pix_clk", 1902 .parent_names = (const char *[]){ 1903 "csi0_clk_src", 1904 }, 1905 .num_parents = 1, 1906 .flags = CLK_SET_RATE_PARENT, 1907 .ops = &clk_branch2_ops, 1908 }, 1909 }, 1910}; 1911 1912static struct clk_branch gcc_camss_csi0rdi_clk = { 1913 .halt_reg = 0x4e050, 1914 .clkr = { 1915 .enable_reg = 0x4e050, 1916 .enable_mask = BIT(0), 1917 .hw.init = &(struct clk_init_data){ 1918 .name = "gcc_camss_csi0rdi_clk", 1919 .parent_names = (const char *[]){ 1920 "csi0_clk_src", 1921 }, 1922 .num_parents = 1, 1923 .flags = CLK_SET_RATE_PARENT, 1924 .ops = &clk_branch2_ops, 1925 }, 1926 }, 1927}; 1928 1929static struct clk_branch gcc_camss_csi1_ahb_clk = { 1930 .halt_reg = 0x4f040, 1931 .clkr = { 1932 .enable_reg = 0x4f040, 1933 .enable_mask = BIT(0), 1934 .hw.init = &(struct clk_init_data){ 1935 .name = "gcc_camss_csi1_ahb_clk", 1936 .parent_names = (const char *[]){ 1937 "camss_ahb_clk_src", 1938 }, 1939 .num_parents = 1, 1940 .flags = CLK_SET_RATE_PARENT, 1941 .ops = &clk_branch2_ops, 1942 }, 1943 }, 1944}; 1945 1946static struct clk_branch gcc_camss_csi1_clk = { 1947 .halt_reg = 0x4f03c, 1948 .clkr = { 1949 .enable_reg = 0x4f03c, 1950 .enable_mask = BIT(0), 1951 .hw.init = &(struct clk_init_data){ 1952 .name = "gcc_camss_csi1_clk", 1953 .parent_names = (const char *[]){ 1954 "csi1_clk_src", 1955 }, 1956 .num_parents = 1, 1957 .flags = CLK_SET_RATE_PARENT, 1958 .ops = &clk_branch2_ops, 1959 }, 1960 }, 1961}; 1962 1963static struct clk_branch gcc_camss_csi1phy_clk = { 1964 .halt_reg = 0x4f048, 1965 .clkr = { 1966 .enable_reg = 0x4f048, 1967 .enable_mask = BIT(0), 1968 .hw.init = &(struct clk_init_data){ 1969 .name = "gcc_camss_csi1phy_clk", 1970 .parent_names = (const char *[]){ 1971 "csi1_clk_src", 1972 }, 1973 .num_parents = 1, 1974 .flags = CLK_SET_RATE_PARENT, 1975 .ops = &clk_branch2_ops, 1976 }, 1977 }, 1978}; 1979 1980static struct clk_branch gcc_camss_csi1pix_clk = { 1981 .halt_reg = 0x4f058, 1982 .clkr = { 1983 .enable_reg = 0x4f058, 1984 .enable_mask = BIT(0), 1985 .hw.init = &(struct clk_init_data){ 1986 .name = "gcc_camss_csi1pix_clk", 1987 .parent_names = (const char *[]){ 1988 "csi1_clk_src", 1989 }, 1990 .num_parents = 1, 1991 .flags = CLK_SET_RATE_PARENT, 1992 .ops = &clk_branch2_ops, 1993 }, 1994 }, 1995}; 1996 1997static struct clk_branch gcc_camss_csi1rdi_clk = { 1998 .halt_reg = 0x4f050, 1999 .clkr = { 2000 .enable_reg = 0x4f050, 2001 .enable_mask = BIT(0), 2002 .hw.init = &(struct clk_init_data){ 2003 .name = "gcc_camss_csi1rdi_clk", 2004 .parent_names = (const char *[]){ 2005 "csi1_clk_src", 2006 }, 2007 .num_parents = 1, 2008 .flags = CLK_SET_RATE_PARENT, 2009 .ops = &clk_branch2_ops, 2010 }, 2011 }, 2012}; 2013 2014static struct clk_branch gcc_camss_csi_vfe0_clk = { 2015 .halt_reg = 0x58050, 2016 .clkr = { 2017 .enable_reg = 0x58050, 2018 .enable_mask = BIT(0), 2019 .hw.init = &(struct clk_init_data){ 2020 .name = "gcc_camss_csi_vfe0_clk", 2021 .parent_names = (const char *[]){ 2022 "vfe0_clk_src", 2023 }, 2024 .num_parents = 1, 2025 .flags = CLK_SET_RATE_PARENT, 2026 .ops = &clk_branch2_ops, 2027 }, 2028 }, 2029}; 2030 2031static struct clk_branch gcc_camss_gp0_clk = { 2032 .halt_reg = 0x54018, 2033 .clkr = { 2034 .enable_reg = 0x54018, 2035 .enable_mask = BIT(0), 2036 .hw.init = &(struct clk_init_data){ 2037 .name = "gcc_camss_gp0_clk", 2038 .parent_names = (const char *[]){ 2039 "camss_gp0_clk_src", 2040 }, 2041 .num_parents = 1, 2042 .flags = CLK_SET_RATE_PARENT, 2043 .ops = &clk_branch2_ops, 2044 }, 2045 }, 2046}; 2047 2048static struct clk_branch gcc_camss_gp1_clk = { 2049 .halt_reg = 0x55018, 2050 .clkr = { 2051 .enable_reg = 0x55018, 2052 .enable_mask = BIT(0), 2053 .hw.init = &(struct clk_init_data){ 2054 .name = "gcc_camss_gp1_clk", 2055 .parent_names = (const char *[]){ 2056 "camss_gp1_clk_src", 2057 }, 2058 .num_parents = 1, 2059 .flags = CLK_SET_RATE_PARENT, 2060 .ops = &clk_branch2_ops, 2061 }, 2062 }, 2063}; 2064 2065static struct clk_branch gcc_camss_ispif_ahb_clk = { 2066 .halt_reg = 0x50004, 2067 .clkr = { 2068 .enable_reg = 0x50004, 2069 .enable_mask = BIT(0), 2070 .hw.init = &(struct clk_init_data){ 2071 .name = "gcc_camss_ispif_ahb_clk", 2072 .parent_names = (const char *[]){ 2073 "camss_ahb_clk_src", 2074 }, 2075 .num_parents = 1, 2076 .flags = CLK_SET_RATE_PARENT, 2077 .ops = &clk_branch2_ops, 2078 }, 2079 }, 2080}; 2081 2082static struct clk_branch gcc_camss_jpeg0_clk = { 2083 .halt_reg = 0x57020, 2084 .clkr = { 2085 .enable_reg = 0x57020, 2086 .enable_mask = BIT(0), 2087 .hw.init = &(struct clk_init_data){ 2088 .name = "gcc_camss_jpeg0_clk", 2089 .parent_names = (const char *[]){ 2090 "jpeg0_clk_src", 2091 }, 2092 .num_parents = 1, 2093 .flags = CLK_SET_RATE_PARENT, 2094 .ops = &clk_branch2_ops, 2095 }, 2096 }, 2097}; 2098 2099static struct clk_branch gcc_camss_jpeg_ahb_clk = { 2100 .halt_reg = 0x57024, 2101 .clkr = { 2102 .enable_reg = 0x57024, 2103 .enable_mask = BIT(0), 2104 .hw.init = &(struct clk_init_data){ 2105 .name = "gcc_camss_jpeg_ahb_clk", 2106 .parent_names = (const char *[]){ 2107 "camss_ahb_clk_src", 2108 }, 2109 .num_parents = 1, 2110 .flags = CLK_SET_RATE_PARENT, 2111 .ops = &clk_branch2_ops, 2112 }, 2113 }, 2114}; 2115 2116static struct clk_branch gcc_camss_jpeg_axi_clk = { 2117 .halt_reg = 0x57028, 2118 .clkr = { 2119 .enable_reg = 0x57028, 2120 .enable_mask = BIT(0), 2121 .hw.init = &(struct clk_init_data){ 2122 .name = "gcc_camss_jpeg_axi_clk", 2123 .parent_names = (const char *[]){ 2124 "system_noc_bfdcd_clk_src", 2125 }, 2126 .num_parents = 1, 2127 .flags = CLK_SET_RATE_PARENT, 2128 .ops = &clk_branch2_ops, 2129 }, 2130 }, 2131}; 2132 2133static struct clk_branch gcc_camss_mclk0_clk = { 2134 .halt_reg = 0x52018, 2135 .clkr = { 2136 .enable_reg = 0x52018, 2137 .enable_mask = BIT(0), 2138 .hw.init = &(struct clk_init_data){ 2139 .name = "gcc_camss_mclk0_clk", 2140 .parent_names = (const char *[]){ 2141 "mclk0_clk_src", 2142 }, 2143 .num_parents = 1, 2144 .flags = CLK_SET_RATE_PARENT, 2145 .ops = &clk_branch2_ops, 2146 }, 2147 }, 2148}; 2149 2150static struct clk_branch gcc_camss_mclk1_clk = { 2151 .halt_reg = 0x53018, 2152 .clkr = { 2153 .enable_reg = 0x53018, 2154 .enable_mask = BIT(0), 2155 .hw.init = &(struct clk_init_data){ 2156 .name = "gcc_camss_mclk1_clk", 2157 .parent_names = (const char *[]){ 2158 "mclk1_clk_src", 2159 }, 2160 .num_parents = 1, 2161 .flags = CLK_SET_RATE_PARENT, 2162 .ops = &clk_branch2_ops, 2163 }, 2164 }, 2165}; 2166 2167static struct clk_branch gcc_camss_micro_ahb_clk = { 2168 .halt_reg = 0x5600c, 2169 .clkr = { 2170 .enable_reg = 0x5600c, 2171 .enable_mask = BIT(0), 2172 .hw.init = &(struct clk_init_data){ 2173 .name = "gcc_camss_micro_ahb_clk", 2174 .parent_names = (const char *[]){ 2175 "camss_ahb_clk_src", 2176 }, 2177 .num_parents = 1, 2178 .flags = CLK_SET_RATE_PARENT, 2179 .ops = &clk_branch2_ops, 2180 }, 2181 }, 2182}; 2183 2184static struct clk_branch gcc_camss_csi0phytimer_clk = { 2185 .halt_reg = 0x4e01c, 2186 .clkr = { 2187 .enable_reg = 0x4e01c, 2188 .enable_mask = BIT(0), 2189 .hw.init = &(struct clk_init_data){ 2190 .name = "gcc_camss_csi0phytimer_clk", 2191 .parent_names = (const char *[]){ 2192 "csi0phytimer_clk_src", 2193 }, 2194 .num_parents = 1, 2195 .flags = CLK_SET_RATE_PARENT, 2196 .ops = &clk_branch2_ops, 2197 }, 2198 }, 2199}; 2200 2201static struct clk_branch gcc_camss_csi1phytimer_clk = { 2202 .halt_reg = 0x4f01c, 2203 .clkr = { 2204 .enable_reg = 0x4f01c, 2205 .enable_mask = BIT(0), 2206 .hw.init = &(struct clk_init_data){ 2207 .name = "gcc_camss_csi1phytimer_clk", 2208 .parent_names = (const char *[]){ 2209 "csi1phytimer_clk_src", 2210 }, 2211 .num_parents = 1, 2212 .flags = CLK_SET_RATE_PARENT, 2213 .ops = &clk_branch2_ops, 2214 }, 2215 }, 2216}; 2217 2218static struct clk_branch gcc_camss_ahb_clk = { 2219 .halt_reg = 0x5a014, 2220 .clkr = { 2221 .enable_reg = 0x5a014, 2222 .enable_mask = BIT(0), 2223 .hw.init = &(struct clk_init_data){ 2224 .name = "gcc_camss_ahb_clk", 2225 .parent_names = (const char *[]){ 2226 "camss_ahb_clk_src", 2227 }, 2228 .num_parents = 1, 2229 .flags = CLK_SET_RATE_PARENT, 2230 .ops = &clk_branch2_ops, 2231 }, 2232 }, 2233}; 2234 2235static struct clk_branch gcc_camss_top_ahb_clk = { 2236 .halt_reg = 0x56004, 2237 .clkr = { 2238 .enable_reg = 0x56004, 2239 .enable_mask = BIT(0), 2240 .hw.init = &(struct clk_init_data){ 2241 .name = "gcc_camss_top_ahb_clk", 2242 .parent_names = (const char *[]){ 2243 "pcnoc_bfdcd_clk_src", 2244 }, 2245 .num_parents = 1, 2246 .flags = CLK_SET_RATE_PARENT, 2247 .ops = &clk_branch2_ops, 2248 }, 2249 }, 2250}; 2251 2252static struct clk_branch gcc_camss_cpp_ahb_clk = { 2253 .halt_reg = 0x58040, 2254 .clkr = { 2255 .enable_reg = 0x58040, 2256 .enable_mask = BIT(0), 2257 .hw.init = &(struct clk_init_data){ 2258 .name = "gcc_camss_cpp_ahb_clk", 2259 .parent_names = (const char *[]){ 2260 "camss_ahb_clk_src", 2261 }, 2262 .num_parents = 1, 2263 .flags = CLK_SET_RATE_PARENT, 2264 .ops = &clk_branch2_ops, 2265 }, 2266 }, 2267}; 2268 2269static struct clk_branch gcc_camss_cpp_clk = { 2270 .halt_reg = 0x5803c, 2271 .clkr = { 2272 .enable_reg = 0x5803c, 2273 .enable_mask = BIT(0), 2274 .hw.init = &(struct clk_init_data){ 2275 .name = "gcc_camss_cpp_clk", 2276 .parent_names = (const char *[]){ 2277 "cpp_clk_src", 2278 }, 2279 .num_parents = 1, 2280 .flags = CLK_SET_RATE_PARENT, 2281 .ops = &clk_branch2_ops, 2282 }, 2283 }, 2284}; 2285 2286static struct clk_branch gcc_camss_vfe0_clk = { 2287 .halt_reg = 0x58038, 2288 .clkr = { 2289 .enable_reg = 0x58038, 2290 .enable_mask = BIT(0), 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "gcc_camss_vfe0_clk", 2293 .parent_names = (const char *[]){ 2294 "vfe0_clk_src", 2295 }, 2296 .num_parents = 1, 2297 .flags = CLK_SET_RATE_PARENT, 2298 .ops = &clk_branch2_ops, 2299 }, 2300 }, 2301}; 2302 2303static struct clk_branch gcc_camss_vfe_ahb_clk = { 2304 .halt_reg = 0x58044, 2305 .clkr = { 2306 .enable_reg = 0x58044, 2307 .enable_mask = BIT(0), 2308 .hw.init = &(struct clk_init_data){ 2309 .name = "gcc_camss_vfe_ahb_clk", 2310 .parent_names = (const char *[]){ 2311 "camss_ahb_clk_src", 2312 }, 2313 .num_parents = 1, 2314 .flags = CLK_SET_RATE_PARENT, 2315 .ops = &clk_branch2_ops, 2316 }, 2317 }, 2318}; 2319 2320static struct clk_branch gcc_camss_vfe_axi_clk = { 2321 .halt_reg = 0x58048, 2322 .clkr = { 2323 .enable_reg = 0x58048, 2324 .enable_mask = BIT(0), 2325 .hw.init = &(struct clk_init_data){ 2326 .name = "gcc_camss_vfe_axi_clk", 2327 .parent_names = (const char *[]){ 2328 "system_noc_bfdcd_clk_src", 2329 }, 2330 .num_parents = 1, 2331 .flags = CLK_SET_RATE_PARENT, 2332 .ops = &clk_branch2_ops, 2333 }, 2334 }, 2335}; 2336 2337static struct clk_branch gcc_crypto_ahb_clk = { 2338 .halt_reg = 0x16024, 2339 .halt_check = BRANCH_HALT_VOTED, 2340 .clkr = { 2341 .enable_reg = 0x45004, 2342 .enable_mask = BIT(0), 2343 .hw.init = &(struct clk_init_data){ 2344 .name = "gcc_crypto_ahb_clk", 2345 .parent_names = (const char *[]){ 2346 "pcnoc_bfdcd_clk_src", 2347 }, 2348 .num_parents = 1, 2349 .flags = CLK_SET_RATE_PARENT, 2350 .ops = &clk_branch2_ops, 2351 }, 2352 }, 2353}; 2354 2355static struct clk_branch gcc_crypto_axi_clk = { 2356 .halt_reg = 0x16020, 2357 .halt_check = BRANCH_HALT_VOTED, 2358 .clkr = { 2359 .enable_reg = 0x45004, 2360 .enable_mask = BIT(1), 2361 .hw.init = &(struct clk_init_data){ 2362 .name = "gcc_crypto_axi_clk", 2363 .parent_names = (const char *[]){ 2364 "pcnoc_bfdcd_clk_src", 2365 }, 2366 .num_parents = 1, 2367 .flags = CLK_SET_RATE_PARENT, 2368 .ops = &clk_branch2_ops, 2369 }, 2370 }, 2371}; 2372 2373static struct clk_branch gcc_crypto_clk = { 2374 .halt_reg = 0x1601c, 2375 .halt_check = BRANCH_HALT_VOTED, 2376 .clkr = { 2377 .enable_reg = 0x45004, 2378 .enable_mask = BIT(2), 2379 .hw.init = &(struct clk_init_data){ 2380 .name = "gcc_crypto_clk", 2381 .parent_names = (const char *[]){ 2382 "crypto_clk_src", 2383 }, 2384 .num_parents = 1, 2385 .flags = CLK_SET_RATE_PARENT, 2386 .ops = &clk_branch2_ops, 2387 }, 2388 }, 2389}; 2390 2391static struct clk_branch gcc_oxili_gmem_clk = { 2392 .halt_reg = 0x59024, 2393 .clkr = { 2394 .enable_reg = 0x59024, 2395 .enable_mask = BIT(0), 2396 .hw.init = &(struct clk_init_data){ 2397 .name = "gcc_oxili_gmem_clk", 2398 .parent_names = (const char *[]){ 2399 "gfx3d_clk_src", 2400 }, 2401 .num_parents = 1, 2402 .flags = CLK_SET_RATE_PARENT, 2403 .ops = &clk_branch2_ops, 2404 }, 2405 }, 2406}; 2407 2408static struct clk_branch gcc_gp1_clk = { 2409 .halt_reg = 0x08000, 2410 .clkr = { 2411 .enable_reg = 0x08000, 2412 .enable_mask = BIT(0), 2413 .hw.init = &(struct clk_init_data){ 2414 .name = "gcc_gp1_clk", 2415 .parent_names = (const char *[]){ 2416 "gp1_clk_src", 2417 }, 2418 .num_parents = 1, 2419 .flags = CLK_SET_RATE_PARENT, 2420 .ops = &clk_branch2_ops, 2421 }, 2422 }, 2423}; 2424 2425static struct clk_branch gcc_gp2_clk = { 2426 .halt_reg = 0x09000, 2427 .clkr = { 2428 .enable_reg = 0x09000, 2429 .enable_mask = BIT(0), 2430 .hw.init = &(struct clk_init_data){ 2431 .name = "gcc_gp2_clk", 2432 .parent_names = (const char *[]){ 2433 "gp2_clk_src", 2434 }, 2435 .num_parents = 1, 2436 .flags = CLK_SET_RATE_PARENT, 2437 .ops = &clk_branch2_ops, 2438 }, 2439 }, 2440}; 2441 2442static struct clk_branch gcc_gp3_clk = { 2443 .halt_reg = 0x0a000, 2444 .clkr = { 2445 .enable_reg = 0x0a000, 2446 .enable_mask = BIT(0), 2447 .hw.init = &(struct clk_init_data){ 2448 .name = "gcc_gp3_clk", 2449 .parent_names = (const char *[]){ 2450 "gp3_clk_src", 2451 }, 2452 .num_parents = 1, 2453 .flags = CLK_SET_RATE_PARENT, 2454 .ops = &clk_branch2_ops, 2455 }, 2456 }, 2457}; 2458 2459static struct clk_branch gcc_mdss_ahb_clk = { 2460 .halt_reg = 0x4d07c, 2461 .clkr = { 2462 .enable_reg = 0x4d07c, 2463 .enable_mask = BIT(0), 2464 .hw.init = &(struct clk_init_data){ 2465 .name = "gcc_mdss_ahb_clk", 2466 .parent_names = (const char *[]){ 2467 "pcnoc_bfdcd_clk_src", 2468 }, 2469 .num_parents = 1, 2470 .flags = CLK_SET_RATE_PARENT, 2471 .ops = &clk_branch2_ops, 2472 }, 2473 }, 2474}; 2475 2476static struct clk_branch gcc_mdss_axi_clk = { 2477 .halt_reg = 0x4d080, 2478 .clkr = { 2479 .enable_reg = 0x4d080, 2480 .enable_mask = BIT(0), 2481 .hw.init = &(struct clk_init_data){ 2482 .name = "gcc_mdss_axi_clk", 2483 .parent_names = (const char *[]){ 2484 "system_noc_bfdcd_clk_src", 2485 }, 2486 .num_parents = 1, 2487 .flags = CLK_SET_RATE_PARENT, 2488 .ops = &clk_branch2_ops, 2489 }, 2490 }, 2491}; 2492 2493static struct clk_branch gcc_mdss_byte0_clk = { 2494 .halt_reg = 0x4d094, 2495 .clkr = { 2496 .enable_reg = 0x4d094, 2497 .enable_mask = BIT(0), 2498 .hw.init = &(struct clk_init_data){ 2499 .name = "gcc_mdss_byte0_clk", 2500 .parent_names = (const char *[]){ 2501 "byte0_clk_src", 2502 }, 2503 .num_parents = 1, 2504 .flags = CLK_SET_RATE_PARENT, 2505 .ops = &clk_branch2_ops, 2506 }, 2507 }, 2508}; 2509 2510static struct clk_branch gcc_mdss_esc0_clk = { 2511 .halt_reg = 0x4d098, 2512 .clkr = { 2513 .enable_reg = 0x4d098, 2514 .enable_mask = BIT(0), 2515 .hw.init = &(struct clk_init_data){ 2516 .name = "gcc_mdss_esc0_clk", 2517 .parent_names = (const char *[]){ 2518 "esc0_clk_src", 2519 }, 2520 .num_parents = 1, 2521 .flags = CLK_SET_RATE_PARENT, 2522 .ops = &clk_branch2_ops, 2523 }, 2524 }, 2525}; 2526 2527static struct clk_branch gcc_mdss_mdp_clk = { 2528 .halt_reg = 0x4D088, 2529 .clkr = { 2530 .enable_reg = 0x4D088, 2531 .enable_mask = BIT(0), 2532 .hw.init = &(struct clk_init_data){ 2533 .name = "gcc_mdss_mdp_clk", 2534 .parent_names = (const char *[]){ 2535 "mdp_clk_src", 2536 }, 2537 .num_parents = 1, 2538 .flags = CLK_SET_RATE_PARENT, 2539 .ops = &clk_branch2_ops, 2540 }, 2541 }, 2542}; 2543 2544static struct clk_branch gcc_mdss_pclk0_clk = { 2545 .halt_reg = 0x4d084, 2546 .clkr = { 2547 .enable_reg = 0x4d084, 2548 .enable_mask = BIT(0), 2549 .hw.init = &(struct clk_init_data){ 2550 .name = "gcc_mdss_pclk0_clk", 2551 .parent_names = (const char *[]){ 2552 "pclk0_clk_src", 2553 }, 2554 .num_parents = 1, 2555 .flags = CLK_SET_RATE_PARENT, 2556 .ops = &clk_branch2_ops, 2557 }, 2558 }, 2559}; 2560 2561static struct clk_branch gcc_mdss_vsync_clk = { 2562 .halt_reg = 0x4d090, 2563 .clkr = { 2564 .enable_reg = 0x4d090, 2565 .enable_mask = BIT(0), 2566 .hw.init = &(struct clk_init_data){ 2567 .name = "gcc_mdss_vsync_clk", 2568 .parent_names = (const char *[]){ 2569 "vsync_clk_src", 2570 }, 2571 .num_parents = 1, 2572 .flags = CLK_SET_RATE_PARENT, 2573 .ops = &clk_branch2_ops, 2574 }, 2575 }, 2576}; 2577 2578static struct clk_branch gcc_mss_cfg_ahb_clk = { 2579 .halt_reg = 0x49000, 2580 .clkr = { 2581 .enable_reg = 0x49000, 2582 .enable_mask = BIT(0), 2583 .hw.init = &(struct clk_init_data){ 2584 .name = "gcc_mss_cfg_ahb_clk", 2585 .parent_names = (const char *[]){ 2586 "pcnoc_bfdcd_clk_src", 2587 }, 2588 .num_parents = 1, 2589 .flags = CLK_SET_RATE_PARENT, 2590 .ops = &clk_branch2_ops, 2591 }, 2592 }, 2593}; 2594 2595static struct clk_branch gcc_oxili_ahb_clk = { 2596 .halt_reg = 0x59028, 2597 .clkr = { 2598 .enable_reg = 0x59028, 2599 .enable_mask = BIT(0), 2600 .hw.init = &(struct clk_init_data){ 2601 .name = "gcc_oxili_ahb_clk", 2602 .parent_names = (const char *[]){ 2603 "pcnoc_bfdcd_clk_src", 2604 }, 2605 .num_parents = 1, 2606 .flags = CLK_SET_RATE_PARENT, 2607 .ops = &clk_branch2_ops, 2608 }, 2609 }, 2610}; 2611 2612static struct clk_branch gcc_oxili_gfx3d_clk = { 2613 .halt_reg = 0x59020, 2614 .clkr = { 2615 .enable_reg = 0x59020, 2616 .enable_mask = BIT(0), 2617 .hw.init = &(struct clk_init_data){ 2618 .name = "gcc_oxili_gfx3d_clk", 2619 .parent_names = (const char *[]){ 2620 "gfx3d_clk_src", 2621 }, 2622 .num_parents = 1, 2623 .flags = CLK_SET_RATE_PARENT, 2624 .ops = &clk_branch2_ops, 2625 }, 2626 }, 2627}; 2628 2629static struct clk_branch gcc_pdm2_clk = { 2630 .halt_reg = 0x4400c, 2631 .clkr = { 2632 .enable_reg = 0x4400c, 2633 .enable_mask = BIT(0), 2634 .hw.init = &(struct clk_init_data){ 2635 .name = "gcc_pdm2_clk", 2636 .parent_names = (const char *[]){ 2637 "pdm2_clk_src", 2638 }, 2639 .num_parents = 1, 2640 .flags = CLK_SET_RATE_PARENT, 2641 .ops = &clk_branch2_ops, 2642 }, 2643 }, 2644}; 2645 2646static struct clk_branch gcc_pdm_ahb_clk = { 2647 .halt_reg = 0x44004, 2648 .clkr = { 2649 .enable_reg = 0x44004, 2650 .enable_mask = BIT(0), 2651 .hw.init = &(struct clk_init_data){ 2652 .name = "gcc_pdm_ahb_clk", 2653 .parent_names = (const char *[]){ 2654 "pcnoc_bfdcd_clk_src", 2655 }, 2656 .num_parents = 1, 2657 .flags = CLK_SET_RATE_PARENT, 2658 .ops = &clk_branch2_ops, 2659 }, 2660 }, 2661}; 2662 2663static struct clk_branch gcc_prng_ahb_clk = { 2664 .halt_reg = 0x13004, 2665 .halt_check = BRANCH_HALT_VOTED, 2666 .clkr = { 2667 .enable_reg = 0x45004, 2668 .enable_mask = BIT(8), 2669 .hw.init = &(struct clk_init_data){ 2670 .name = "gcc_prng_ahb_clk", 2671 .parent_names = (const char *[]){ 2672 "pcnoc_bfdcd_clk_src", 2673 }, 2674 .num_parents = 1, 2675 .ops = &clk_branch2_ops, 2676 }, 2677 }, 2678}; 2679 2680static struct clk_branch gcc_sdcc1_ahb_clk = { 2681 .halt_reg = 0x4201c, 2682 .clkr = { 2683 .enable_reg = 0x4201c, 2684 .enable_mask = BIT(0), 2685 .hw.init = &(struct clk_init_data){ 2686 .name = "gcc_sdcc1_ahb_clk", 2687 .parent_names = (const char *[]){ 2688 "pcnoc_bfdcd_clk_src", 2689 }, 2690 .num_parents = 1, 2691 .flags = CLK_SET_RATE_PARENT, 2692 .ops = &clk_branch2_ops, 2693 }, 2694 }, 2695}; 2696 2697static struct clk_branch gcc_sdcc1_apps_clk = { 2698 .halt_reg = 0x42018, 2699 .clkr = { 2700 .enable_reg = 0x42018, 2701 .enable_mask = BIT(0), 2702 .hw.init = &(struct clk_init_data){ 2703 .name = "gcc_sdcc1_apps_clk", 2704 .parent_names = (const char *[]){ 2705 "sdcc1_apps_clk_src", 2706 }, 2707 .num_parents = 1, 2708 .flags = CLK_SET_RATE_PARENT, 2709 .ops = &clk_branch2_ops, 2710 }, 2711 }, 2712}; 2713 2714static struct clk_branch gcc_sdcc2_ahb_clk = { 2715 .halt_reg = 0x4301c, 2716 .clkr = { 2717 .enable_reg = 0x4301c, 2718 .enable_mask = BIT(0), 2719 .hw.init = &(struct clk_init_data){ 2720 .name = "gcc_sdcc2_ahb_clk", 2721 .parent_names = (const char *[]){ 2722 "pcnoc_bfdcd_clk_src", 2723 }, 2724 .num_parents = 1, 2725 .flags = CLK_SET_RATE_PARENT, 2726 .ops = &clk_branch2_ops, 2727 }, 2728 }, 2729}; 2730 2731static struct clk_branch gcc_sdcc2_apps_clk = { 2732 .halt_reg = 0x43018, 2733 .clkr = { 2734 .enable_reg = 0x43018, 2735 .enable_mask = BIT(0), 2736 .hw.init = &(struct clk_init_data){ 2737 .name = "gcc_sdcc2_apps_clk", 2738 .parent_names = (const char *[]){ 2739 "sdcc2_apps_clk_src", 2740 }, 2741 .num_parents = 1, 2742 .flags = CLK_SET_RATE_PARENT, 2743 .ops = &clk_branch2_ops, 2744 }, 2745 }, 2746}; 2747 2748static struct clk_rcg2 bimc_ddr_clk_src = { 2749 .cmd_rcgr = 0x32004, 2750 .hid_width = 5, 2751 .parent_map = gcc_xo_gpll0_bimc_map, 2752 .clkr.hw.init = &(struct clk_init_data){ 2753 .name = "bimc_ddr_clk_src", 2754 .parent_names = gcc_xo_gpll0_bimc, 2755 .num_parents = 3, 2756 .ops = &clk_rcg2_ops, 2757 .flags = CLK_GET_RATE_NOCACHE, 2758 }, 2759}; 2760 2761static struct clk_branch gcc_apss_tcu_clk = { 2762 .halt_reg = 0x12018, 2763 .clkr = { 2764 .enable_reg = 0x4500c, 2765 .enable_mask = BIT(1), 2766 .hw.init = &(struct clk_init_data){ 2767 .name = "gcc_apss_tcu_clk", 2768 .parent_names = (const char *[]){ 2769 "bimc_ddr_clk_src", 2770 }, 2771 .num_parents = 1, 2772 .ops = &clk_branch2_ops, 2773 }, 2774 }, 2775}; 2776 2777static struct clk_branch gcc_gfx_tcu_clk = { 2778 .halt_reg = 0x12020, 2779 .clkr = { 2780 .enable_reg = 0x4500c, 2781 .enable_mask = BIT(2), 2782 .hw.init = &(struct clk_init_data){ 2783 .name = "gcc_gfx_tcu_clk", 2784 .parent_names = (const char *[]){ 2785 "bimc_ddr_clk_src", 2786 }, 2787 .num_parents = 1, 2788 .ops = &clk_branch2_ops, 2789 }, 2790 }, 2791}; 2792 2793static struct clk_branch gcc_gtcu_ahb_clk = { 2794 .halt_reg = 0x12044, 2795 .clkr = { 2796 .enable_reg = 0x4500c, 2797 .enable_mask = BIT(13), 2798 .hw.init = &(struct clk_init_data){ 2799 .name = "gcc_gtcu_ahb_clk", 2800 .parent_names = (const char *[]){ 2801 "pcnoc_bfdcd_clk_src", 2802 }, 2803 .num_parents = 1, 2804 .flags = CLK_SET_RATE_PARENT, 2805 .ops = &clk_branch2_ops, 2806 }, 2807 }, 2808}; 2809 2810static struct clk_branch gcc_bimc_gfx_clk = { 2811 .halt_reg = 0x31024, 2812 .clkr = { 2813 .enable_reg = 0x31024, 2814 .enable_mask = BIT(0), 2815 .hw.init = &(struct clk_init_data){ 2816 .name = "gcc_bimc_gfx_clk", 2817 .parent_names = (const char *[]){ 2818 "bimc_gpu_clk_src", 2819 }, 2820 .num_parents = 1, 2821 .flags = CLK_SET_RATE_PARENT, 2822 .ops = &clk_branch2_ops, 2823 }, 2824 }, 2825}; 2826 2827static struct clk_branch gcc_bimc_gpu_clk = { 2828 .halt_reg = 0x31040, 2829 .clkr = { 2830 .enable_reg = 0x31040, 2831 .enable_mask = BIT(0), 2832 .hw.init = &(struct clk_init_data){ 2833 .name = "gcc_bimc_gpu_clk", 2834 .parent_names = (const char *[]){ 2835 "bimc_gpu_clk_src", 2836 }, 2837 .num_parents = 1, 2838 .flags = CLK_SET_RATE_PARENT, 2839 .ops = &clk_branch2_ops, 2840 }, 2841 }, 2842}; 2843 2844static struct clk_branch gcc_jpeg_tbu_clk = { 2845 .halt_reg = 0x12034, 2846 .clkr = { 2847 .enable_reg = 0x4500c, 2848 .enable_mask = BIT(10), 2849 .hw.init = &(struct clk_init_data){ 2850 .name = "gcc_jpeg_tbu_clk", 2851 .parent_names = (const char *[]){ 2852 "system_noc_bfdcd_clk_src", 2853 }, 2854 .num_parents = 1, 2855 .flags = CLK_SET_RATE_PARENT, 2856 .ops = &clk_branch2_ops, 2857 }, 2858 }, 2859}; 2860 2861static struct clk_branch gcc_mdp_tbu_clk = { 2862 .halt_reg = 0x1201c, 2863 .clkr = { 2864 .enable_reg = 0x4500c, 2865 .enable_mask = BIT(4), 2866 .hw.init = &(struct clk_init_data){ 2867 .name = "gcc_mdp_tbu_clk", 2868 .parent_names = (const char *[]){ 2869 "system_noc_bfdcd_clk_src", 2870 }, 2871 .num_parents = 1, 2872 .flags = CLK_SET_RATE_PARENT, 2873 .ops = &clk_branch2_ops, 2874 }, 2875 }, 2876}; 2877 2878static struct clk_branch gcc_smmu_cfg_clk = { 2879 .halt_reg = 0x12038, 2880 .clkr = { 2881 .enable_reg = 0x4500c, 2882 .enable_mask = BIT(12), 2883 .hw.init = &(struct clk_init_data){ 2884 .name = "gcc_smmu_cfg_clk", 2885 .parent_names = (const char *[]){ 2886 "pcnoc_bfdcd_clk_src", 2887 }, 2888 .num_parents = 1, 2889 .flags = CLK_SET_RATE_PARENT, 2890 .ops = &clk_branch2_ops, 2891 }, 2892 }, 2893}; 2894 2895static struct clk_branch gcc_venus_tbu_clk = { 2896 .halt_reg = 0x12014, 2897 .clkr = { 2898 .enable_reg = 0x4500c, 2899 .enable_mask = BIT(5), 2900 .hw.init = &(struct clk_init_data){ 2901 .name = "gcc_venus_tbu_clk", 2902 .parent_names = (const char *[]){ 2903 "system_noc_bfdcd_clk_src", 2904 }, 2905 .num_parents = 1, 2906 .flags = CLK_SET_RATE_PARENT, 2907 .ops = &clk_branch2_ops, 2908 }, 2909 }, 2910}; 2911 2912static struct clk_branch gcc_vfe_tbu_clk = { 2913 .halt_reg = 0x1203c, 2914 .clkr = { 2915 .enable_reg = 0x4500c, 2916 .enable_mask = BIT(9), 2917 .hw.init = &(struct clk_init_data){ 2918 .name = "gcc_vfe_tbu_clk", 2919 .parent_names = (const char *[]){ 2920 "system_noc_bfdcd_clk_src", 2921 }, 2922 .num_parents = 1, 2923 .flags = CLK_SET_RATE_PARENT, 2924 .ops = &clk_branch2_ops, 2925 }, 2926 }, 2927}; 2928 2929static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2930 .halt_reg = 0x4102c, 2931 .clkr = { 2932 .enable_reg = 0x4102c, 2933 .enable_mask = BIT(0), 2934 .hw.init = &(struct clk_init_data){ 2935 .name = "gcc_usb2a_phy_sleep_clk", 2936 .parent_names = (const char *[]){ 2937 "sleep_clk_src", 2938 }, 2939 .num_parents = 1, 2940 .flags = CLK_SET_RATE_PARENT, 2941 .ops = &clk_branch2_ops, 2942 }, 2943 }, 2944}; 2945 2946static struct clk_branch gcc_usb_hs_ahb_clk = { 2947 .halt_reg = 0x41008, 2948 .clkr = { 2949 .enable_reg = 0x41008, 2950 .enable_mask = BIT(0), 2951 .hw.init = &(struct clk_init_data){ 2952 .name = "gcc_usb_hs_ahb_clk", 2953 .parent_names = (const char *[]){ 2954 "pcnoc_bfdcd_clk_src", 2955 }, 2956 .num_parents = 1, 2957 .flags = CLK_SET_RATE_PARENT, 2958 .ops = &clk_branch2_ops, 2959 }, 2960 }, 2961}; 2962 2963static struct clk_branch gcc_usb_hs_system_clk = { 2964 .halt_reg = 0x41004, 2965 .clkr = { 2966 .enable_reg = 0x41004, 2967 .enable_mask = BIT(0), 2968 .hw.init = &(struct clk_init_data){ 2969 .name = "gcc_usb_hs_system_clk", 2970 .parent_names = (const char *[]){ 2971 "usb_hs_system_clk_src", 2972 }, 2973 .num_parents = 1, 2974 .flags = CLK_SET_RATE_PARENT, 2975 .ops = &clk_branch2_ops, 2976 }, 2977 }, 2978}; 2979 2980static struct clk_branch gcc_venus0_ahb_clk = { 2981 .halt_reg = 0x4c020, 2982 .clkr = { 2983 .enable_reg = 0x4c020, 2984 .enable_mask = BIT(0), 2985 .hw.init = &(struct clk_init_data){ 2986 .name = "gcc_venus0_ahb_clk", 2987 .parent_names = (const char *[]){ 2988 "pcnoc_bfdcd_clk_src", 2989 }, 2990 .num_parents = 1, 2991 .flags = CLK_SET_RATE_PARENT, 2992 .ops = &clk_branch2_ops, 2993 }, 2994 }, 2995}; 2996 2997static struct clk_branch gcc_venus0_axi_clk = { 2998 .halt_reg = 0x4c024, 2999 .clkr = { 3000 .enable_reg = 0x4c024, 3001 .enable_mask = BIT(0), 3002 .hw.init = &(struct clk_init_data){ 3003 .name = "gcc_venus0_axi_clk", 3004 .parent_names = (const char *[]){ 3005 "system_noc_bfdcd_clk_src", 3006 }, 3007 .num_parents = 1, 3008 .flags = CLK_SET_RATE_PARENT, 3009 .ops = &clk_branch2_ops, 3010 }, 3011 }, 3012}; 3013 3014static struct clk_branch gcc_venus0_vcodec0_clk = { 3015 .halt_reg = 0x4c01c, 3016 .clkr = { 3017 .enable_reg = 0x4c01c, 3018 .enable_mask = BIT(0), 3019 .hw.init = &(struct clk_init_data){ 3020 .name = "gcc_venus0_vcodec0_clk", 3021 .parent_names = (const char *[]){ 3022 "vcodec0_clk_src", 3023 }, 3024 .num_parents = 1, 3025 .flags = CLK_SET_RATE_PARENT, 3026 .ops = &clk_branch2_ops, 3027 }, 3028 }, 3029}; 3030 3031static struct gdsc venus_gdsc = { 3032 .gdscr = 0x4c018, 3033 .pd = { 3034 .name = "venus", 3035 }, 3036 .pwrsts = PWRSTS_OFF_ON, 3037}; 3038 3039static struct gdsc mdss_gdsc = { 3040 .gdscr = 0x4d078, 3041 .pd = { 3042 .name = "mdss", 3043 }, 3044 .pwrsts = PWRSTS_OFF_ON, 3045}; 3046 3047static struct gdsc jpeg_gdsc = { 3048 .gdscr = 0x5701c, 3049 .pd = { 3050 .name = "jpeg", 3051 }, 3052 .pwrsts = PWRSTS_OFF_ON, 3053}; 3054 3055static struct gdsc vfe_gdsc = { 3056 .gdscr = 0x58034, 3057 .pd = { 3058 .name = "vfe", 3059 }, 3060 .pwrsts = PWRSTS_OFF_ON, 3061}; 3062 3063static struct gdsc oxili_gdsc = { 3064 .gdscr = 0x5901c, 3065 .pd = { 3066 .name = "oxili", 3067 }, 3068 .pwrsts = PWRSTS_OFF_ON, 3069}; 3070 3071static struct clk_regmap *gcc_msm8916_clocks[] = { 3072 [GPLL0] = &gpll0.clkr, 3073 [GPLL0_VOTE] = &gpll0_vote, 3074 [BIMC_PLL] = &bimc_pll.clkr, 3075 [BIMC_PLL_VOTE] = &bimc_pll_vote, 3076 [GPLL1] = &gpll1.clkr, 3077 [GPLL1_VOTE] = &gpll1_vote, 3078 [GPLL2] = &gpll2.clkr, 3079 [GPLL2_VOTE] = &gpll2_vote, 3080 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, 3081 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, 3082 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr, 3083 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, 3084 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 3085 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 3086 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 3087 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 3088 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 3089 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 3090 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 3091 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 3092 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 3093 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 3094 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 3095 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 3096 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 3097 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 3098 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 3099 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 3100 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 3101 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 3102 [CCI_CLK_SRC] = &cci_clk_src.clkr, 3103 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 3104 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 3105 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 3106 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 3107 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 3108 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 3109 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 3110 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 3111 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, 3112 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 3113 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 3114 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 3115 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 3116 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 3117 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 3118 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 3119 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 3120 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 3121 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 3122 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 3123 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr, 3124 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 3125 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 3126 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 3127 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 3128 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 3129 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 3130 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 3131 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 3132 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 3133 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 3134 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 3135 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 3136 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 3137 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 3138 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 3139 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 3140 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 3141 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 3142 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3143 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr, 3144 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr, 3145 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, 3146 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, 3147 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr, 3148 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, 3149 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, 3150 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, 3151 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, 3152 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr, 3153 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, 3154 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, 3155 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, 3156 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, 3157 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, 3158 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, 3159 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr, 3160 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr, 3161 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr, 3162 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 3163 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 3164 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr, 3165 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 3166 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, 3167 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr, 3168 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 3169 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr, 3170 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr, 3171 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, 3172 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr, 3173 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr, 3174 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 3175 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 3176 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 3177 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr, 3178 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3179 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3180 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3181 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr, 3182 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr, 3183 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr, 3184 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr, 3185 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr, 3186 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr, 3187 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr, 3188 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 3189 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr, 3190 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr, 3191 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3192 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3193 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 3194 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 3195 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 3196 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3197 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3198 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr, 3199 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr, 3200 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, 3201 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, 3202 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr, 3203 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr, 3204 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 3205 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 3206 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 3207 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr, 3208 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr, 3209 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr, 3210 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, 3211 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, 3212 [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, 3213 [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, 3214 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 3215 [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, 3216 [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr, 3217 [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr, 3218 [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr, 3219 [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr, 3220 [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr, 3221 [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr, 3222 [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr, 3223 [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr, 3224 [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr, 3225 [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr, 3226 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr, 3227 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr, 3228 [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr, 3229 [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr, 3230 [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr, 3231 [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr, 3232}; 3233 3234static struct gdsc *gcc_msm8916_gdscs[] = { 3235 [VENUS_GDSC] = &venus_gdsc, 3236 [MDSS_GDSC] = &mdss_gdsc, 3237 [JPEG_GDSC] = &jpeg_gdsc, 3238 [VFE_GDSC] = &vfe_gdsc, 3239 [OXILI_GDSC] = &oxili_gdsc, 3240}; 3241 3242static const struct qcom_reset_map gcc_msm8916_resets[] = { 3243 [GCC_BLSP1_BCR] = { 0x01000 }, 3244 [GCC_BLSP1_QUP1_BCR] = { 0x02000 }, 3245 [GCC_BLSP1_UART1_BCR] = { 0x02038 }, 3246 [GCC_BLSP1_QUP2_BCR] = { 0x03008 }, 3247 [GCC_BLSP1_UART2_BCR] = { 0x03028 }, 3248 [GCC_BLSP1_QUP3_BCR] = { 0x04018 }, 3249 [GCC_BLSP1_QUP4_BCR] = { 0x05018 }, 3250 [GCC_BLSP1_QUP5_BCR] = { 0x06018 }, 3251 [GCC_BLSP1_QUP6_BCR] = { 0x07018 }, 3252 [GCC_IMEM_BCR] = { 0x0e000 }, 3253 [GCC_SMMU_BCR] = { 0x12000 }, 3254 [GCC_APSS_TCU_BCR] = { 0x12050 }, 3255 [GCC_SMMU_XPU_BCR] = { 0x12054 }, 3256 [GCC_PCNOC_TBU_BCR] = { 0x12058 }, 3257 [GCC_PRNG_BCR] = { 0x13000 }, 3258 [GCC_BOOT_ROM_BCR] = { 0x13008 }, 3259 [GCC_CRYPTO_BCR] = { 0x16000 }, 3260 [GCC_SEC_CTRL_BCR] = { 0x1a000 }, 3261 [GCC_AUDIO_CORE_BCR] = { 0x1c008 }, 3262 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 }, 3263 [GCC_DEHR_BCR] = { 0x1f000 }, 3264 [GCC_SYSTEM_NOC_BCR] = { 0x26000 }, 3265 [GCC_PCNOC_BCR] = { 0x27018 }, 3266 [GCC_TCSR_BCR] = { 0x28000 }, 3267 [GCC_QDSS_BCR] = { 0x29000 }, 3268 [GCC_DCD_BCR] = { 0x2a000 }, 3269 [GCC_MSG_RAM_BCR] = { 0x2b000 }, 3270 [GCC_MPM_BCR] = { 0x2c000 }, 3271 [GCC_SPMI_BCR] = { 0x2e000 }, 3272 [GCC_SPDM_BCR] = { 0x2f000 }, 3273 [GCC_MM_SPDM_BCR] = { 0x2f024 }, 3274 [GCC_BIMC_BCR] = { 0x31000 }, 3275 [GCC_RBCPR_BCR] = { 0x33000 }, 3276 [GCC_TLMM_BCR] = { 0x34000 }, 3277 [GCC_USB_HS_BCR] = { 0x41000 }, 3278 [GCC_USB2A_PHY_BCR] = { 0x41028 }, 3279 [GCC_SDCC1_BCR] = { 0x42000 }, 3280 [GCC_SDCC2_BCR] = { 0x43000 }, 3281 [GCC_PDM_BCR] = { 0x44000 }, 3282 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 }, 3283 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 }, 3284 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 }, 3285 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 }, 3286 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 }, 3287 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 }, 3288 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 }, 3289 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 }, 3290 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 }, 3291 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 }, 3292 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 }, 3293 [GCC_MMSS_BCR] = { 0x4b000 }, 3294 [GCC_VENUS0_BCR] = { 0x4c014 }, 3295 [GCC_MDSS_BCR] = { 0x4d074 }, 3296 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 }, 3297 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 }, 3298 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 }, 3299 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c }, 3300 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 }, 3301 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 }, 3302 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 }, 3303 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 }, 3304 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c }, 3305 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 }, 3306 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 }, 3307 [GCC_CAMSS_CCI_BCR] = { 0x51014 }, 3308 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 }, 3309 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 }, 3310 [GCC_CAMSS_GP0_BCR] = { 0x54014 }, 3311 [GCC_CAMSS_GP1_BCR] = { 0x55014 }, 3312 [GCC_CAMSS_TOP_BCR] = { 0x56000 }, 3313 [GCC_CAMSS_MICRO_BCR] = { 0x56008 }, 3314 [GCC_CAMSS_JPEG_BCR] = { 0x57018 }, 3315 [GCC_CAMSS_VFE_BCR] = { 0x58030 }, 3316 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c }, 3317 [GCC_OXILI_BCR] = { 0x59018 }, 3318 [GCC_GMEM_BCR] = { 0x5902c }, 3319 [GCC_CAMSS_AHB_BCR] = { 0x5a018 }, 3320 [GCC_MDP_TBU_BCR] = { 0x62000 }, 3321 [GCC_GFX_TBU_BCR] = { 0x63000 }, 3322 [GCC_GFX_TCU_BCR] = { 0x64000 }, 3323 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 }, 3324 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 }, 3325 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 }, 3326 [GCC_GTCU_AHB_BCR] = { 0x68000 }, 3327 [GCC_SMMU_CFG_BCR] = { 0x69000 }, 3328 [GCC_VFE_TBU_BCR] = { 0x6a000 }, 3329 [GCC_VENUS_TBU_BCR] = { 0x6b000 }, 3330 [GCC_JPEG_TBU_BCR] = { 0x6c000 }, 3331 [GCC_PRONTO_TBU_BCR] = { 0x6d000 }, 3332 [GCC_SMMU_CATS_BCR] = { 0x7c000 }, 3333}; 3334 3335static const struct regmap_config gcc_msm8916_regmap_config = { 3336 .reg_bits = 32, 3337 .reg_stride = 4, 3338 .val_bits = 32, 3339 .max_register = 0x80000, 3340 .fast_io = true, 3341}; 3342 3343static const struct qcom_cc_desc gcc_msm8916_desc = { 3344 .config = &gcc_msm8916_regmap_config, 3345 .clks = gcc_msm8916_clocks, 3346 .num_clks = ARRAY_SIZE(gcc_msm8916_clocks), 3347 .resets = gcc_msm8916_resets, 3348 .num_resets = ARRAY_SIZE(gcc_msm8916_resets), 3349 .gdscs = gcc_msm8916_gdscs, 3350 .num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs), 3351}; 3352 3353static const struct of_device_id gcc_msm8916_match_table[] = { 3354 { .compatible = "qcom,gcc-msm8916" }, 3355 { } 3356}; 3357MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table); 3358 3359static int gcc_msm8916_probe(struct platform_device *pdev) 3360{ 3361 struct clk *clk; 3362 struct device *dev = &pdev->dev; 3363 3364 /* Temporary until RPM clocks supported */ 3365 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000); 3366 if (IS_ERR(clk)) 3367 return PTR_ERR(clk); 3368 3369 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL, 3370 CLK_IS_ROOT, 32768); 3371 if (IS_ERR(clk)) 3372 return PTR_ERR(clk); 3373 3374 return qcom_cc_probe(pdev, &gcc_msm8916_desc); 3375} 3376 3377static struct platform_driver gcc_msm8916_driver = { 3378 .probe = gcc_msm8916_probe, 3379 .driver = { 3380 .name = "gcc-msm8916", 3381 .of_match_table = gcc_msm8916_match_table, 3382 }, 3383}; 3384 3385static int __init gcc_msm8916_init(void) 3386{ 3387 return platform_driver_register(&gcc_msm8916_driver); 3388} 3389core_initcall(gcc_msm8916_init); 3390 3391static void __exit gcc_msm8916_exit(void) 3392{ 3393 platform_driver_unregister(&gcc_msm8916_driver); 3394} 3395module_exit(gcc_msm8916_exit); 3396 3397MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver"); 3398MODULE_LICENSE("GPL v2"); 3399MODULE_ALIAS("platform:gcc-msm8916"); 3400