1/*
2 * TI Divider Clock
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo <t-kristo@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/slab.h>
20#include <linux/err.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/clk/ti.h>
24#include "clock.h"
25
26#undef pr_fmt
27#define pr_fmt(fmt) "%s: " fmt, __func__
28
29#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
30
31#define div_mask(d)	((1 << ((d)->width)) - 1)
32
33static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
34{
35	unsigned int maxdiv = 0;
36	const struct clk_div_table *clkt;
37
38	for (clkt = table; clkt->div; clkt++)
39		if (clkt->div > maxdiv)
40			maxdiv = clkt->div;
41	return maxdiv;
42}
43
44static unsigned int _get_maxdiv(struct clk_divider *divider)
45{
46	if (divider->flags & CLK_DIVIDER_ONE_BASED)
47		return div_mask(divider);
48	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
49		return 1 << div_mask(divider);
50	if (divider->table)
51		return _get_table_maxdiv(divider->table);
52	return div_mask(divider) + 1;
53}
54
55static unsigned int _get_table_div(const struct clk_div_table *table,
56				   unsigned int val)
57{
58	const struct clk_div_table *clkt;
59
60	for (clkt = table; clkt->div; clkt++)
61		if (clkt->val == val)
62			return clkt->div;
63	return 0;
64}
65
66static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
67{
68	if (divider->flags & CLK_DIVIDER_ONE_BASED)
69		return val;
70	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
71		return 1 << val;
72	if (divider->table)
73		return _get_table_div(divider->table, val);
74	return val + 1;
75}
76
77static unsigned int _get_table_val(const struct clk_div_table *table,
78				   unsigned int div)
79{
80	const struct clk_div_table *clkt;
81
82	for (clkt = table; clkt->div; clkt++)
83		if (clkt->div == div)
84			return clkt->val;
85	return 0;
86}
87
88static unsigned int _get_val(struct clk_divider *divider, u8 div)
89{
90	if (divider->flags & CLK_DIVIDER_ONE_BASED)
91		return div;
92	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
93		return __ffs(div);
94	if (divider->table)
95		return  _get_table_val(divider->table, div);
96	return div - 1;
97}
98
99static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
100						unsigned long parent_rate)
101{
102	struct clk_divider *divider = to_clk_divider(hw);
103	unsigned int div, val;
104
105	val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;
106	val &= div_mask(divider);
107
108	div = _get_div(divider, val);
109	if (!div) {
110		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
111		     "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
112		     clk_hw_get_name(hw));
113		return parent_rate;
114	}
115
116	return DIV_ROUND_UP(parent_rate, div);
117}
118
119/*
120 * The reverse of DIV_ROUND_UP: The maximum number which
121 * divided by m is r
122 */
123#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
124
125static bool _is_valid_table_div(const struct clk_div_table *table,
126				unsigned int div)
127{
128	const struct clk_div_table *clkt;
129
130	for (clkt = table; clkt->div; clkt++)
131		if (clkt->div == div)
132			return true;
133	return false;
134}
135
136static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
137{
138	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
139		return is_power_of_2(div);
140	if (divider->table)
141		return _is_valid_table_div(divider->table, div);
142	return true;
143}
144
145static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
146				  unsigned long *best_parent_rate)
147{
148	struct clk_divider *divider = to_clk_divider(hw);
149	int i, bestdiv = 0;
150	unsigned long parent_rate, best = 0, now, maxdiv;
151	unsigned long parent_rate_saved = *best_parent_rate;
152
153	if (!rate)
154		rate = 1;
155
156	maxdiv = _get_maxdiv(divider);
157
158	if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
159		parent_rate = *best_parent_rate;
160		bestdiv = DIV_ROUND_UP(parent_rate, rate);
161		bestdiv = bestdiv == 0 ? 1 : bestdiv;
162		bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
163		return bestdiv;
164	}
165
166	/*
167	 * The maximum divider we can use without overflowing
168	 * unsigned long in rate * i below
169	 */
170	maxdiv = min(ULONG_MAX / rate, maxdiv);
171
172	for (i = 1; i <= maxdiv; i++) {
173		if (!_is_valid_div(divider, i))
174			continue;
175		if (rate * i == parent_rate_saved) {
176			/*
177			 * It's the most ideal case if the requested rate can be
178			 * divided from parent clock without needing to change
179			 * parent rate, so return the divider immediately.
180			 */
181			*best_parent_rate = parent_rate_saved;
182			return i;
183		}
184		parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
185				MULT_ROUND_UP(rate, i));
186		now = DIV_ROUND_UP(parent_rate, i);
187		if (now <= rate && now > best) {
188			bestdiv = i;
189			best = now;
190			*best_parent_rate = parent_rate;
191		}
192	}
193
194	if (!bestdiv) {
195		bestdiv = _get_maxdiv(divider);
196		*best_parent_rate =
197			clk_hw_round_rate(clk_hw_get_parent(hw), 1);
198	}
199
200	return bestdiv;
201}
202
203static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
204				      unsigned long *prate)
205{
206	int div;
207	div = ti_clk_divider_bestdiv(hw, rate, prate);
208
209	return DIV_ROUND_UP(*prate, div);
210}
211
212static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
213				   unsigned long parent_rate)
214{
215	struct clk_divider *divider;
216	unsigned int div, value;
217	u32 val;
218
219	if (!hw || !rate)
220		return -EINVAL;
221
222	divider = to_clk_divider(hw);
223
224	div = DIV_ROUND_UP(parent_rate, rate);
225	value = _get_val(divider, div);
226
227	if (value > div_mask(divider))
228		value = div_mask(divider);
229
230	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
231		val = div_mask(divider) << (divider->shift + 16);
232	} else {
233		val = ti_clk_ll_ops->clk_readl(divider->reg);
234		val &= ~(div_mask(divider) << divider->shift);
235	}
236	val |= value << divider->shift;
237	ti_clk_ll_ops->clk_writel(val, divider->reg);
238
239	return 0;
240}
241
242const struct clk_ops ti_clk_divider_ops = {
243	.recalc_rate = ti_clk_divider_recalc_rate,
244	.round_rate = ti_clk_divider_round_rate,
245	.set_rate = ti_clk_divider_set_rate,
246};
247
248static struct clk *_register_divider(struct device *dev, const char *name,
249				     const char *parent_name,
250				     unsigned long flags, void __iomem *reg,
251				     u8 shift, u8 width, u8 clk_divider_flags,
252				     const struct clk_div_table *table)
253{
254	struct clk_divider *div;
255	struct clk *clk;
256	struct clk_init_data init;
257
258	if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
259		if (width + shift > 16) {
260			pr_warn("divider value exceeds LOWORD field\n");
261			return ERR_PTR(-EINVAL);
262		}
263	}
264
265	/* allocate the divider */
266	div = kzalloc(sizeof(*div), GFP_KERNEL);
267	if (!div) {
268		pr_err("%s: could not allocate divider clk\n", __func__);
269		return ERR_PTR(-ENOMEM);
270	}
271
272	init.name = name;
273	init.ops = &ti_clk_divider_ops;
274	init.flags = flags | CLK_IS_BASIC;
275	init.parent_names = (parent_name ? &parent_name : NULL);
276	init.num_parents = (parent_name ? 1 : 0);
277
278	/* struct clk_divider assignments */
279	div->reg = reg;
280	div->shift = shift;
281	div->width = width;
282	div->flags = clk_divider_flags;
283	div->hw.init = &init;
284	div->table = table;
285
286	/* register the clock */
287	clk = clk_register(dev, &div->hw);
288
289	if (IS_ERR(clk))
290		kfree(div);
291
292	return clk;
293}
294
295static struct clk_div_table *
296_get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
297{
298	int valid_div = 0;
299	struct clk_div_table *table;
300	int i;
301	int div;
302	u32 val;
303	u8 flags;
304
305	if (!setup->num_dividers) {
306		/* Clk divider table not provided, determine min/max divs */
307		flags = setup->flags;
308
309		if (flags & CLKF_INDEX_STARTS_AT_ONE)
310			val = 1;
311		else
312			val = 0;
313
314		div = 1;
315
316		while (div < setup->max_div) {
317			if (flags & CLKF_INDEX_POWER_OF_TWO)
318				div <<= 1;
319			else
320				div++;
321			val++;
322		}
323
324		*width = fls(val);
325
326		return NULL;
327	}
328
329	for (i = 0; i < setup->num_dividers; i++)
330		if (setup->dividers[i])
331			valid_div++;
332
333	table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
334	if (!table)
335		return ERR_PTR(-ENOMEM);
336
337	valid_div = 0;
338	*width = 0;
339
340	for (i = 0; i < setup->num_dividers; i++)
341		if (setup->dividers[i]) {
342			table[valid_div].div = setup->dividers[i];
343			table[valid_div].val = i;
344			valid_div++;
345			*width = i;
346		}
347
348	*width = fls(*width);
349
350	return table;
351}
352
353struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
354{
355	struct clk_divider *div;
356	struct clk_omap_reg *reg;
357
358	if (!setup)
359		return NULL;
360
361	div = kzalloc(sizeof(*div), GFP_KERNEL);
362	if (!div)
363		return ERR_PTR(-ENOMEM);
364
365	reg = (struct clk_omap_reg *)&div->reg;
366	reg->index = setup->module;
367	reg->offset = setup->reg;
368
369	if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
370		div->flags |= CLK_DIVIDER_ONE_BASED;
371
372	if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
373		div->flags |= CLK_DIVIDER_POWER_OF_TWO;
374
375	div->table = _get_div_table_from_setup(setup, &div->width);
376
377	div->shift = setup->bit_shift;
378
379	return &div->hw;
380}
381
382struct clk *ti_clk_register_divider(struct ti_clk *setup)
383{
384	struct ti_clk_divider *div;
385	struct clk_omap_reg *reg_setup;
386	u32 reg;
387	u8 width;
388	u32 flags = 0;
389	u8 div_flags = 0;
390	struct clk_div_table *table;
391	struct clk *clk;
392
393	div = setup->data;
394
395	reg_setup = (struct clk_omap_reg *)&reg;
396
397	reg_setup->index = div->module;
398	reg_setup->offset = div->reg;
399
400	if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
401		div_flags |= CLK_DIVIDER_ONE_BASED;
402
403	if (div->flags & CLKF_INDEX_POWER_OF_TWO)
404		div_flags |= CLK_DIVIDER_POWER_OF_TWO;
405
406	if (div->flags & CLKF_SET_RATE_PARENT)
407		flags |= CLK_SET_RATE_PARENT;
408
409	table = _get_div_table_from_setup(div, &width);
410	if (IS_ERR(table))
411		return (struct clk *)table;
412
413	clk = _register_divider(NULL, setup->name, div->parent,
414				flags, (void __iomem *)reg, div->bit_shift,
415				width, div_flags, table);
416
417	if (IS_ERR(clk))
418		kfree(table);
419
420	return clk;
421}
422
423static struct clk_div_table *
424__init ti_clk_get_div_table(struct device_node *node)
425{
426	struct clk_div_table *table;
427	const __be32 *divspec;
428	u32 val;
429	u32 num_div;
430	u32 valid_div;
431	int i;
432
433	divspec = of_get_property(node, "ti,dividers", &num_div);
434
435	if (!divspec)
436		return NULL;
437
438	num_div /= 4;
439
440	valid_div = 0;
441
442	/* Determine required size for divider table */
443	for (i = 0; i < num_div; i++) {
444		of_property_read_u32_index(node, "ti,dividers", i, &val);
445		if (val)
446			valid_div++;
447	}
448
449	if (!valid_div) {
450		pr_err("no valid dividers for %s table\n", node->name);
451		return ERR_PTR(-EINVAL);
452	}
453
454	table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
455
456	if (!table)
457		return ERR_PTR(-ENOMEM);
458
459	valid_div = 0;
460
461	for (i = 0; i < num_div; i++) {
462		of_property_read_u32_index(node, "ti,dividers", i, &val);
463		if (val) {
464			table[valid_div].div = val;
465			table[valid_div].val = i;
466			valid_div++;
467		}
468	}
469
470	return table;
471}
472
473static int _get_divider_width(struct device_node *node,
474			      const struct clk_div_table *table,
475			      u8 flags)
476{
477	u32 min_div;
478	u32 max_div;
479	u32 val = 0;
480	u32 div;
481
482	if (!table) {
483		/* Clk divider table not provided, determine min/max divs */
484		if (of_property_read_u32(node, "ti,min-div", &min_div))
485			min_div = 1;
486
487		if (of_property_read_u32(node, "ti,max-div", &max_div)) {
488			pr_err("no max-div for %s!\n", node->name);
489			return -EINVAL;
490		}
491
492		/* Determine bit width for the field */
493		if (flags & CLK_DIVIDER_ONE_BASED)
494			val = 1;
495
496		div = min_div;
497
498		while (div < max_div) {
499			if (flags & CLK_DIVIDER_POWER_OF_TWO)
500				div <<= 1;
501			else
502				div++;
503			val++;
504		}
505	} else {
506		div = 0;
507
508		while (table[div].div) {
509			val = table[div].val;
510			div++;
511		}
512	}
513
514	return fls(val);
515}
516
517static int __init ti_clk_divider_populate(struct device_node *node,
518	void __iomem **reg, const struct clk_div_table **table,
519	u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
520{
521	u32 val;
522
523	*reg = ti_clk_get_reg_addr(node, 0);
524	if (IS_ERR(*reg))
525		return PTR_ERR(*reg);
526
527	if (!of_property_read_u32(node, "ti,bit-shift", &val))
528		*shift = val;
529	else
530		*shift = 0;
531
532	*flags = 0;
533	*div_flags = 0;
534
535	if (of_property_read_bool(node, "ti,index-starts-at-one"))
536		*div_flags |= CLK_DIVIDER_ONE_BASED;
537
538	if (of_property_read_bool(node, "ti,index-power-of-two"))
539		*div_flags |= CLK_DIVIDER_POWER_OF_TWO;
540
541	if (of_property_read_bool(node, "ti,set-rate-parent"))
542		*flags |= CLK_SET_RATE_PARENT;
543
544	*table = ti_clk_get_div_table(node);
545
546	if (IS_ERR(*table))
547		return PTR_ERR(*table);
548
549	*width = _get_divider_width(node, *table, *div_flags);
550
551	return 0;
552}
553
554/**
555 * of_ti_divider_clk_setup - Setup function for simple div rate clock
556 * @node: device node for this clock
557 *
558 * Sets up a basic divider clock.
559 */
560static void __init of_ti_divider_clk_setup(struct device_node *node)
561{
562	struct clk *clk;
563	const char *parent_name;
564	void __iomem *reg;
565	u8 clk_divider_flags = 0;
566	u8 width = 0;
567	u8 shift = 0;
568	const struct clk_div_table *table = NULL;
569	u32 flags = 0;
570
571	parent_name = of_clk_get_parent_name(node, 0);
572
573	if (ti_clk_divider_populate(node, &reg, &table, &flags,
574				    &clk_divider_flags, &width, &shift))
575		goto cleanup;
576
577	clk = _register_divider(NULL, node->name, parent_name, flags, reg,
578				shift, width, clk_divider_flags, table);
579
580	if (!IS_ERR(clk)) {
581		of_clk_add_provider(node, of_clk_src_simple_get, clk);
582		of_ti_clk_autoidle_setup(node);
583		return;
584	}
585
586cleanup:
587	kfree(table);
588}
589CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
590
591static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
592{
593	struct clk_divider *div;
594	u32 val;
595
596	div = kzalloc(sizeof(*div), GFP_KERNEL);
597	if (!div)
598		return;
599
600	if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
601				    &div->flags, &div->width, &div->shift) < 0)
602		goto cleanup;
603
604	if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
605		return;
606
607cleanup:
608	kfree(div->table);
609	kfree(div);
610}
611CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
612	       of_ti_composite_divider_clk_setup);
613