Lines Matching refs:CLK_SET_RATE_PARENT

403 		CLK_SET_RATE_PARENT, 0),
480 CLK_SET_RATE_PARENT, 0),
487 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
490 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
500 CLK_SET_RATE_PARENT, 0),
505 CLK_SET_RATE_PARENT, 0),
508 CLK_SET_RATE_PARENT, 0),
513 CLK_SET_RATE_PARENT, 0),
515 CLK_SET_RATE_PARENT, 0),
525 CLK_SET_RATE_PARENT, 0),
528 CLK_SET_RATE_PARENT, 0),
533 CLK_SET_RATE_PARENT, 0),
673 CLK_SET_RATE_PARENT, 0),
676 10, CLK_SET_RATE_PARENT, 0),
678 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
680 GATE_SCLK_CAM, 7, CLK_SET_RATE_PARENT, 0),
682 GATE_SCLK_CAM, 6, CLK_SET_RATE_PARENT, 0),
684 GATE_SCLK_CAM, 5, CLK_SET_RATE_PARENT, 0),
686 GATE_SCLK_CAM, 3, CLK_SET_RATE_PARENT, 0),
688 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
690 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
692 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
696 GATE_SCLK_TV, 3, CLK_SET_RATE_PARENT, 0),
698 GATE_SCLK_TV, 2, CLK_SET_RATE_PARENT, 0),
700 GATE_SCLK_TV, 0, CLK_SET_RATE_PARENT, 0),
704 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
708 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
712 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
714 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
716 GATE_SCLK_LCD, 1, CLK_SET_RATE_PARENT, 0),
718 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
722 GATE_SCLK_MAUDIO, 1, CLK_SET_RATE_PARENT, 0),
724 GATE_SCLK_MAUDIO, 0, CLK_SET_RATE_PARENT, 0),
728 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
730 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
732 GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
734 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
736 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
740 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
742 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
744 GATE_SCLK_PERIL, 15, CLK_SET_RATE_PARENT, 0),
746 GATE_SCLK_PERIL, 14, CLK_SET_RATE_PARENT, 0),
748 GATE_SCLK_PERIL, 13, CLK_SET_RATE_PARENT, 0),
750 GATE_SCLK_PERIL, 10, CLK_SET_RATE_PARENT, 0),
752 GATE_SCLK_PERIL, 8, CLK_SET_RATE_PARENT, 0),
754 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
756 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
758 GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
760 GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
762 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
764 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),